End Semester Examination, Autumn’17 Full Mark: 50, Department of Electronics and Communication Engg, Time: 3hts. National Institute of Technology, ROURKELA ‘Sub: Reconfigurable IC Design (EC-623) Class: M-Tech, 1sem , Dual Degree, 7" Sem (VLSI & ESD) Answer any five question including Q.6 Figures in the right hand margin indicate marks. ‘This question paper contains 2 pages [QNo. 7 Marks T | a, | Design a Verilog model for a2 bit counter that will count from 00 t0 99 and display | 5+5 the output in seven segment displays. Verify the functionality using a suitable test bench. > | a | Describe the IC design flow. List both Front end and Back end flow of IC design. ) 5+5 b. | Explain how the parameters can be overridden in module instantiation. 3 |, | Design a FSM and Write its HDL coding. The sj ,ecifications of the designs are as jae : 545 given: The circuit is a positive edge triggered, has one input X and one output Y. ‘The output Y =1 in the same clock cycle when the alternate occurrence of X=I is detected. - b,_| Write atest bench to verify the functionality of the above FSM. a What is hold violation? Explain methods of fixing hold violation in sequential 1s 4 a. | circuit 545 p,_| Verify ifthe given figure has setup and hold violations. Also specify a method to fix these violations. The timing model for the diagram is as follows: Setup = 8ns, hold= 3 ns, clock period=10ns, Tck2Q delay Ins, Net delays=Ons, Tinv=I ns. D D FFL Q |__| I CLK 2 i S| 8re a 9 -Rm oe Find out the maximum frequency of clock for the given block diagram. Taig= 11 ns T=4ns Ti=2ns aaM6 | Differentiate between different programmable devices. Is ASIC a programmable | device? How ASICs are different from FPGA? | What is the difference between Verilog and VHDL? What is the difference between transport and inertial delays? What does “timescale 1 ns/ 100 ps signify in a verilog code? What tran: What is the width of a time register. If Z=4°1101 then &Z equals ? Which directive is used to include entire content of Verilog source Into another file. What is the difference between $setup and $hold? What is level se ion happens in @posedge syntax. ve timing control in Verilog? If there is mismatch in connecting wire such as A[7:0] = B[15:0],What will be the final result. 10