A B C D E

1 1

Compal confidential 2

Schematics Document
Mobile Merom uFCPGA with Intel
3
Crestline + ICH8-M core logic 3

IBT00 LA-3262P Discrete VGA (M64)

2007-08-02 REV:1A

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 1 of 57
A B C D E
 A B C D E

Compal confidential
File Name : LA-3262P
Chimay Discrete
Thermal Sensor Mobile Merom
1 1
ADM1032ARMZ
uFCPGA-478 CPU
P4

P4, 5, 6 CK505
Fan conn Clock Generator
P4 H_A#(3..35)
CRT & TV OUT FSB ICS 9LPRS355
H_D#(0..63) 667/800MHz 1.05V
P16
DDR2 667MHz 1.8V DDR2-SO-DIMM X2 P15
BANK 0, 1, 2, 3 P13, 14

LVDS Panel Interface Intel Crestline MCH

P17 Dual Channel
ATI M64S PCIE (PM) FCBGA 1299
USB conn x2
P33
DVI (Docking) P18, 19, 20, 21, 22, 23 P7, 8, 9, 10, 11, 12 (Docking)
P33
2 2
FingerPrinter AES1610
DMI X4 C-Link USBx1 P34 daughter board

USB conn x3
USB2.0
PCI-E BUS P34

Intel ICH8-M Azalia

BT Conn
P28
CardBus Controller & PCMCIA conn PCI mBGA-676 SATA Master
10/100/1000 LAN Mini-Card PATA Slave
Mini-Card WWAN
P24, 25, 26, 27
Intel 82566MM P25 Ricoh R5C853 P25
P29 P31 MDC
P38
SPI Audio CKT
AD1981HD P32 AMP & Audio Jack
Slot 0/Smart Card MAX9710
RJ45/11 CONN P33
3 P30 3

SPI ROM & Debug port SATA HDD Connector

1394 port 6in1 Slot
P28 P33
P34 16Mb*2 or 32Mb*1 Docking CONN.
LED P36
P30
*RJ-45(LED*2)
Multi-bay II Connector *RJ-11(Pass Through)
daughter board P28 *CRT
LPC BUS *COMPOSITE Video Out
RTC CKT. *TVOUT
P19 *DVI
*LINE IN
*LINE OUT
TPM1.2 SMSC Super I/O *PCI-E x2
Power OK CKT. SMSC KBC 1070 *Serial Port
P35
SLB9635TT LPC47N217 P35 *Parallel Port
P36 P37 *PS/2 x2
*USB x2
4 Int.KBD COM1 LPT *DC JACK 4
Power On/Off CKT. Touch Pad CONN. ( Docking ) ( Docking )
P33 P33
P32 P38 P38

TrackPoint CONN. Security Classification Compal Secret Data Compal Electronics, Inc.
P38 2006/09/25 2006/09/25 Title
DC/DC Interface CKT. Issued Date Deciphered Date
Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P34 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 2 of 57
A B C D E
 A

O MEANS ON X MEANS OFF

Voltage Rails IRQ Device

+5VS 0 System Timer

+3VS
power 1 Keyboard
plane +2.5VS
+1.8VS 2 N/A
+B
+1.5VS
LDO3 +5VALW +1.8V +3VM
CLOCK 3 Serial port (COM2),LAN/Modem
+1.25VS
LDO5 +3VALW +5V +1.05VM
+VGA_CORE 4 Serial port (COM1)
+0.9V
+CPU_CORE +1.25VM
State 5 Audio/VGA
+VCCP
6 Floppy

7 Parallel port
S0 O O O O O O
8 System CMOS/Real-time clock

S3/M1
O O O O O 9 Microsoft ACPI
X
10 N/A,Momem,LAN
S3
O O O X O O
11 Mass strorage control/ PCI simple communication control
S5 S4/AC
O O X X O O 12 synactic PS2 port GlidePAD

S5 S4/ Battery only

O 13 Numeric Data Process
X X X X X
14 Primary IDE interface,HDD
S5 S4/AC & Battery
don't exist X X X X X X
15 Secondary IDE innterface,CD-ROM

16 Mobile Intel Crestline Express Chipset Family

Microsoft UAA Bus Driver for High Definition Audio
Intel 82801H (ICH8 Family) PCI Express Root Port -27D0
PCI Devices
1
Broadcom NetXtreme Gigabit Ethernet 1

EXTERNAL IDSEL# REQ/GNT# PIRQ

17 Intel 82801H (ICH8 Family)PCI Express Root Port - 27D2
CARD BUS & 1394 AD22 2 C,D,E,G Broadcom 802.11b/g WLAN
Intel 82801H (ICH8 Family)USB Universal Host Controll
Intel 82801H (ICH8 Family)USB Universal Host Controll
DMA Channel Device 18
Ricoh R5C853 Cardbus Control
DMA0 MODEM / LAN Ricoh R5C853 Integrates FlashMedia Control
DMA1 ECP Ricoh R5C853 Gemcore based SmartCard Control
DMA2 FLOPPY DISK 19 Intel 82801H (ICH8 Family)PCI Express Root Port - 27D6
DMA3 AUDIO Intel 82801H (ICH8 Family)USB Universal Host Controll
DMA4 (Cascade)
DMA5 Unused 20 Intel 82801H (ICH8 Family)USB Universal Host Controll

DMA6 Unused Intel 82801H (ICH8 Family)USB2 Enhanced Host Controll

DMA7 Unused 21 Intel 82801H (ICH8 Family)USB Universal Host Controll

22
SDA Standard Compliant SD Host Controller
USB PORT# Destination
23 HP Mobile Data Protection Sensor
0 Walk-up0 (Right side)

1 Fingerprint

2 Reserve

3 WWAN

4 Walk-up1 (Left Side)

5 Walk-up2 (Left Side)

6 Bluetooth

7 Reserve Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

8 Docking THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64 1A
9 Docking MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 3 of 57
A
 5 4 3 2 1

layout note: Change R237 to 649 ohm if using XTP to ITP adapter
XDP Connector +3VS

R243
XDP_DBRESET#_R 1 2 @ 1K_0402_5%
+VCCP

JP51 XDP_TDI R143 1 2 54.9_0402_1%

1 GND0 GND1 2
XDP_BPM#5 3 4 XDP_TMS R236 1 2 54.9_0402_1%
XDP_BPM#4 OBSFN_A0 OBSFN_C0
5 OBSFN_A1 OBSFN_C1 6
7 8 XDP_TDO R1670 1 2 54.9_0402_1%
D XDP_BPM#3 GND2 GND3 D
9 OBSDATA_A0 OBSDATA_C0 10
XDP_BPM#2 11 12 XDP_BPM#5 R241 1 2 54.9_0402_1%
OBSDATA_A1 OBSDATA_C1
13 GND4 GND5 14
XDP_BPM#1 15 16 XDP_HOOK1 R1430 1 2 @ 54.9_0402_1%
XDP_BPM#0 OBSDATA_A2 OBSDATA_C2
17 OBSDATA_A3 OBSDATA_C3 18
19 GND6 GND7 20
21 22 XDP_TRST# R237 1 2 51_0402_1%
OBSFN_B0 OBSFN_D0
<7> H_A#[3..16] 23 OBSFN_B1 OBSFN_D1 24
JP12A 25 26 XDP_TCK R239 1 2 54.9_0402_1%
H_A#3 H_ADS# GND8 GND9
J4 A[3]# ADS# H1 H_ADS# <7> 27 OBSDATA_B0 OBSDATA_D0 28

ADDR GROUP 0
H_A#4 L5 E2 H_BNR# 29 30
A[4]# BNR# H_BNR# <7> OBSDATA_B1 OBSDATA_D1
H_A#5 L4 G5 H_BPRI# 31 32
A[5]# BPRI# H_BPRI# <7> GND10 GND11
H_A#6 K5 33 34
H_A#7 A[6]# H_DEFER# OBSDATA_B2 OBSDATA_D2
M3 A[7]# DEFER# H5 H_DEFER# <7> 35 OBSDATA_B3 OBSDATA_D3 36
H_A#8 N2 F21 H_DRDY# 37 38
A[8]# DRDY# H_DRDY# <7> GND12 GND13
H_A#9 J1 E1 H_DBSY# <5> H_PWRGOOD_R H_PWRGOOD_R 39 40 CLK_CPU_XDP CLK_CPU_XDP <15>
A[9]# DBSY# H_DBSY# <7> PWRGOOD/HOOK0 ITPCLK/HOOK4
H_A#10 N3 XDP_HOOK1 41 42 CLK_CPU_XDP# CLK_CPU_XDP# <15>
H_A#11 A[10]# H_BR0# R172 HOOK1 ITPCLK#/HOOK5 1K_0402_1%
P5 A[11]# BR0# F1 H_BR0# <7> +VCCP 43 VCC_OBS_AB VCC_OBS_CD 44 +VCCP
H_A#12 P2 56_0402_5% 45 46 H_RESET#_R 1 R1431 2 H_RESET#
A[12]# HOOK2 RESET#/HOOK6

CONTROL
H_A#13 L2 D20 H_IERR# 2 1 1 47 48 XDP_DBRESET#_R 2 1 XDP_DBRESET#
H_A#14 A[13]# IERR# H_INIT# +VCCP HOOK3 DBR#/HOOK7 200_0402_1%
P4 A[14]# INIT# B3 H_INIT# <25> 49 GND14 GND15 50
H_A#15 P1 C1099 51 52 XDP_TDO R1432
H_A#16 A[15]# H_LOCK# SDA TD0 XDP_TRST#
R1 A[16]# LOCK# H4 H_LOCK# <7> 53 SCL TRST# 54
H_ADSTB#0 2 XDP_TDI
<7> H_ADSTB#0 M1 ADSTB[0]# 55 TCK1 TDI 56
C1 H_RESET# XDP_TCK 57 58 XDP_TMS
RESET# H_RESET# <7> TCK0 TMS
H_REQ#0 K3 F3 H_RS#0 59 60 XDP_PRE 1 R1433 2 0_0402_5%
<7> H_REQ#0 REQ[0]# RS[0]# H_RS#0 <7> GND16 GND17
H_REQ#1 H2 F4 H_RS#1 0.1U_0402_16V4Z
<7> H_REQ#1 REQ[1]# RS[1]# H_RS#1 <7>
H_REQ#2 K2 G3 H_RS#2 conn@ SAMTE_BSH-030-01-L-D-A
<7> H_REQ#2 REQ[2]# RS[2]# H_RS#2 <7>
H_REQ#3 J3 G2 H_TRDY# Place R1431 within 200ps (~1") to CPU
<7> H_REQ#3 REQ[3]# TRDY# H_TRDY# <7>
H_REQ#4 L1
<7> H_REQ#4 REQ[4]#
G6 H_HIT#
<7> H_A#[17..35] HIT# H_HIT# <7>
H_A#17 Y2 E4 H_HITM#
C A[17]# HITM# H_HITM# <7> C
H_A#18 U5
H_A#19 A[18]# XDP_BPM#0
R3 A[19]# BPM[0]# AD4
ADDR GROUP 1

H_A#20 W6 AD3 XDP_BPM#1

H_A#21 A[20]# BPM[1]# XDP_BPM#2
U4 AD1
XDP/ITP SIGNALS

H_A#22 A[21]# BPM[2]# XDP_BPM#3

Y5 A[22]# BPM[3]# AC4
H_A#23 U1 AC2 XDP_BPM#4
H_A#24 A[23]# PRDY# XDP_BPM#5
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK For Merom, R23 and R34 are 0ohm
H_A#26 A[25]# TCK XDP_TDI
T3 AA6
H_A#27
H_A#28
W2
W5
A[26]#
A[27]#
TDI
TDO AB3
AB5
XDP_TDO
XDP_TMS
For Penryn, R23 and R34 are 100ohm. Thermal Sensor ADM1032ARMZ
H_A#29 A[28]# TMS XDP_TRST# +3VS
Y4 A[29]# TRST# AB6
H_A#30 U2 C20 XDP_DBRESET#
A[30]# DBR# XDP_DBRESET# <26>
H_A#31 V4 A[31]# H_PROCHOT# <49>
H_A#32 W3 R410 2
H_A#33 A[32]# H_PROCHOT# C273
AA4 A[33]# THERMAL 2 1 +VCCP

2
H_A#34 AB2 68_0402_5%
H_A#35 A[34]# 0.1U_0402_16V4Z R227
AA3 A[35]# PROCHOT# D21
H_ADSTB#1 1
<7> H_ADSTB#1 V1 ADSTB[1]# THERMDA A24 H_THERMDA_R R23 1 2 0_0402_5% H_THERMDA 10K_0402_5%
THERMDC B25 H_THERMDC_R R34 1 2 0_0402_5% H_THERMDC U16
H_A20M# A6 1 8 ICH_SM_CLK
<25> H_A20M#

1
A20M# VDD SCLK
ICH

H_FERR# A5 C7 H_THERMTRIP#
<25> H_FERR# FERR# THERMTRIP# H_THERMTRIP# <7,23,25>
H_IGNNE# C4 H_THERMDA 2 7 ICH_SM_DA
<25> H_IGNNE# IGNNE# D+ SDATA
11/20 Penryn support to add R23,R34 C264
H_STPCLK# D5 1 2 H_THERMDC 3 6 THERM_SCI#
<25> H_STPCLK# STPCLK# D- ALERT# THERM_SCI# <23,26>
H_INTR C6 H CLK
<25> H_INTR LINT0
H_NMI B4 A22 CLK_CPU_BCLK 2200P_0402_50V7K THERM# 4 5
<25> H_NMI LINT1 BCLK[0] CLK_CPU_BCLK <15> THERM# GND
H_SMI# A3 A21 CLK_CPU_BCLK#
<25> H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# <15>
R228
M4 +3VS 1 2 ADM1032ARMZ-2REEL_MSOP8
RSVD[01]
N5 RSVD[02] H_THERMDA, H_THERMDC routing together, 10K_0402_5%
T2 RSVD[03]
Address:100_1100
B
V3 Trace width / Spacing = 10 / 10 mil B
RSVD[04] R229
B2
RESERVED

RSVD[05]
C3 RSVD[06] <23> THERM#_VGA 1 2
D2 <19,23,26,31> ICH_SM_CLK ICH_SM_CLK
RSVD[07] 0_0402_5% ICH_SM_DA
D22 RSVD[08] <19,23,26,31> ICH_SM_DA
D3 RSVD[09] @
F6 RSVD[10]
0802 (R1A) add for VGA thermal function

Merom Ball-out Rev 1a

conn@
PWM Fan Control circuit
+VCCP
1

0308 change design

R1255 +3VS

@ 56_0402_5%
conn@
2 2

5
U24 JP8
B

1 1

P
<37> FAN_PWM INB +5VS 1
O 4 2 2 G1 4
E

H_PROCHOT# 3 1 OCP# THERM# 1 2 2 3 5

OCP# <26,50> INA 3 G2

G
C

@ Q85
MMBT3904_SOT23 0_0402_5% TC7SH00FU_SSOP5 ACES_85204-03001

3
R230
+3VS 1 2
A R232 A
@ 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(1/3)-AGTL+/XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 4 of 57
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE +VCC_CORE
<7> H_D#[0..15] H_D#[32..47] <7>
JP12B JP12C
H_D#0 E22 Y22 H_D#32 A7 AB20
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
F24 D[1]# D[33]# AB24 A9 VCC[002] VCC[069] AB7
H_D#2 E26 V24 H_D#34 A10 AC7
H_D#3 D[2]# D[34]# H_D#35 VCC[003] VCC[070]
G22 D[3]# D[35]# V26 A12 VCC[004] VCC[071] AC9

DATA GRP 0
D H_D#4 H_D#36 D
F23 D[4]# D[36]# V23 A13 VCC[005] VCC[072] AC12
H_D#5 G25 T22 H_D#37 A15 AC13
H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
E25 D[6]# D[38]# U25 A17 VCC[007] VCC[074] AC15
H_D#7 E23 U23 H_D#39 A18 AC17
H_D#8 D[7]# D[39]# H_D#40 VCC[008] VCC[075]
K24 Y25 A20 AC18

DATA GRP 2
H_D#9 D[8]# D[40]# H_D#41 VCC[009] VCC[076]
G24 D[9]# D[41]# W22 B7 VCC[010] VCC[077] AD7
H_D#10 J24 Y23 H_D#42 B9 AD9
H_D#11 D[10]# D[42]# H_D#43 VCC[011] VCC[078]
J23 D[11]# D[43]# W24 B10 VCC[012] VCC[079] AD10
H_D#12 H22 W25 H_D#44 B12 AD12
H_D#13 D[12]# D[44]# H_D#45 VCC[013] VCC[080]
F26 D[13]# D[45]# AA23 B14 VCC[014] VCC[081] AD14
H_D#14 K22 AA24 H_D#46 B15 AD15
H_D#15 D[14]# D[46]# H_D#47 VCC[015] VCC[082]
H23 D[15]# D[47]# AB25 B17 VCC[016] VCC[083] AD17
H_DSTBN#0 J26 Y26 H_DSTBN#2 B18 AD18
<7> H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 <7> VCC[017] VCC[084]
H_DSTBP#0 H26 AA26 H_DSTBP#2 B20 AE9
<7> H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 <7> VCC[018] VCC[085]
H_DINV#0 H25 U22 H_DINV#2 C9 AE10
<7> H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 <7> VCC[019] VCC[086]
<7> H_D#[16..31] H_D#[48..63] <7> C10 VCC[020] VCC[087] AE12
C12 VCC[021] VCC[088] AE13
H_D#16 N22 AE24 H_D#48 C13 AE15
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
K25 D[17]# D[49]# AD24 C15 VCC[023] VCC[090] AE17
H_D#18 P26 AA21 H_D#50 C17 AE18
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
R23 D[19]# D[51]# AB22 C18 VCC[025] VCC[092] AE20
H_D#20 L23 AB21 H_D#52 D9 AF9
D[20]# D[52]# VCC[026] VCC[093]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D10 AF10
H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
L22 D[22]# D[54]# AD20 D12 VCC[028] VCC[095] AF12
H_D#23 M23 AE22 H_D#55 D14 AF14
H_D#24 D[23]# D[55]# H_D#56 VCC[029] VCC[096]
P25 D[24]# D[56]# AF23 D15 VCC[030] VCC[097] AF15
H_D#25 P23 AC25 H_D#57 D17 AF17
H_D#26 D[25]# D[57]# H_D#58 VCC[031] VCC[098]
P22 AE21 D18 AF18

DATA GRP 3
H_D#27 D[26]# D[58]# H_D#59 VCC[032] VCC[099] +VCCP
T24 D[27]# D[59]# AD21 E7 VCC[033] VCC[100] AF20
H_D#28 R24 AC22 H_D#60 E9 R1434 0_0402_5%
H_D#29 D[28]# D[60]# H_D#61 VCC[034] 0228 change value
L25 D[29]# D[61]# AD23 E10 VCC[035] VCCP[01] G21 2 1
H_D#30 T25 AF22 H_D#62 E12 V6 2 1
C H_D#31 D[30]# D[62]# H_D#63 VCC[036] VCCP[02] R1435 0_0402_5% C
N25 D[31]# D[63]# AC23 E13 VCC[037] VCCP[03] J6
H_DSTBN#1 L26 AE25 H_DSTBN#3 E15 K6 1
<7> H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 <7> VCC[038] VCCP[04]
H_DSTBP#1 M26 AF24 H_DSTBP#3 E17 M6
<7> H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 <7> VCC[039] VCCP[05]
H_DINV#1 N24 AC20 H_DINV#3 E18 J21 C1100 +
<7> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <7> VCC[040] VCCP[06]
E20 VCC[041] VCCP[07] K21
V_CPU_GTLREF AD26 R26 COMP0 F7 M21 330U_D2E_2.5VM_R15
R1264 1 GTLREF COMP[0] VCC[042] VCCP[08] 2
2 @ 1K_0402_5% TEST1 C23 TEST1 MISC COMP[1] U26 COMP1 F9 VCC[043] VCCP[09] N21
R1265 1 2 @ 1K_0402_5% TEST2 D25 AA1 COMP2 F10 N6
TEST3 TEST2 COMP[2] COMP3 VCC[044] VCCP[10]
T1 C24 TEST3 COMP[3] Y1 F12 VCC[045] VCCP[11] R21
C1101 1 2 @ 0.1U_0402_16V4Z TEST4 AF26 F14 R6
TEST5 TEST4 H_DPRSTP# VCC[046] VCCP[12]
T2 AF1 TEST5 DPRSTP# E5 H_DPRSTP# <7,25,49> F15 VCC[047] VCCP[13] T21

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%
TEST6 A26 B5 H_DPSLP# F17 T6
T3 TEST6 DPSLP# H_DPSLP# <25> VCC[048] VCCP[14]

1
D24 H_DPWR# F18 V21
DPWR# H_DPWR# <7> VCC[049] VCCP[15]
CPU_BSEL0 B22 D6 H_PWRGOOD F20 W21
<15> CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD <25> VCC[050] VCCP[16]

R1220

R355

R245

R244
CPU_BSEL1 B23 D7 H_CPUSLP# AA7
<15> CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# <7> VCC[051]
CPU_BSEL2 C21 AE6 H_PSI# AA9 B26
<15> CPU_BSEL2 BSEL[2] PSI# H_PSI# <49> VCC[052] VCCA[01] +1.5VS

0.01U_0402_16V7K
AA10 C26

2
VCC[053] VCCA[02]

10U_0805_10V4Z
Merom Ball-out Rev 1a R1436 AA12 VCC[054]
conn@ 2 1H_PWRGOOD_R H_PWRGOOD_R <4> AA13 VCC[055] VID[0] AD6 CPU_VID0 <49>
1K_0402_5% AA15 AF5 1 1
VCC[056] VID[1] CPU_VID1 <49>
AA17 VCC[057] VID[2] AE5 CPU_VID2 <49>

C520

C531
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs Resistor placed within AA18 VCC[058] VID[3] AF4 CPU_VID3 <49>
AA20 AE3 CPU_VID4 <49>
0.5" of CPU pin.Trace AB9
VCC[059] VID[4]
AF3
2 2
VCC[060] VID[5] CPU_VID5 <49>
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 should be at least 25 AC10 VCC[061] VID[6] AE2 CPU_VID6 <49>
AB10
mils away from any other AB12
VCC[062]
VCC[063]
toggling signal. AB14 VCC[064] VCCSENSE AF7 VCCSENSE VCCSENSE <49>
166 0 1 1 COMP[0,2] trace width is AB15 VCC[065] Near pin B26
AB17 VCC[066]
18 mils. COMP[1,3] trace AB18 VCC[067] VSSSENSE AE7 VSSSENSE VSSSENSE <49>
B width is 4 mils. Merom Ball-out Rev 1a B
200 0 1 0
conn@ .
Length match within 25 mils.
The trace width/space/other is
20/7/25.
+VCCP
1

R1268
1K_0402_1%
+VCC_CORE
2

V_CPU_GTLREF R1269
100_0402_1%
1 2 VCCSENSE
1

R1270
R1271 100_0402_1%
2K_0402_1% 1 2 VSSSENSE
2

Close to CPU pin AD26

within 500mils. Close to CPU pin
within 500mils.
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(2/3)-AGTL+/PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 5 of 57
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE

1 1 1 1 1 1 1 1
C899 C900 C901 C902 C903 C904 C905 C906
Place these capacitors on L8
(North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
D 2 2 2 2 2 2 2 2 D

JP12D
A4 VSS[001] VSS[082] P6
+VCC_CORE
A8 VSS[002] VSS[083] P21
A11 VSS[003] VSS[084] P24
A14 VSS[004] VSS[085] R2
A16 VSS[005] VSS[086] R5 1 1 1 1 1 1 1 1
A19 R22 C907 C908 C909 C910 C911 C912 C913 C914
VSS[006] VSS[087] Place these capacitors on L8
A23 VSS[007] VSS[088] R25
AF2 T1 (North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[008] VSS[089] 2 2 2 2 2 2 2 2
B6 VSS[009] VSS[090] T4
B8 VSS[010] VSS[091] T23
B11 VSS[011] VSS[092] T26
B13 VSS[012] VSS[093] U3
+VCC_CORE
B16 VSS[013] VSS[094] U6
B19 VSS[014] VSS[095] U21
B21 VSS[015] VSS[096] U24
B24 VSS[016] VSS[097] V2 1 1 1 1 1 1 1 1
C5 V5 C915 C916 C917 C918 C919 C920 C921 C922
VSS[017] VSS[098] Place these capacitors on L8
C8 VSS[018] VSS[099] V22
C11 V25 (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[019] VSS[100] 2 2 2 2 2 2 2 2
C14 VSS[020] VSS[101] W1
C16 VSS[021] VSS[102] W4
C19 VSS[022] VSS[103] W23
C2 VSS[023] VSS[104] W26
+VCC_CORE
C22 VSS[024] VSS[105] Y3
C25 VSS[025] VSS[106] Y6
D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24 1 1 1 1 1 1 1 1
D8 AA2 C923 C924 C925 C926 C927 C928 C929 C930
VSS[028] VSS[109] Place these capacitors on L8
D11 VSS[029] VSS[110] AA5
C (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M C
D13 VSS[030] VSS[111] AA8
2 2 2 2 2 2 2 2
D16 VSS[031] VSS[112] AA11
D19 VSS[032] VSS[113] AA14 Mid Frequence Decoupling
D23 VSS[033] VSS[114] AA16
D26 VSS[034] VSS[115] AA19
E3 VSS[035] VSS[116] AA22
E6 VSS[036] VSS[117] AA25
E8 VSS[037] VSS[118] AB1
E11 VSS[038] VSS[119] AB4
E14 VSS[039] VSS[120] AB8
E16 VSS[040] VSS[121] AB11
E19 VSS[041] VSS[122] AB13
E21 VSS[042] VSS[123] AB16
E24 VSS[043] VSS[124] AB19
F5 VSS[044] VSS[125] AB23
F8 VSS[045] VSS[126] AB26
F11 VSS[046] VSS[127] AC3
F13 VSS[047] VSS[128] AC6
F16 AC8
F19
F2
VSS[048]
VSS[049]
VSS[129]
VSS[130] AC11
AC14
ESR <= 1.5m ohm
F22
VSS[050]
VSS[051]
VSS[131]
VSS[132] AC16 Near CPU CORE regulator Capacitor > 1980uF
F25 VSS[052] VSS[133] AC19
G4 VSS[053] VSS[134] AC21
G1 VSS[054] VSS[135] AC24
G23 VSS[055] VSS[136] AD2
G26 VSS[056] VSS[137] AD5
+VCC_CORE
H3 VSS[057] VSS[138] AD8
H6 VSS[058] VSS[139] AD11
H21 AD13 330U_D2E_2.5VM_R7 330U_D2E_2.5VM_R7
VSS[059] VSS[140]
H24 VSS[060] VSS[141] AD16
J2 VSS[061] VSS[142] AD19
B B
J5 VSS[062] VSS[143] AD22
J22 VSS[063] VSS[144] AD25 1 1 1 1 1 1
J25 AE1 @ @
VSS[064] VSS[145] C931 + C932 + C933 + C935 + C936 + C937 +
K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8
K23 AE11 330U_D2E_2.5VM_R7
VSS[067] VSS[148] 2 2 2 2 2 2
K26 VSS[068] VSS[149] AE14
L3 VSS[069] VSS[150] AE16
L6 VSS[070] VSS[151] AE19
L21 AE23 330U_D2E_2.5VM_R7 330U_D2E_2.5VM_R7 330U_D2E_2.5VM_R7
VSS[071] VSS[152]
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2
M5 VSS[074] VSS[155] AF6
M22 VSS[075] VSS[156] AF8
M25 VSS[076] VSS[157] AF11 Place these inside
N1 VSS[077] VSS[158] AF13 socket cavity on L8
N4 VSS[078] VSS[159] AF16 (North side
N23 VSS[079] VSS[160] AF19
N26 AF21
Secondary)
VSS[080] VSS[161]
P3 VSS[081] VSS[162] A25
AF25 +VCCP
VSS[163]
Merom Ball-out Rev 1a
conn@ . 1 1 1 1 1 1
C940 C941 C942 C943 C944 C945

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(3/3)-GND&Bypass
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 6 of 57
5 4 3 2 1
 5 4 3 2 1

H_A#[3..35] <4> U15B For Crestline: 20ohm

<5> H_D#[0..63] U15A For Calero: 80.6ohm
J13 H_A#3 P36
H_D#0 H_A#_3 H_A#4 RSVD1 M_CLK_DDR0
E2 H_D#_0 H_A#_4 B11 P37 RSVD2 SM_CK_0 AV29 M_CLK_DDR0 <13>
H_D#1 G2 C11 H_A#5 R35 BB23 M_CLK_DDR1 M_CLK_DDR1 <13>
H_D#2 H_D#_1 H_A#_5 H_A#6 RSVD3 SM_CK_1 M_CLK_DDR2
G7 H_D#_2 H_A#_6 M11 N35 RSVD4 SM_CK_3 BA25 M_CLK_DDR2 <14>
H_D#3 M6 C15 H_A#7 AR12 AV23 M_CLK_DDR3 M_CLK_DDR3 <14>

2.2U_0603_6.3V4Z
H_D#_3 H_A#_7 +1.8V RSVD5 SM_CK_4

0.01U_0402_25V7K
H_D#4 H7 F16 H_A#8 AR13
H_D#5 H_D#_4 H_A#_8 H_A#9 RSVD6 M_CLK_DDR#0
H3 H_D#_5 H_A#_9 L13 AM12 RSVD7 SM_CK#_0 AW30 M_CLK_DDR#0 <13>
H_D#6 G4 G17 H_A#10 2 2 AN13 BA23 M_CLK_DDR#1
H_D#_6 H_A#_10 RSVD8 SM_CK#_1 M_CLK_DDR#1 <13>

1
H_D#7 F3 C14 H_A#11 J12 AW25 M_CLK_DDR#2
H_D#_7 H_A#_11 RSVD9 SM_CK#_3 M_CLK_DDR#2 <14>

RSVD
H_D#8 N8 K16 H_A#12 R1437 AR37 AW23 M_CLK_DDR#3
H_D#_8 H_A#_12 RSVD10 SM_CK#_4 M_CLK_DDR#3 <14>

C1102

C1103
H_D#9 H2 B13 H_A#13 AM36
H_D#10 H_D#_9 H_A#_13 H_A#14 1 1 1K_0402_1% RSVD11 DDR_CKE0_DIMMA
M10 H_D#_10 H_A#_14 L16 AL36 RSVD12 SM_CKE_0 BE29 DDR_CKE0_DIMMA <13>
H_D#11 N12 J17 H_A#15 AM37 AY32 DDR_CKE1_DIMMA
DDR_CKE1_DIMMA <13>

2
D H_D#12 H_D#_11 H_A#_15 H_A#16 SMRCOMP_VOH RSVD13 SM_CKE_1 DDR_CKE2_DIMMB D
N9 H_D#_12 H_A#_16 B14 D20 RSVD14 SM_CKE_3 BD39 DDR_CKE2_DIMMB <14>
H_D#13 H5 K19 H_A#17 BG37 DDR_CKE3_DIMMB
H_D#_13 H_A#_17 SM_CKE_4 DDR_CKE3_DIMMB <14>

1
H_D#14 P13 P15 H_A#18
H_D#15 H_D#_14 H_A#_18 H_A#19 R31 DDR_CS0_DIMMA#
K9 H_D#_15 H_A#_19 R17 SM_CS#_0 BG20 DDR_CS0_DIMMA# <13>
H_D#16 M2 B16 H_A#20 3.01K_0402_1% BK16 DDR_CS1_DIMMA#
H_D#_16 H_A#_20 SM_CS#_1 DDR_CS1_DIMMA# <13>
H_D#17 W10 H20 H_A#21 BG16 DDR_CS2_DIMMB#
H_D#_17 H_A#_21 SM_CS#_2 DDR_CS2_DIMMB# <14>
H_D#18 Y8 L19 H_A#22 H10 BE13 DDR_CS3_DIMMB#
DDR_CS3_DIMMB# <14>

2
H_D#19 H_D#_18 H_A#_22 H_A#23 SMRCOMP_VOL RSVD20 SM_CS#_3
V4 D17 B51

MUXING
H_D#20 H_D#_19 H_A#_23 H_A#24 RSVD21 M_ODT0
M3 H_D#_20 H_A#_24 M17 BJ20 RSVD22 SM_ODT_0 BH18 M_ODT0 <13>

1
0.01U_0402_25V7K
H_D#21 H_A#25 M_ODT1

2.2U_0603_6.3V4Z
J1 H_D#_21 H_A#_25 N16 BK22 RSVD23 SM_ODT_1 BJ15 M_ODT1 <13>
H_D#22 H_A#26 R1438 M_ODT2 +1.8V
N5 H_D#_22 H_A#_26 J19 1 1 BF19 RSVD24 SM_ODT_2 BJ14 M_ODT2 <14>
H_D#23 N3 B18 H_A#27 BH20 BE16 M_ODT3 M_ODT3 <14>
H_D#24 H_D#_23 H_A#_27 H_A#28 1K_0402_1% RSVD25 SM_ODT_3 20_0402_1%
W6 H_D#_24 H_A#_28 E19 BK18 RSVD26

C1104

C1105
H_D#25 W9 B17 H_A#29 BJ18 BL15 SMRCOMP R1194 2 1

2
H_D#26 H_D#_25 H_A#_29 H_A#30 2 2 RSVD27 SM_RCOMP SMRCOMP#
N2 H_D#_26 H_A#_30 B15 BF23 RSVD28 SM_RCOMP# BK14 2 1
H_D#27 Y7 E17 H_A#31 BG23 R1195 20_0402_1%
H_D#28 H_D#_27 H_A#_31 H_A#32 RSVD29 SMRCOMP_VOH
Y9 H_D#_28 H_A#_32 C18 BC23 RSVD30 SM_RCOMP_VOH BK31
H_D#29 P4 A19 H_A#33 BD24 BL31 SMRCOMP_VOL

DDR
H_D#30 H_D#_29 H_A#_33 H_A#34 RSVD31 SM_RCOMP_VOL
W3 H_D#_30 H_A#_34 B19 <13> DDR_A_MA14 BJ29 RSVD32
H_D#31 N1 N19 H_A#35 BE24 AR49
H_D#_31 H_A#_35 <14> DDR_B_MA14 RSVD33 SM_VREF_0
H_D#32 AD12 BH39 AW4 V_DDR_MCH_REF
H_D#33 H_D#_32 H_ADS# RSVD34 SM_VREF_1
AE3 H_D#_33 H_ADS# G12 H_ADS# <4> AW20 RSVD35
H_D#34 AD9
HOST H17 H_ADSTB#0 +3VS BK20
H_D#_34 H_ADSTB#_0 H_ADSTB#0 <4> RSVD36
H_D#35 AC9 G20 H_ADSTB#1 R1439 C48
H_D#_35 H_ADSTB#_1 H_ADSTB#1 <4> RSVD37
H_D#36 AC7 C8 H_BNR# PM_EXTTS#0 2 1 D47 B42
H_D#_36 H_BNR# H_BNR# <4> RSVD38 DPLL_REF_CLK
H_D#37 AC14 E8 H_BPRI# B44 C42
H_D#_37 H_BPRI# H_BPRI# <4> RSVD39 DPLL_REF_CLK#
H_D#38 AD11 F12 H_BR0# 10K_0402_5% C44 H48
H_D#_38 H_BREQ# H_BR0# <4> RSVD40 DPLL_REF_SSCLK
H_D#39 AC11 D6 H_DEFER# A35 H47
H_D#_39 H_DEFER# H_DEFER# <4> RSVD41 DPLL_REF_SSCLK#
H_D#40 AB2 C10 H_DBSY# R1440 B37
H_D#_40 H_DBSY# H_DBSY# <4> RSVD42
H_D#41 AD7 AM5 CLK_MCH_BCLK PM_EXTTS#1 2 1 B36 K44 CLK_MCH_3GPLL
H_D#_41 HPLL_CLK CLK_MCH_BCLK <15> RSVD43 PEG_CLK CLK_MCH_3GPLL <15>

CLK
H_D#42 AB1 AM7 CLK_MCH_BCLK# B34 K45 CLK_MCH_3GPLL#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# <15> RSVD44 PEG_CLK# CLK_MCH_3GPLL# <15>
H_D#43 Y3 H8 H_DPWR# 10K_0402_5% C34
C H_D#_43 H_DPWR# H_DPWR# <5> RSVD45 C
H_D#44 AC6 K7 H_DRDY#
H_D#_44 H_DRDY# H_DRDY# <4>
H_D#45 AE2 E4 H_HIT# R1441
H_D#_45 H_HIT# H_HIT# <4>
H_D#46 AC5 C6 H_HITM# CLKREQ#_B 2 <> 1 AN47 DMI_TXN0
H_D#_46 H_HITM# H_HITM# <4> DMI_RXN_0 DMI_TXN0 <26>
H_D#47 AG3 G10 H_LOCK# AJ38 DMI_TXN1
H_D#_47 H_LOCK# H_LOCK# <4> DMI_RXN_1 DMI_TXN1 <26>
H_D#48 AJ9 B7 H_TRDY# 10K_0402_5% AN42 DMI_TXN2
H_D#_48 H_TRDY# H_TRDY# <4> DMI_RXN_2 DMI_TXN2 <26>
H_D#49 AH8 AN46 DMI_TXN3
H_D#_49 DMI_RXN_3 DMI_TXN3 <26>
H_D#50 AJ14
H_D#51 H_D#_50 DMI_TXP0
AE9 H_D#_51 DMI_RXP_0 AM47 DMI_TXP0 <26>
H_D#52 AE11 MCH_CLKSEL0 P27 AJ39 DMI_TXP1
+VCCP H_D#_52 <15> MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_TXP1 <26>
H_D#53 AH12 K5 H_DINV#0 MCH_CLKSEL1 N27 AN41 DMI_TXP2
H_D#_53 H_DINV#_0 H_DINV#0 <5> <15> MCH_CLKSEL1 CFG_1 DMI_RXP_2 DMI_TXP2 <26>
H_D#54 AJ5 L2 H_DINV#1 MCH_CLKSEL2 N24 AN45 DMI_TXP3
H_D#_54 H_DINV#_1 H_DINV#1 <5> <15> MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_TXP3 <26>
H_D#55 AH5 AD13 H_DINV#2 CFG3 C21
H_D#_55 H_DINV#_2 H_DINV#2 <5> T104 CFG_3
H_D#56 AJ6 AE13 H_DINV#3 CFG4 C23 AJ46 DMI_RXN0
H_D#_56 H_DINV#_3 H_DINV#3 <5> T105 CFG_4 DMI_TXN_0 DMI_RXN0 <26>
54.9_0402_1%

54.9_0402_1%

H_D#57 AE7 CFG5 F23 AJ41 DMI_RXN1

H_D#_57 <9> CFG5 CFG_5 DMI_TXN_1 DMI_RXN1 <26>
1

H_D#58 AJ7 M7 H_DSTBN#0 CFG6 N23 AM40 DMI_RXN2

H_D#_58 H_DSTBN#_0 H_DSTBN#0 <5> T106 CFG_6 DMI_TXN_2 DMI_RXN2 <26>
H_D#59 AJ2 K3 H_DSTBN#1 CFG7 G23 AM44 DMI_RXN3
H_D#_59 H_DSTBN#_1 H_DSTBN#1 <5> <9> CFG7 CFG_7 DMI_TXN_3 DMI_RXN3 <26>
R1196

R1197

H_D#60 AE5 AD2 H_DSTBN#2 CFG8 J20

DMI
H_D#_60 H_DSTBN#_2 H_DSTBN#2 <5> <9> CFG8 CFG_8

CFG
H_D#61 AJ3 AH11 H_DSTBN#3 CFG9 C20 AJ47 DMI_RXP0
H_D#_61 H_DSTBN#_3 H_DSTBN#3 <5> <9> CFG9 CFG_9 DMI_TXP_0 DMI_RXP0 <26>
H_D#62 AH2 CFG10 R24 AJ42 DMI_RXP1
T107 DMI_RXP1 <26>
2

H_D#63 H_D#_62 H_DSTBP#0 CFG11 CFG_10 DMI_TXP_1 DMI_RXP2

AH13 H_D#_63 H_DSTBP#_0 L7 H_DSTBP#0 <5> T108 L23 CFG_11 DMI_TXP_2 AM39 DMI_RXP2 <26>
K2 H_DSTBP#1 CFG12 J23 AM43 DMI_RXP3
H_DSTBP#_1 H_DSTBP#1 <5> <9> CFG12 CFG_12 DMI_TXP_3 DMI_RXP3 <26>
AC2 H_DSTBP#2 CFG13 E23
H_DSTBP#_2 H_DSTBP#2 <5> <9> CFG13 CFG_13
H_SWNG B3 AJ10 H_DSTBP#3 CFG14 E20
H_SWING H_DSTBP#_3 H_DSTBP#3 <5> T109 CFG_14
H_RCOMP C2 CFG15 K23
H_RCOMP T110 CFG_15
M14 H_REQ#0 CFG16 M20
H_REQ#_0 H_REQ#0 <4> <9> CFG16 CFG_16
H_SCOMP W1 E13 H_REQ#1 CFG17 M24
H_REQ#1 <4> T111

GRAPHICS VID
H_SCOMP# H_SCOMP H_REQ#_1 H_REQ#2 CFG18 CFG_17
W2 H_SCOMP# H_REQ#_2 A11 H_REQ#2 <4> T112 L32 CFG_18
H13 H_REQ#3 CFG19 N33
H_REQ#_3 H_REQ#3 <4> <9> CFG19 CFG_19
<4> H_RESET# H_RESET# B6 B12 H_REQ#4 CFG20 L35
H_CPURST# H_REQ#_4 H_REQ#4 <4> <9> CFG20 CFG_20
<5> H_CPUSLP# H_CPUSLP# E5 H_CPUSLP# H_RS#0
H_RS#_0 E12 H_RS#0 <4>
D7 H_RS#1 H_RS#1 <4> E35
B H_RS#_1 H_RS#2 PM_BMBUSY# GFX_VID_0 B
H_RS#_2 D8 H_RS#2 <4> <26> PM_BMBUSY# G41 PM_BM_BUSY# GFX_VID_1 A39
B9 H_DPRSTP# L39 C38
H_AVREF <5,25,49> H_DPRSTP# PM_DPRSTP# GFX_VID_2
H_VREF A9 PM_EXTTS#0 L36 B39
H_DVREF <13> PM_EXTTS#0 PM_EXT_TS#_0 GFX_VID_3

PM
0904 add PM_EXTTS#1 J36 E36
<14> PM_EXTTS#1 PM_EXT_TS#_1 GFX_VR_EN
CRESTLINE_1p0 PM_POK_R AW49
0_0402_5% PLT_RST#_R PWROK +1.25VM_AXD
layout note: AV20 RSTIN#
<4,23,25> H_THERMTRIP# 1 2 R2 THERM_TRIP# N20 THERMTRIP#
<26,49> DPRSLPVR DPRSLPVR G36 DPRSLPVR

1
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces
AM49 CL_CLK0 R1442
CL_CLK CL_CLK0 <26>
11/20 Add R2 for Intel ES2 chipset AK50 CL_DATA0
CL_DATA CL_DATA0 <26>
2 1 PM_POK_R BJ51 AT43 M_PWROK 1K_0402_1%
<26,37> VGATE NC_1 CL_PWROK M_PWROK <26,41>
R1484 0_0402_5% CL_RST#

ME
Layout Note: BK51 AN49 CL_RST# <26>

2
NC_2 CL_RST# CL_VREF CL_VREF
BK50 AM50
H_RCOMP / H_VREF / H_SWNG BL50
NC_3 CL_VREF
NC_4

1
trace width and spacing is 10/20 2007,0125 change BL49 0.1U_0402_16V4Z 1
NC_5 R1443
Layout Note: BL3 NC_6
BL2 C1106 392_0402_1%
V_DDR_MCH_REF +1.8V NC_7

NC
BK1 NC_8
trace width and THERM_TRIP# 2
BJ1 H35

2
+VCCP NC_9 SDVO_CTRL_CLK
0.1U_0402_16V4Z

spacing is 20/20. E1 K36

MISC
NC_10 SDVO_CTRL_DATA
1

+VCCP A5 G39 CLKREQ#_B

NC_11 CLK_REQ# CLKREQ#_B <15>
R1201 1 C51 G40 MCH_ICH_SYNC#
NC_12 ICH_SYNC# MCH_ICH_SYNC# <26>
221_0603_1%
1K_0402_1%

@ 1K_0402_1% B50 NC_13

1

C1626

A50 NC_14
R1206

A49 A37
2

2 NC_15 TEST_1
R1208

V_DDR_MCH_REF BK2 R32

<13,14,48> V_DDR_MCH_REF NC_16 TEST_2
0.1U_0402_16V4Z

1
0.1U_0402_16V4Z @ CRESTLINE_1p0
2

H_VREF H_RCOMP H_SWNG 1 R1204 R1444 R1445

24.9_0402_1%

C895
0.1U_0402_16V4Z

@ 1K_0402_1% 20K_0402_5% 0_0402_5%

1

1
2K_0402_1%

100_0402_1%

A A
1 1
2

2
2 R1446
R1212

C60

R1199

R1210

C896

PLT_RST#_R 2 1 PLT_RST#
PLT_RST# <24,28,36>
2 2 100_0402_5%
2

Security Classification Compal Secret Data Compal Electronics, Inc.

within 100 mils from NB Near B3 pin Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE(1/6)-AGTL+/DMI/DDR2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 7 of 57
5 4 3 2 1
 5 4 3 2 1

D D

<13> DDR_A_D[0..63] <14> DDR_B_D[0..63]

U15D U15E
DDR_A_D0 AR43 BB19 DDR_A_BS0 DDR_B_D0 AP49 AY17 DDR_B_BS0
SA_DQ_0 SA_BS_0 DDR_A_BS0 <13> SB_DQ_0 SB_BS_0 DDR_B_BS0 <14>
DDR_A_D1 AW44 BK19 DDR_A_BS1 DDR_B_D1 AR51 BG18 DDR_B_BS1
SA_DQ_1 SA_BS_1 DDR_A_BS1 <13> SB_DQ_1 SB_BS_1 DDR_B_BS1 <14>
DDR_A_D2 BA45 BF29 DDR_A_BS2 DDR_B_D2 AW50 BG36 DDR_B_BS2
SA_DQ_2 SA_BS_2 DDR_A_BS2 <13> SB_DQ_2 SB_BS_2 DDR_B_BS2 <14>
DDR_A_D3 AY46 DDR_B_D3 AW51
DDR_A_D4 SA_DQ_3 DDR_A_CAS# DDR_B_D4 SB_DQ_3 DDR_B_CAS#
AR41 SA_DQ_4 SA_CAS# BL17 DDR_A_CAS# <13> AN51 SB_DQ_4 SB_CAS# BE17 DDR_B_CAS# <14>
DDR_A_D5 AR45 DDR_B_D5 AN50
SA_DQ_5 DDR_A_DM[0..7] <13> SB_DQ_5 DDR_B_DM[0..7] <14>
DDR_A_D6 AT42 AT45 DDR_A_DM0 DDR_B_D6 AV50 AR50 DDR_B_DM0
DDR_A_D7 SA_DQ_6 SA_DM_0 DDR_A_DM1 DDR_B_D7 SB_DQ_6 SB_DM_0 DDR_B_DM1
AW47 SA_DQ_7 SA_DM_1 BD44 AV49 SB_DQ_7 SB_DM_1 BD49
DDR_A_D8 BB45 BD42 DDR_A_DM2 DDR_B_D8 BA50 BK45 DDR_B_DM2
DDR_A_D9 SA_DQ_8 SA_DM_2 DDR_A_DM3 DDR_B_D9 SB_DQ_8 SB_DM_2 DDR_B_DM3
BF48 SA_DQ_9 SA_DM_3 AW38 BB50 SB_DQ_9 SB_DM_3 BL39
DDR_A_D10 BG47 AW13 DDR_A_DM4 DDR_B_D10 BA49 BH12 DDR_B_DM4
DDR_A_D11 SA_DQ_10 SA_DM_4 DDR_A_DM5 DDR_B_D11 SB_DQ_10 SB_DM_4 DDR_B_DM5
BJ45 SA_DQ_11 SA_DM_5 BG8 BE50 SB_DQ_11 SB_DM_5 BJ7
DDR_A_D12 BB47 AY5 DDR_A_DM6 DDR_B_D12 BA51 BF3 DDR_B_DM6
DDR_A_D13 SA_DQ_12 SA_DM_6 DDR_A_DM7 DDR_B_D13 SB_DQ_12 SB_DM_6 DDR_B_DM7
BG50 SA_DQ_13 SA_DM_7 AN6 AY49 SB_DQ_13 SB_DM_7 AW2
DDR_A_D14 BH49 DDR_A_DQS[0..7] <13> DDR_B_D14 BF50
SA_DQ_14 SB_DQ_14 DDR_B_DQS[0..7] <14>
DDR_A_D15 BE45 AT46 DDR_A_DQS0 DDR_B_D15 BF49 AT50 DDR_B_DQS0

A
SA_DQ_15 SA_DQS_0 SB_DQ_15 SB_DQS_0

B
DDR_A_D16 AW43 BE48 DDR_A_DQS1 DDR_B_D16 BJ50 BD50 DDR_B_DQS1
DDR_A_D17 SA_DQ_16 SA_DQS_1 DDR_A_DQS2 DDR_B_D17 SB_DQ_16 SB_DQS_1 DDR_B_DQS2
BE44 SA_DQ_17 SA_DQS_2 BB43 BJ44 SB_DQ_17 SB_DQS_2 BK46
DDR_A_D18 BG42 BC37 DDR_A_DQS3 DDR_B_D18 BJ43 BK39 DDR_B_DQS3
DDR_A_D19 SA_DQ_18 SA_DQS_3 DDR_A_DQS4 DDR_B_D19 SB_DQ_18 SB_DQS_3 DDR_B_DQS4
BE40 SA_DQ_19 SA_DQS_4 BB16 BL43 SB_DQ_19 SB_DQS_4 BJ12
DDR_A_D20 BF44 BH6 DDR_A_DQS5 DDR_B_D20 BK47 BL7 DDR_B_DQS5

MEMORY
SA_DQ_20 SA_DQS_5 SB_DQ_20 SB_DQS_5

MEMORY
DDR_A_D21 BH45 BB2 DDR_A_DQS6 DDR_B_D21 BK49 BE2 DDR_B_DQS6
DDR_A_D22 SA_DQ_21 SA_DQS_6 DDR_A_DQS7 DDR_B_D22 SB_DQ_21 SB_DQS_6 DDR_B_DQS7
BG40 SA_DQ_22 SA_DQS_7 AP3 DDR_A_DQS#[0..7] <13> BK43 SB_DQ_22 SB_DQS_7 AV2 DDR_B_DQS#[0..7] <14>
DDR_A_D23 BF40 AT47 DDR_A_DQS#0 DDR_B_D23 BK42 AU50 DDR_B_DQS#0
DDR_A_D24 SA_DQ_23 SA_DQS#_0 DDR_A_DQS#1 DDR_B_D24 SB_DQ_23 SB_DQS#_0 DDR_B_DQS#1
AR40 SA_DQ_24 SA_DQS#_1 BD47 BJ41 SB_DQ_24 SB_DQS#_1 BC50
DDR_A_D25 AW40 BC41 DDR_A_DQS#2 DDR_B_D25 BL41 BL45 DDR_B_DQS#2
DDR_A_D26 SA_DQ_25 SA_DQS#_2 DDR_A_DQS#3 DDR_B_D26 SB_DQ_25 SB_DQS#_2 DDR_B_DQS#3
AT39 SA_DQ_26 SA_DQS#_3 BA37 BJ37 SB_DQ_26 SB_DQS#_3 BK38
DDR_A_D27 AW36 BA16 DDR_A_DQS#4 DDR_B_D27 BJ36 BK12 DDR_B_DQS#4
DDR_A_D28 SA_DQ_27 SA_DQS#_4 DDR_A_DQS#5 DDR_B_D28 SB_DQ_27 SB_DQS#_4 DDR_B_DQS#5
AW41 SA_DQ_28 SA_DQS#_5 BH7 BK41 SB_DQ_28 SB_DQS#_5 BK7
C DDR_A_D29 DDR_A_DQS#6 DDR_B_D29 DDR_B_DQS#6 C
AY41 SA_DQ_29 SA_DQS#_6 BC1 BJ40 SB_DQ_29 SB_DQS#_6 BF2
DDR_A_D30 AV38 AP2 DDR_A_DQS#7 DDR_B_D30 BL35 AV3 DDR_B_DQS#7
SA_DQ_30 SA_DQS#_7 DDR_A_MA[0..13] <13> SB_DQ_30 SB_DQS#_7
DDR_A_D31 AT38 DDR_B_D31 BK37 DDR_B_MA[0..13] <14>
DDR_A_D32 SA_DQ_31 DDR_A_MA0 DDR_B_D32 SB_DQ_31 DDR_B_MA0
AV13 SA_DQ_32 SA_MA_0 BJ19 BK13 SB_DQ_32 SB_MA_0 BC18
SYSTEM

DDR_A_D33 AT13 BD20 DDR_A_MA1 DDR_B_D33 BE11 BG28 DDR_B_MA1

SA_DQ_33 SA_MA_1 SB_DQ_33 SB_MA_1

SYSTEM
DDR_A_D34 AW11 BK27 DDR_A_MA2 DDR_B_D34 BK11 BG25 DDR_B_MA2
DDR_A_D35 SA_DQ_34 SA_MA_2 DDR_A_MA3 DDR_B_D35 SB_DQ_34 SB_MA_2 DDR_B_MA3
AV11 SA_DQ_35 SA_MA_3 BH28 BC11 SB_DQ_35 SB_MA_3 AW17
DDR_A_D36 AU15 BL24 DDR_A_MA4 DDR_B_D36 BC13 BF25 DDR_B_MA4
DDR_A_D37 SA_DQ_36 SA_MA_4 DDR_A_MA5 DDR_B_D37 SB_DQ_36 SB_MA_4 DDR_B_MA5
AT11 SA_DQ_37 SA_MA_5 BK28 BE12 SB_DQ_37 SB_MA_5 BE25
DDR_A_D38 BA13 BJ27 DDR_A_MA6 DDR_B_D38 BC12 BA29 DDR_B_MA6
DDR_A_D39 SA_DQ_38 SA_MA_6 DDR_A_MA7 DDR_B_D39 SB_DQ_38 SB_MA_6 DDR_B_MA7
BA11 SA_DQ_39 SA_MA_7 BJ25 BG12 SB_DQ_39 SB_MA_7 BC28
DDR_A_D40 BE10 BL28 DDR_A_MA8 DDR_B_D40 BJ10 AY28 DDR_B_MA8
DDR_A_D41 SA_DQ_40 SA_MA_8 DDR_A_MA9 DDR_B_D41 SB_DQ_40 SB_MA_8 DDR_B_MA9
BD10 SA_DQ_41 SA_MA_9 BA28 BL9 SB_DQ_41 SB_MA_9 BD37
DDR_A_D42 BD8 BC19 DDR_A_MA10 DDR_B_D42 BK5 BG17 DDR_B_MA10
DDR_A_D43 SA_DQ_42 SA_MA_10 DDR_A_MA11 DDR_B_D43 SB_DQ_42 SB_MA_10 DDR_B_MA11
AY9 SA_DQ_43 SA_MA_11 BE28 BL5 SB_DQ_43 SB_MA_11 BE37
DDR_A_D44 BG10 BG30 DDR_A_MA12 DDR_B_D44 BK9 BA39 DDR_B_MA12
DDR_A_D45 SA_DQ_44 SA_MA_12 DDR_A_MA13 DDR_B_D45 SB_DQ_44 SB_MA_12 DDR_B_MA13
AW9 SA_DQ_45 SA_MA_13 BJ16 BK10 SB_DQ_45 SB_MA_13 BG13
DDR

DDR_A_D46 BD7 DDR_B_D46 BJ8

DDR
DDR_A_D47 SA_DQ_46 DDR_B_D47 SB_DQ_46 DDR_B_RAS#
BB9 SA_DQ_47 BJ6 SB_DQ_47 SB_RAS# AV16 DDR_B_RAS# <14>
DDR_A_D48 BB5 BE18 DDR_A_RAS# DDR_B_D48 BF4 AY18 SB_RCVEN#
SA_DQ_48 SA_RAS# DDR_A_RAS# <13> SB_DQ_48 SB_RCVEN#
DDR_A_D49 AY7 AY20 SA_RCVEN# DDR_B_D49 BH5 T4
DDR_A_D50 SA_DQ_49 SA_RCVEN# T5 DDR_B_D50 SB_DQ_49 DDR_B_WE#
AT5 SA_DQ_50 BG1 SB_DQ_50 SB_WE# BC17 DDR_B_WE# <14>
DDR_A_D51 AT7 BA19 DDR_A_WE# DDR_A_WE# <13> DDR_B_D51 BC2
DDR_A_D52 SA_DQ_51 SA_WE# DDR_B_D52 SB_DQ_51
AY6 SA_DQ_52 BK3 SB_DQ_52
DDR_A_D53 BB7 DDR_B_D53 BE4
DDR_A_D54 SA_DQ_53 DDR_B_D54 SB_DQ_53
AR5 SA_DQ_54 BD3 SB_DQ_54
DDR_A_D55 AR8 DDR_B_D55 BJ2
DDR_A_D56 SA_DQ_55 DDR_B_D56 SB_DQ_55
AR9 SA_DQ_56 BA3 SB_DQ_56
DDR_A_D57 AN3 DDR_B_D57 BB3
DDR_A_D58 SA_DQ_57 DDR_B_D58 SB_DQ_57
AM8 SA_DQ_58 AR1 SB_DQ_58
DDR_A_D59 AN10 DDR_B_D59 AT3
DDR_A_D60 SA_DQ_59 DDR_B_D60 SB_DQ_59
AT9 SA_DQ_60 AY2 SB_DQ_60
B DDR_A_D61 DDR_B_D61 B
AN9 SA_DQ_61 AY3 SB_DQ_61
DDR_A_D62 AM9 DDR_B_D62 AU2
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AN11 SA_DQ_63 AT2 SB_DQ_63
CRESTLINE_1p0 CRESTLINE_1p0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((2/6)-DDR2 A/B CH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 8 of 57
5 4 3 2 1
 5 4 3 2 1

U15C
PEGCOMP trace width
R1176
+VCCP
and spacing is 20/25 mils. Strap Pin Table
J40 24.9_0402_1%
L_BKLT_CTRL PEGCOMP
H39 L_BKLT_EN PEG_COMPI N43 1 2
E39 L_CTRL_CLK PEG_COMPO M43 010 = FSB 800MHz
E40 L_CTRL_DATA PEG_RXN[0..15] <18>
C37 L_DDC_CLK CFG[2:0] FSB Freq select 011 = FSB 667MHz
D35 J51 PEG_RXN0
L_DDC_DATA PEG_RX#_0 PEG_RXN1
K40 L_VDD_EN PEG_RX#_1 L51 Others = Reserved
N47 PEG_RXN2
PEG_RX#_2 PEG_RXN3
L41 LVDS_IBG PEG_RX#_3 T45
L43 T50 PEG_RXN4 0 = DMI x 2
D LVDS_VBG PEG_RX#_4 PEG_RXN5 D
N41 LVDS_VREFH PEG_RX#_5 U40 CFG5 (DMI select)
N40 Y44 PEG_RXN6 1 = DMI x 4
D46
C45
LVDS_VREFL
LVDSA_CLK#
PEG_RX#_6
PEG_RX#_7 Y40
AB51
PEG_RXN7
PEG_RXN8
*
LVDSA_CLK PEG_RX#_8 PEG_RXN9
D44 LVDSB_CLK# PEG_RX#_9 W49 CFG6 Reserved
E42 AD44 PEG_RXN10
LVDSB_CLK PEG_RX#_10

LVDS
AD40 PEG_RXN11
PEG_RX#_11 PEG_RXN12
G51 LVDSA_DATA#_0 PEG_RX#_12 AG46 CFG7 (CPU Strap) 0 = Reserved
E51 AH49 PEG_RXN13
LVDSA_DATA#_1 PEG_RX#_13 PEG_RXN14
F49 AG45 1 = Mobile CPU
LVDSA_DATA#_2 PEG_RX#_14
PEG_RX#_15 AG41 PEG_RXN15
PEG_RXP[0..15] <18> *

GRAPHICS
G50 J50 PEG_RXP0 0 = Normal mode
LVDSA_DATA_0 PEG_RX_0 PEG_RXP1
E50 LVDSA_DATA_1 PEG_RX_1 L50 CFG8 (Low power PCIE)
F48 M47 PEG_RXP2 1 = Low Power mode
LVDSA_DATA_2 PEG_RX_2
PEG_RX_3 U44
T49
PEG_RXP3
PEG_RXP4
*
PEG_RX_4 PEG_RXP5
G44 LVDSB_DATA#_0 PEG_RX_5 T41 CFG9 0 = Reverse Lane
B47 W45 PEG_RXP6
LVDSB_DATA#_1 PEG_RX_6 PEG_RXP7
B45 W41 (PCIE Graphics Lane Reversal) 1 = Normal Operation
LVDSB_DATA#_2 PEG_RX_7
PEG_RX_8 AB50
Y48
PEG_RXP8
PEG_RXP9
*
PEG_RX_9 PEG_RXP10
E44 LVDSB_DATA_0 PEG_RX_10 AC45
A47 AC41 PEG_RXP11 CFG[11:10] Reserved
LVDSB_DATA_1 PEG_RX_11 PEG_RXP12
A45 LVDSB_DATA_2 PEG_RX_12 AH47

PCI-EXPRESS
AG49 PEG_RXP13
PEG_RX_13
AH45 PEG_RXP14 00 = Reserved
PEG_RX_14 PEG_RXP15 01 = XOR Mode Enabled
PEG_RX_15 AG42 PEG_M_TXN[0..15] <18> CFG[13:12] (XOR/ALLZ)
10 = All Z Mode Enabled
E27 N45 PEG_TXN0 C1058 1 2 0.1U_0402_16V4Z PEG_M_TXN0 11 = Normal Operation(Default)
G27
K27
TVA_DAC
TVB_DAC
PEG_TX#_0
PEG_TX#_1 U39
U47
PEG_TXN1
PEG_TXN2
C1059 1
C1060 1
2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
PEG_M_TXN1
PEG_M_TXN2
*
TVC_DAC PEG_TX#_2

TV
C PEG_TXN3 C1559 1 PEG_M_TXN3 C
PEG_TX#_3 N51 2 0.1U_0402_16V4Z CFG[15:14] Reserved
F27 R50 PEG_TXN4 C1562 0.1U_0402_16V4Z PEG_M_TXN4
TVA_RTN PEG_TX#_4 PEG_TXN5 C1563 0.1U_0402_16V4Z PEG_M_TXN5
J27 TVB_RTN PEG_TX#_5 T42
L27 Y43 PEG_TXN6 C1560 0.1U_0402_16V4Z PEG_M_TXN6 CFG16 (FSB Dynamic ODT) 0 = Disabled
TVC_RTN PEG_TX#_6 PEG_TXN7 C1561 0.1U_0402_16V4Z PEG_M_TXN7
PEG_TX#_7 W46
M35 W38 PEG_TXN8 C1564 0.1U_0402_16V4Z PEG_M_TXN8 1 = Enabled
P33
TV_DCONSEL_0
TV_DCONSEL_1
PEG_TX#_8
PEG_TX#_9 AD39
AC46
PEG_TXN9
PEG_TXN10
C1361
C1362
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_M_TXN9
PEG_M_TXN10
*
PEG_TX#_10 PEG_TXN11 C1363 0.1U_0402_16V4Z PEG_M_TXN11
PEG_TX#_11 AC49 CFG[18:17] Reserved
AC42 PEG_TXN12 C1364 0.1U_0402_16V4Z PEG_M_TXN12
PEG_TX#_12 PEG_TXN13 C1365 0.1U_0402_16V4Z PEG_M_TXN13
PEG_TX#_13 AH39
AE49 PEG_TXN14 C1366 0.1U_0402_16V4Z PEG_M_TXN14 0 = No SDVO Device Present
PEG_TX#_14
PEG_TX#_15 AH44 PEG_TXN15 C1367 0.1U_0402_16V4Z PEG_M_TXN15 PEG_M_TXP[0..15] <18> SDVO_CTRLDATA
1 = SDVO Device Present
*
H32 M45 PEG_TXP0 C1062 1 2 0.1U_0402_16V4Z PEG_M_TXP0
CRT_BLUE PEG_TX_0 PEG_TXP1 C1063 1 PEG_M_TXP1
G32 CRT_BLUE# PEG_TX_1 T38 2 0.1U_0402_16V4Z
K29 T46 PEG_TXP2 C1066 1 2 0.1U_0402_16V4Z PEG_M_TXP2 0 = Normal Operation
J29
F29
CRT_GREEN
CRT_GREEN#
PEG_TX_2
PEG_TX_3 N50
R51
PEG_TXP3
PEG_TXP4
C1067 1
C1368
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_M_TXP3
PEG_M_TXP4
CFG19 (DMI Lane Reversal) (Lane number in Order) *
CRT_RED PEG_TX_4
VGA

E29 U43 PEG_TXP5 C1369 0.1U_0402_16V4Z PEG_M_TXP5 1 = Reverse Lane

CRT_RED# PEG_TX_5 PEG_TXP6 C1370 0.1U_0402_16V4Z PEG_M_TXP6
PEG_TX_6 W42
Y47 PEG_TXP7 C1371 0.1U_0402_16V4Z PEG_M_TXP7
PEG_TX_7 PEG_TXP8 C1372 0.1U_0402_16V4Z PEG_M_TXP8
K33 Y39 0 = Only PCIE or SDVO is operational.
G35
F33
CRT_DDC_CLK
CRT_DDC_DATA
PEG_TX_8
PEG_TX_9 AC38
AD47
PEG_TXP9
PEG_TXP10
C1373
C1374
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_M_TXP9
PEG_M_TXP10
CFG20 (PCIE/SDVO concurrent)
1 = PCIE/SDVO are operating simu.
*
CRT_HSYNC PEG_TX_10 PEG_TXP11 C1375 0.1U_0402_16V4Z PEG_M_TXP11
C32 CRT_TVO_IREF PEG_TX_11 AC50
E33 AD43 PEG_TXP12 C1376 0.1U_0402_16V4Z PEG_M_TXP12
CRT_VSYNC PEG_TX_12 PEG_TXP13 C1377 0.1U_0402_16V4Z PEG_M_TXP13
PEG_TX_13 AG39 J37
AE50 PEG_TXP14 C1378 0.1U_0402_16V4Z PEG_M_TXP14 R1151 1 2 @ 4.02K_0402_1%
PEG_TX_14 <7> CFG5
AH43 PEG_TXP15 C1379 0.1U_0402_16V4Z PEG_M_TXP15 CFG5 2 1
PEG_TX_15
R1152 1 2 @ 4.02K_0402_1%
B PAD-NO SHORT 2x2m <7> CFG7 B
CRESTLINE_1p0

R1451 1 2 @ 4.02K_0402_1%
<7> CFG8

R1153 1 2 @ 4.02K_0402_1%
<7> CFG9

R1155 1 2 @ 4.02K_0402_1%
<7> CFG12

R1156 1 2 @ 4.02K_0402_1%
<7> CFG13

R1157 1 2 @ 4.02K_0402_1%
<7> CFG16

CFG[17:3] have internal pull up

CFG[19:18] have internal pull down

+3VS

R1159 1 2 @ 4.02K_0402_1%
<7> CFG19

R1160 1 2 @ 4.02K_0402_1%
<7> CFG20

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((3/6)-VGA/LVDS/TV
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 9 of 57
5 4 3 2 1
 5 4 3 2 1

+V1.25VS_AXF +1.25VS
+VCCP +1.25VS_DMI +1.25VS
1 2

10U_0603_6.3V6M

1U_0603_10V4Z
U15H 1 2
R1455

0.1U_0402_16V4Z
J32 U13 330U_D2E_2.5VM_R15 R1457 1 1 0_0603_5%
VCCSYNC VTT_1

4.7U_0603_6.3V6M

C1111

C1112
U12 0_0603_5%
VTT_2
A33 VCCA_CRT_DAC_1 VTT_3 U11 1 1 1

C1117
B33 VCCA_CRT_DAC_2 VTT_4 U9
+ 2 2

C838
U8 C830
VTT_5

CRT
VTT_6 U7
D A30 U5 2 2 D
VCCA_DAC_BG VTT_7 2
VTT_8 U3
B32 VSSA_DAC_BG VTT_9 U2
VTT_10 U1
T13 +1.25VS
VTT_11 +1.25VS_PEGPLL +1.8V_SM_CK

VTT
B49 T11 L77 +1.8V
VCCA_DPLLA VTT_12

0.47U_0603_10V7K

4.7U_0603_6.3V6M

2.2U_0603_6.3V4Z
T10 R1458
VTT_13
H49 VCCA_DPLLB VTT_14 T9 1 1 1 2 1 1 2

22U_0805_6.3VAM

22U_0805_6.3VAM

0.1U_0402_16V4Z
T7 MBK2012221YZF_0805 0_0805_5%
VTT_15

1
PLL

C849

C836

C837
+1.25VM_HPLL AL2 VCCA_HPLL VTT_16 T6 1 1
T5 R1468 1
VTT_17 2 2 2

C1230

C1115

C1116
+1.25VM_MPLL AM2 T3 1_0402_5%
VCCA_MPLL VTT_18
VTT_19 T2
2 2
R3

2
VTT_20 2

A LVDS
A41 VCCA_LVDS VTT_21 R2 1
R1 C1123
VTT_22 +1.25VM_AXD
B41 VSSA_LVDS R1671 10U_0603_6.3V6M
+3VS_PEG_BG
AT23
250mA 1 2
2
VCC_AXD_1 +1.25VM
R1459 AU28 0_0805_5%
VCC_AXD_2

1U_0402_6.3V4Z

10U_0603_6.3V6M
+3VS 2 1 K50 VCCA_PEG_BG VCC_AXD_3 AU24 1 1 0904 change

C1119

C1120
AXD
0_0603_5% AT29 +VCCP
VCC_AXD_4 +1.5VS_TVDAC +1.5VS
1 K49 VSSA_PEG_BG VCC_AXD_5 AT25
+VCC_PEG

A PEG
0.1U_0402_16V4Z AT30 R1460
VCC_AXD_6 2 2 R1465
+1.25VS_PEGPLL 1 2

0.022U_0402_16V7K

0.1U_0402_16V4Z
C1121 20 mils U51 AR29 2 1 0_0805_5%
2 VCCA_PEG_PLL VCC_AXD_NCTF

10U_0603_6.3V6M
1 0_0805_5%

10U_0603_6.3V6M
1 1 1 1

220U_D2_4VM_R15

C1607
C1606 AW18 B23 +V1.25VS_AXF 1
VCCA_SM_1 VCC_AXF_1 +1.25VS

C1227

C1138

C1124

C1125
0.1U_0402_16V4Z AV19 B21 +
2 VCCA_SM_2
POWER VCC_AXF_2 R1467

AXF
AU19 A21 @
VCCA_SM_3 VCC_AXF_3 2 2 2
+1.25VM_A_SM AU18 VCCA_SM_4 1 2
2 2 100NH_LQW18ANR10J00D_5%_0805
AU17 VCCA_SM_5 VCC_DMI AJ50 +1.25VS_DMI
R1461 0317 change value (link CIS)

A SM
C +1.25VM 1 2 AT22 VCCA_SM_7 C
1 0_0805_5% AT21 BK24 +1.8V_SM_CK
VCCA_SM_8 VCC_SM_CK_1

SM CK
1 1 1 AT19 VCCA_SM_9 VCC_SM_CK_2 BK23
C1126 + C1127 C1128 C1129 AT18 BJ24
VCCA_SM_10 VCC_SM_CK_3
AT17 VCCA_SM_11 VCC_SM_CK_4 BJ23
150U_D_6.3VM 22U_0805_6.3VAM 4.7U_0603_6.3V6M AR17 +1.25VM_HPLL
2 2 2 2 VCCA_SM_NCTF_1 R1464 +1.25VM
AR16 VCCA_SM_NCTF_2
1U_0603_10V4Z +1.25VM_MPLL
R1462 +1.25VM_A_SM_CK R1466 +1.25VM
VCC_TX_LVDS A43 2 1

A CK
2 1 BC29 MBK2012121YZF_0805
VCCA_SM_CK_1 +3VS_HV
1U_0402_6.3V4Z

22U_0805_6.3VAM

1U_0603_10V4Z

0.1U_0402_16V4Z

0_0603_5% BB29 2 1
VCCA_SM_CK_2 MBK2012121YZF_0805
VCC_HV_1 C40 1 1
C1134 C1135

0.1U_0402_16V4Z
1 1 1 1 C25 VCCA_TVA_DAC_1 VCC_HV_2 B40
C1226

C1130

C1131

C1132

0.1U_0402_16V4Z
HV
B25 VCCA_TVA_DAC_2 1 1
C27 1 C1140 0.1U_0402_16V4Z 22U_0805_6.3VAM
VCCA_TVB_DAC_1 2 2

C1136
B27 VCCA_TVB_DAC_2 VCC_PEG_1 AD51 +VCC_PEG
2 2 2 2
TV

B28 VCCA_TVC_DAC_1 VCC_PEG_2 W50

2 C1139 2

PEG
A28 VCCA_TVC_DAC_2 VCC_PEG_3 W51
2 22U_0805_6.3VAM
VCC_PEG_4 V49
VCC_PEG_5 V50
D TV/CRT

M32 VCCD_CRT
+1.5VS_TVDAC L29 VCCD_TVDAC
VCC_RXR_DMI_1 AH50 +VCC_DMI
DMI

N28 VCCD_QDAC VCC_RXR_DMI_2 AH51

20mils +VCCP_D
+1.25VM_HPLL AN2 VCCD_HPLL
1 +1.25VS_PEGPLL VTTLF1 A7
VTTLF

U48 VCCD_PEG_PLL VTTLF2 F2

C1608 1 AH1 D12 R1469
0.1U_0402_16V4Z VTTLF3
J41 VCCD_LVDS_1 +VCCP 2 1 2 1 +3VS_HV
2 0.47U_0402_10V4Z~D

0.47U_0402_10V4Z~D

0.47U_0402_10V4Z~D
LVDS

H42 10_0402_5%
VCCD_LVDS_2 CH751H-40PT_SOD323-2
1 1 1
C1122 2
C1141

C1142

C1143
+3VS 2 1
0.1U_0402_16V4Z 0_0402_5%
CRESTLINE_1p0 R1470
B
2 2 2 B

0904 change

+VCC_DMI +1.25VS
@
L94
1 2
100NH_LQW18ANR10J00D_5%_0805
(link CIS)
1 1
C1615
C1614 1 2 +VCCP
10U_0603_6.3V6M
2 2 R84
0_0805_5%

10U_0603_6.3V6M

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE(4/6)-PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 10 of 57
5 4 3 2 1
 5 4 3 2 1

+VCCP
U15G

AT35 VCC_1
AT34 VCC_2 VCC_AXG_NCTF_1 T17
AH28 VCC_3 VCC_AXG_NCTF_2 T18
AC32 VCC_5 VCC_AXG_NCTF_3 T19
AC31 VCC_4 VCC_AXG_NCTF_4 T21
AK32 VCC_6 VCC_AXG_NCTF_5 T22
AJ31 VCC_7 VCC_AXG_NCTF_6 T23
+VCCP AJ28 T25
D U15F VCC_8 VCC_AXG_NCTF_7 D
AH32 VCC_9 VCC_AXG_NCTF_8 U15

VCC CORE
AH31 VCC_10 VCC_AXG_NCTF_9 U16
AB33 VCC_NCTF_1 AH29 VCC_11 VCC_AXG_NCTF_10 U17
AB36 VCC_NCTF_2 AF32 VCC_12 VCC_AXG_NCTF_11 U19
AB37 VCC_NCTF_3 VCC_AXG_NCTF_12 U20
AC33 VCC_NCTF_4 VSS_NCTF_1 T27 VCC_AXG_NCTF_13 U21
AC35 T37 R1475 U23
VCC_NCTF_5 VSS_NCTF_2 VCC_AXG_NCTF_14
AC36 VCC_NCTF_6 VSS_NCTF_3 U24 1 2 R30 VCC_13 VCC_AXG_NCTF_15 U26
AD35 U28 0_0603_5% V16
VCC_NCTF_7 VSS_NCTF_4 VCC_AXG_NCTF_16
AD36 VCC_NCTF_8 VSS_NCTF_5 V31 VCC_AXG_NCTF_17 V17
AF33 VCC_NCTF_9 VSS_NCTF_6 V35 VCC_AXG_NCTF_18 V19
AF36 VCC_NCTF_10 VSS_NCTF_7 AA19 VCC_AXG_NCTF_19 V20
220U_D2_4VM_R15

22U_0805_6.3VAM

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z

AH33 VCC_NCTF_11 VSS_NCTF_8 AB17 VCC_AXG_NCTF_20 V21

VSS NCTF
1 AH35 VCC_NCTF_12 VSS_NCTF_9 AB35 VCC_AXG_NCTF_21 V23
1 1 1 1 AH36 VCC_NCTF_13 VSS_NCTF_10 AD19 VCC_AXG_NCTF_22 V24
C806

C803

C796

C798

C797

+ AH37 AD37 Y15

2 2 2 2 2
AJ33
AJ35
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
AF17
AF35
POWER VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
Y16
Y17
AK33 VCC_NCTF_17 VSS_NCTF_14 AK17 AU32 VCC_SM_1 VCC_AXG_NCTF_26 Y19
AK35 AM17 330U_D2E_2.5VM_R15 AU33 Y20
VCC_NCTF_18 VSS_NCTF_15 VCC_SM_2 VCC_AXG_NCTF_27
AK36 VCC_NCTF_19 VSS_NCTF_16 AM24 +1.8V AU35 VCC_SM_3 VCC_AXG_NCTF_28 Y21
AK37 VCC_NCTF_20 VSS_NCTF_17 AP26 AV33 VCC_SM_4 VCC_AXG_NCTF_29 Y23

0.01U_0402_16V7K
AD33 VCC_NCTF_21 VSS_NCTF_18 AP28 AW33 VCC_SM_5 VCC_AXG_NCTF_30 Y24

22U_0805_6.3VAM

22U_0805_6.3VAM
AJ36 VCC_NCTF_22 VSS_NCTF_19 AR15 1 AW35 VCC_SM_6 VCC_AXG_NCTF_31 Y26

VCC NCTF
AM35 VCC_NCTF_23 VSS_NCTF_20 AR19 1 1 2 AY35 VCC_SM_7 VCC_AXG_NCTF_32 Y28

C809

C810

C794
AL33 AR28 C808 + BA32 Y29
VCC_NCTF_24 VSS_NCTF_21 VCC_SM_8 VCC_AXG_NCTF_33
AL35 VCC_NCTF_25 BA33 VCC_SM_9 VCC_AXG_NCTF_34 AA16
AA33 VCC_NCTF_26 BA35 VCC_SM_10 VCC_AXG_NCTF_35 AA17
2 2 2 1
AA35 VCC_NCTF_27 BB33 VCC_SM_11 VCC_AXG_NCTF_36 AB16
AA36 VCC_NCTF_28 BC32 VCC_SM_12 VCC_AXG_NCTF_37 AB19
AP35 VCC_NCTF_29 BC33 VCC_SM_13 VCC_AXG_NCTF_38 AC16
AP36 0_0402_5% BC35 AC17
VCC_NCTF_30 VCC_SM_14 VCC_AXG_NCTF_39

VCC SM
C 0_0402_5% C
AR35 VCC_NCTF_31 BD32 VCC_SM_15 VCC_AXG_NCTF_40 AC19
AR36 0_0402_5% BD35 AD15
VCC_NCTF_32 0_0402_5% VCC_SM_16 VCC_AXG_NCTF_41
Y32 VCC_NCTF_33 BE32 VCC_SM_17 VCC_AXG_NCTF_42 AD16
Y33 0_0402_5% BE33 AD17
VCC_NCTF_34
POWER VCC_SM_18 VCC_AXG_NCTF_43

VCC GFX NCTF

Y35 0_0402_5% BE35 AF16
VCC_NCTF_35 VCC_SM_19 VCC_AXG_NCTF_44
Y36 VCC_NCTF_36 BF33 VCC_SM_20 VCC_AXG_NCTF_45 AF19
Y37 A3 MCHGND1 R112 1 2 BF34 AH15
VCC_NCTF_37 VSS_SCB1 MCHGND2 R132 VCC_SM_21 VCC_AXG_NCTF_46
T30 VCC_NCTF_38 VSS_SCB2 B2 1 2 BG32 VCC_SM_22 VCC_AXG_NCTF_47 AH16
VSS SCB
T34 C1 MCHGND3 R133 1 2 BG33 AH17
VCC_NCTF_39 VSS_SCB3 MCHGND4 R122 VCC_SM_23 VCC_AXG_NCTF_48
T35 VCC_NCTF_40 VSS_SCB4 BL1 1 2 BG35 VCC_SM_24 VCC_AXG_NCTF_49 AH19
U29 BL51 MCHGND5 R113 1 2 BH32 AJ16
VCC_NCTF_41 VSS_SCB5 MCHGND6 R111 VCC_SM_25 VCC_AXG_NCTF_50
U31 VCC_NCTF_42 VSS_SCB6 A51 1 2 BH34 VCC_SM_26 VCC_AXG_NCTF_51 AJ17
U32 VCC_NCTF_43 BH35 VCC_SM_27 VCC_AXG_NCTF_52 AJ19
U33 VCC_NCTF_44 BJ32 VCC_SM_28 VCC_AXG_NCTF_53 AK16
U35 VCC_NCTF_45 BJ33 VCC_SM_29 VCC_AXG_NCTF_54 AK19
U36 VCC_NCTF_46 BJ34 VCC_SM_30 VCC_AXG_NCTF_55 AL16
V32 VCC_NCTF_47 BK32 VCC_SM_31 VCC_AXG_NCTF_56 AL17
V33 VCC_NCTF_48 BK33 VCC_SM_32 VCC_AXG_NCTF_57 AL19
V36 VCC_NCTF_49 BK34 VCC_SM_33 VCC_AXG_NCTF_58 AL20
V37 VCC_NCTF_50 BK35 VCC_SM_34 VCC_AXG_NCTF_59 AL21
BL33 VCC_SM_35 VCC_AXG_NCTF_60 AL23
+1.05VM
VCC_AXM_1 AT33 +1.05VM AU30 VCC_SM_36 VCC_AXG_NCTF_61 AM15
VCC_AXM_2 AT31 VCC_AXG_NCTF_62 AM16
VCC AXM

VCC_AXM_3 AK29 VCC_AXG_NCTF_63 AM19

VCC_AXM_4 AK24 VCC_AXG_NCTF_64 AM20
10U_0603_6.3V6M

10U_0603_6.3V6M

VCC_AXM_5 AK23 VCC_AXG_NCTF_65 AM21

1 1 AL24 VCC_AXM_NCTF_1 VCC_AXM_6 AJ26 R20 VCC_AXG_1 VCC_AXG_NCTF_66 AM23
C1154

C1155

AL26 VCC_AXM_NCTF_2 VCC_AXM_7 AJ23 T14 VCC_AXG_2 VCC_AXG_NCTF_67 AP15

AL28 VCC_AXM_NCTF_3 W13 VCC_AXG_3 VCC_AXG_NCTF_68 AP16
AM26 VCC_AXM_NCTF_4 W14 VCC_AXG_4 VCC_AXG_NCTF_69 AP17
2 2
VCC AXM NCTF

AM28 VCC_AXM_NCTF_5 Y12 VCC_AXG_5 VCC_AXG_NCTF_70 AP19

AM29 VCC_AXM_NCTF_6 AA20 VCC_AXG_6 VCC_AXG_NCTF_71 AP20
B B
AM31 VCC_AXM_NCTF_7 AA23 VCC_AXG_7 VCC_AXG_NCTF_72 AP21
AM32 VCC_AXM_NCTF_8 AA26 VCC_AXG_8 VCC_AXG_NCTF_73 AP23
AM33 VCC_AXM_NCTF_9 AA28 VCC_AXG_9 VCC_AXG_NCTF_74 AP24
AP29 VCC_AXM_NCTF_10 AB21 VCC_AXG_10 VCC_AXG_NCTF_75 AR20
AP31 VCC_AXM_NCTF_11 AB24 VCC_AXG_11 VCC_AXG_NCTF_76 AR21
AP32 VCC_AXM_NCTF_12 AB29 VCC_AXG_12 VCC_AXG_NCTF_77 AR23
AP33 VCC_AXM_NCTF_13 AC20 VCC_AXG_13 VCC_AXG_NCTF_78 AR24

VCC GFX
AL29 VCC_AXM_NCTF_14 AC21 VCC_AXG_14 VCC_AXG_NCTF_79 AR26
AL31 VCC_AXM_NCTF_15 AC23 VCC_AXG_15 VCC_AXG_NCTF_80 V26
AL32 VCC_AXM_NCTF_16 AC24 VCC_AXG_16 VCC_AXG_NCTF_81 V28
AR31 VCC_AXM_NCTF_17 AC26 VCC_AXG_17 VCC_AXG_NCTF_82 V29
AR32 VCC_AXM_NCTF_18 AC28 VCC_AXG_18 VCC_AXG_NCTF_83 Y31
0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

AR33 VCC_AXM_NCTF_19 AC29 VCC_AXG_19

1 1 1 1 1 AD20 VCC_AXG_20
C1157

C1158

C1159

C1160

C1161

AD23 VCC_AXG_21
AD24 VCC_AXG_22 VCC_SM_LF1 AW45 VCCSM_LF1
AD28 VCC_AXG_23 VCC_SM_LF2 BC39 VCCSM_LF2
2 2 2 2 2

VCC SM LF
CRESTLINE_1p0 AF21 BE39 VCCSM_LF3
VCC_AXG_24 VCC_SM_LF3
AF26 VCC_AXG_25 VCC_SM_LF4 BD17 VCCSM_LF4
AA31 VCC_AXG_26 VCC_SM_LF5 BD4 VCCSM_LF5
AH20 VCC_AXG_27 VCC_SM_LF6 AW8 VCCSM_LF6
AH21 VCC_AXG_28 VCC_SM_LF7 AT6 VCCSM_LF7

C1162 0.1U_0402_16V4Z

C1163 0.1U_0402_16V4Z

C1318 0.22U_0603_10V7K

C795 0.22U_0603_10V7K

C1164 0.47U_0402_10V4Z~D

C814 1U_0603_10V4Z

C813 1U_0603_10V4Z
AH23 VCC_AXG_29 1 1 1 1 1 1 1
AH24 VCC_AXG_30
AH26 VCC_AXG_31
AD31 VCC_AXG_32 2 2 2 2 2 2 2
AJ20 VCC_AXG_33
AN14 VCC_AXG_34

04/10 monitor NB crack +3VL

+3VS
A +3VS +3VS +3VS A
2
100K_0402_5%

2
100K_0402_5%

100K_0402_5%

@ R1711
@R1711 @ R1709 CRESTLINE_1p0
2

100K_0402_5% CRACK_GPIO28 R1702

@R1701
@ R1701 CRACK_GPIO28 CRACK_GPIO28
@R1703
@ R1703 CRACK_GPIO28
1 1
1

D 100K_0402_5% CRACK_GPIO28 <27,37>

1
1

D D MCHGND2 D
2 Security Classification Compal Secret Data Compal Electronics, Inc.
1

MCHGND6 2 MCHGND4 2 G MCHGND5 2

G G @ Q121 S G Issued Date 2006/09/25 2006/09/25 Title
Deciphered Date
3

@ Q118 S @ Q123 S RHU002N06_SOT323 S

CRESTLINE((5/6)-PWR/GND
3

RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323

@ Q119 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 11 of 57
5 4 3 2 1
 5 4 3 2 1

U15I

A13 VSS_1 VSS_100 AW24

A15 VSS_2 VSS_101 AW29
A17 VSS_3 VSS_102 AW32
A24 VSS_4 VSS_103 AW5
AA21 VSS_5 VSS_104 AW7
AA24 VSS_6 VSS_105 AY10
AA29 VSS_7 VSS_106 AY24
AB20 AY37 U15J
D VSS_8 VSS_107 D
AB23 VSS_9 VSS_108 AY42 C46 VSS_199 VSS_287 W11
AB26 VSS_10 VSS_109 AY43 C50 VSS_200 VSS_288 W39
AB28 VSS_11 VSS_110 AY45 C7 VSS_201 VSS_289 W43
AB31 VSS_12 VSS_111 AY47 D13 VSS_202 VSS_290 W47
AC10 VSS_13 VSS_112 AY50 D24 VSS_203 VSS_291 W5
AC13 VSS_14 VSS_113 B10 D3 VSS_204 VSS_292 W7
AC3 VSS_15 VSS_114 B20 D32 VSS_205 VSS_293 Y13
AC39 VSS_16 VSS_115 B24 D39 VSS_206 VSS_294 Y2
AC43 VSS_17 VSS_116 B29 D45 VSS_207 VSS_295 Y41
AC47 VSS_18 VSS_117 B30 D49 VSS_208 VSS_296 Y45
AD1 VSS_19 VSS_118 B35 E10 VSS_209 VSS_297 Y49
AD21 VSS_20 VSS_119 B38 E16 VSS_210 VSS_298 Y5
AD26 VSS_21 VSS_120 B43 E24 VSS_211 VSS_299 Y50
AD29 VSS_22 VSS_121 B46 E28 VSS_212 VSS_300 Y11
AD3 VSS_23 VSS_122 B5 E32 VSS_213 VSS_301 P29
AD41 VSS_24 VSS_123 B8 E47 VSS_214 VSS_302 T29
AD45 VSS_25 VSS_124 BA1 F19 VSS_215 VSS_303 T31
AD49 VSS_26 VSS_125 BA17 F36 VSS_216 VSS_304 T33
AD5 VSS_27 VSS_126 BA18 F4 VSS_217 VSS_305 R28
AD50 VSS_28 VSS_127 BA2 F40 VSS_218
AD8 VSS_29 VSS_128 BA24 F50 VSS_219
AE10 VSS_30 VSS_129 BB12 G1 VSS_220
AE14 VSS_31 VSS_130 BB25 G13 VSS_221 VSS_306 AA32
AE6 VSS_32 VSS_131 BB40 G16 VSS_222 VSS_307 AB32
AF20 BB44 G19 AD32
AF23
AF24
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
BB49
BB8
G24
G28
VSS_223
VSS_224
VSS_225
VSS_308
VSS_309
VSS_310
AF28
AF29
AF31 VSS_36 VSS_135 BC16 G29 VSS_226 VSS_311 AT27
AG2 VSS_37 VSS_136 BC24 G33 VSS_227 VSS_312 AV25
AG38 VSS_38 VSS_137 BC25 G42 VSS_228 VSS_313 H50
AG43 VSS_39 VSS_138 BC36 G45 VSS_229
AG47 VSS_40 VSS_139 BC40 G48 VSS_230
C C
AG50 VSS_41 VSS_140 BC51 G8 VSS_231
AH3 VSS_42 VSS_141 BD13 H24 VSS_232
AH40 VSS_43 VSS_142 BD2 H28 VSS_233
AH41 VSS_44 VSS_143 BD28 H4 VSS_234
AH7 VSS_45 VSS_144 BD45 H45 VSS_235
AH9 VSS_46 VSS_145 BD48 J11 VSS_236
AJ11 VSS_47 VSS_146 BD5 J16 VSS_237
AJ13 VSS_48 VSS_147 BE1 J2 VSS_238
AJ21 VSS_49 VSS_148 BE19 J24 VSS_239
AJ24 VSS_50 VSS_149 BE23 J28 VSS_240
AJ29 BE30 J33
AJ32
AJ43
VSS_51
VSS_52
VSS_53
VSS_150
VSS_151
VSS_152
BE42
BE51
J35
J39
VSS_241
VSS_242
VSS_243
VSS
AJ45 VSS_54 VSS_153 BE8
AJ49 VSS_55 VSS_154 BF12 K12 VSS_245
AK20 VSS_56 VSS_155 BF16 K47 VSS_246
AK21 VSS_57 VSS_156 BF36 K8 VSS_247
AK26 VSS_58 VSS_157 BG19 L1 VSS_248
AK28 VSS_59 VSS_158 BG2 L17 VSS_249
AK31 VSS_60 VSS_159 BG24 L20 VSS_250
AK51 VSS_61 VSS_160 BG29 L24 VSS_251
AL1 VSS_62 VSS_161 BG39 L28 VSS_252
AM11 VSS_63 VSS_162 BG48 L3 VSS_253
AM13 VSS_64 VSS_163 BG5 L33 VSS_254
AM3 VSS_65 VSS_164 BG51 L49 VSS_255
AM4 VSS_66 VSS_165 BH17 M28 VSS_256
AM41 VSS_67 VSS_166 BH30 M42 VSS_257
AM45 VSS_68 VSS_167 BH44 M46 VSS_258
AN1 VSS_69 VSS_168 BH46 M49 VSS_259
AN38 VSS_70 VSS_169 BH8 M5 VSS_260
AN39 VSS_71 VSS_170 BJ11 M50 VSS_261
AN43 VSS_72 VSS_171 BJ13 M9 VSS_262
B B
AN5 VSS_73 VSS_172 BJ38 N11 VSS_263
AN7 VSS_74 VSS_173 BJ4 N14 VSS_264
AP4 VSS_75 VSS_174 BJ42 N17 VSS_265
AP48 VSS_76 VSS_175 BJ46 N29 VSS_266
AP50 VSS_77 VSS_176 BK15 N32 VSS_267
AR11 VSS_78 VSS_177 BK17 N36 VSS_268
AR2 VSS_79 VSS_178 BK25 N39 VSS_269
AR39 VSS_80 VSS_179 BK29 N44 VSS_270
AR44 VSS_81 VSS_180 BK36 N49 VSS_271
AR47 VSS_82 VSS_181 BK40 N7 VSS_272
AR7 VSS_83 VSS_182 BK44 P19 VSS_273
AT10 VSS_84 VSS_183 BK6 P2 VSS_274
AT14 VSS_85 VSS_184 BK8 P23 VSS_275
AT41 VSS_86 VSS_185 BL11 P3 VSS_276
AT49 VSS_87 VSS_186 BL13 P50 VSS_277
AU1 VSS_88 VSS_187 BL19 R49 VSS_278
AU23 VSS_89 VSS_188 BL22 T39 VSS_279
AU29 VSS_90 VSS_189 BL37 T43 VSS_280
AU3 VSS_91 VSS_190 BL47 T47 VSS_281
AU36 VSS_92 VSS_191 C12 U41 VSS_282
AU49 VSS_93 VSS_192 C16 U45 VSS_283
AU51 VSS_94 VSS_193 C19 U50 VSS_284
AV39 VSS_95 VSS_194 C28 V2 VSS_285
AV48 VSS_96 VSS_195 C29 V3 VSS_286
AW1 VSS_97 VSS_196 C33
AW12 VSS_98 VSS_197 C36
AW16 C41 CRESTLINE_1p0
VSS_99 VSS_198

CRESTLINE_1p0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((6/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 12 of 57
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V

V_DDR_MCH_REF
<8> DDR_A_DQS#[0..7] V_DDR_MCH_REF <7,14,48>

<8> DDR_A_D[0..63] JP34

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2
3 4 DDR_A_D6 1 1
<8> DDR_A_DM[0..7] VSS DQ4

C363

C362
DDR_A_D4 5 6 DDR_A_D0
DDR_A_D1 DQ0 DQ5
<8> DDR_A_DQS[0..7] 7 DQ1 VSS 8
9 10 DDR_A_DM0
DDR_A_DQS#0 VSS DM0 2 2
<7,8> DDR_A_MA[0..14] 11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D5
DQS0 DQ6 DDR_A_D7
15 VSS DQ7 16
DDR_A_D2 17 18
D DDR_A_D3 DQ2 VSS DDR_A_D13 D
19 DQ3 DQ12 20
21 22 DDR_A_D12
DDR_A_D8 VSS DQ13
23 DQ8 VSS 24
Layout Note: DDR_A_D14 25 26 DDR_A_DM1
DQ9 DM1
27 VSS VSS 28
Place near JP34 DDR_A_DQS#1 29 30 M_CLK_DDR0
M_CLK_DDR0 <7>
DDR_A_DQS1 DQS1# CK0 M_CLK_DDR#0
31 DQS1 CK0# 32 M_CLK_DDR#0 <7>
33 VSS VSS 34
DDR_A_D9 35 36 DDR_A_D11
DDR_A_D15 DQ10 DQ14 DDR_A_D10
37 DQ11 DQ15 38
39 VSS VSS 40
+1.8V
41 VSS VSS 42
DDR_A_D16 43 44 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
45 DQ17 DQ21 46
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
47 VSS VSS 48
1 1 1 1 1 1 1 1 1 DDR_A_DQS#2 49 50
DQS2# NC PM_EXTTS#0 <7>
C458

C498

C473

C491

C465

C255

C242

C280

C235
DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
53 VSS VSS 54
DDR_A_D18 55 56 DDR_A_D23
2 2 2 2 2 2 2 2 2 DDR_A_D19 DQ18 DQ22 DDR_A_D22
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_A_D29 61 62 DDR_A_D28
DDR_A_D24 DQ24 DQ28 DDR_A_D25
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D31
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 DQ27 DQ31 76
77 VSS VSS 78
C DDR_CKE0_DIMMA DDR_CKE1_DIMMA C
<7> DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA <7>
81 VDD VDD 82
83 NC NC/A15 84
DDR_A_BS#2 85 86 DDR_A_MA14
<8> DDR_A_BS2 BA2 NC/A14
Layout Note: DDR_A_MA12
87 VDD VDD 88
DDR_A_MA11
89 A12 A11 90
Place one cap close to every 2 pullup DDR_A_MA9 91 92 DDR_A_MA7
DDR_A_MA8 A9 A7 DDR_A_MA6
resistors terminated to +0.9VS 93 A8 A6 94
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
A10/AP BA1 DDR_A_BS1 <8>
DDR_A_BS#0 107 108 DDR_A_RAS#
<8> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <8>
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
+0.9V <8> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
<8> DDR_A_CAS# CAS# ODT0 M_ODT0 <7>
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
<7> DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

<7> M_ODT1 M_ODT1 119 120

NC/ODT1 NC
121 VSS VSS 122
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_A_D37 123 124 DDR_A_D39
DDR_A_D36 DQ32 DQ36 DDR_A_D38
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
C229

C239

C250

C257

C272

C279

C281

C274

C268

C252

C241

C234

C227

133 134 DDR_A_D34

DDR_A_D35 VSS DQ38 DDR_A_D33
135 DQ34 DQ39 136
DDR_A_D32 137 138
DQ35 VSS DDR_A_D45
139 VSS DQ44 140
DDR_A_D40 141 142 DDR_A_D43
B DDR_A_D44 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_A_D41 151 152 DDR_A_D47
DDR_A_D46 DQ42 DQ46 DDR_A_D42
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D49 157 158 DDR_A_D52
DDR_A_D48 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR1
+0.9V NC,TEST CK1 M_CLK_DDR1 <7>
Layout Note: 165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 <7>
DDR_A_DQS#6 167 168
RP27 RP22 56_0404_4P2R_5%
Place these resistor DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
DDR_A_MA5 1 4 4 1 DDR_A_BS#2 closely JP34,all 171 172
DDR_A_MA8 VSS VSS
2 3 3 2 DDR_CKE0_DIMMA trace length Max=1.5" DDR_A_D54 173 DQ50 DQ54 174 DDR_A_D51
DDR_A_D50 175 176 DDR_A_D55
RP29 56_0404_4P2R_5% RP26 56_0404_4P2R_5% DQ51 DQ55
177 VSS VSS 178
DDR_A_MA1 1 4 4 1 DDR_A_MA7 DDR_A_D61 179 180 DDR_A_D57
DDR_A_MA3 DQ56 DQ60
2 3 3 2 DDR_A_MA6 DDR_A_D60 181 DQ57 DQ61 182 DDR_A_D56
183 VSS VSS 184
RP32 56_0404_4P2R_5% RP25 56_0404_4P2R_5% DDR_A_DM7 185 186 DDR_A_DQS#7
DDR_A_RAS# DM7 DQS7#
1 4 4 1 DDR_A_MA9 187 VSS DQS7 188 DDR_A_DQS7
DDR_CS0_DIMMA# 2 3 3 2 DDR_A_MA12 DDR_A_D59 189 190
DDR_A_D58 DQ58 VSS DDR_A_D62
191 DQ59 DQ62 192
RP31 56_0404_4P2R_5% RP28 56_0404_4P2R_5% 193 194 DDR_A_D63
DDR_A_BS#0 VSS DQ63
1 4 4 1 DDR_A_MA4 <14,15,26> ICH_SMBDATA
ICH_SMBDATA 195 SDA VSS 196
DDR_A_MA10 2 3 3 2 DDR_A_MA2 ICH_SMBCLK 197 198
<14,15,26> ICH_SMBCLK SCL SAO
+3VM 199 VDDSPD SA1 200
RP33 56_0404_4P2R_5% RP30 56_0404_4P2R_5% 203 204
GND GND

1
10K_0402_5%

10K_0402_5%
DDR_A_CAS# 1 DDR_A_MA0
2.2U_0603_6.3V4Z

1 4 4 1 1
0.1U_0402_16V4Z

DDR_A_WE# 2 3 3 2 DDR_A_BS#1 C308 conn@ FOX_ASOA426-M4R-TR

R455

R453
A C311 A
RP35 56_0404_4P2R_5% RP34 56_0404_4P2R_5%
DDR_CS1_DIMMA# 2 2 2
SO-DIMM A
3 4 1 M_ODT0
REVERSE

2
M_ODT1 1 4 3 2 DDR_A_MA13

56_0404_4P2R_5% RP24 56_0404_4P2R_5%

4 1 DDR_CKE1_DIMMA Top side
DDR_A_MA11 1 2 3 2 DDR_A_MA14

R1903 56_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 13 of 57
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V
<8> DDR_B_DQS#[0..7]

<8> DDR_B_D[0..63]
V_DDR_MCH_REF
V_DDR_MCH_REF <7,13,48>
<8> DDR_B_DM[0..7] JP10

2.2U_0805_16V4Z

0.1U_0402_16V4Z
<8> DDR_B_DQS[0..7] 1 VREF VSS 2
3 4 DDR_B_D5 1 1
DDR_B_D0 VSS DQ4 DDR_B_D4
<7,8> DDR_B_MA[0..14] 5 DQ0 DQ5 6

C89

C90
DDR_B_D1 7 8
DQ1 VSS DDR_B_DM0
9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16
D DDR_B_D2 D
17 DQ2 VSS 18
Layout Note: DDR_B_D3 19 20 DDR_B_D12
DQ3 DQ12 DDR_B_D13
21 VSS DQ13 22
Place near JP10 DDR_B_D8 23 24
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 DQ9 DM1 26
27 VSS VSS 28
DDR_B_DQS#1 29 30 M_CLK_DDR3
DQS1# CK0 M_CLK_DDR3 <7>
DDR_B_DQS1 31 32 M_CLK_DDR#3
DQS1 CK0# M_CLK_DDR#3 <7>
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS

41 VSS VSS 42
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_B_D17 43 44 DDR_B_D21
DDR_B_D20 DQ16 DQ20 DDR_B_D16
1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C236

C265

C247

C159

C164

C166

C219

C188

C161
47 VSS VSS 48
DDR_B_DQS#2 49 50
DQS2# NC PM_EXTTS#1 <7>
DDR_B_DQS2 51 52 DDR_B_DM2
2 2 2 2 2 2 2 2 2 DQS2 DM2
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_B_D28 61 62 DDR_B_D26
DDR_B_D25 DQ24 DQ28 DDR_B_D24
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_B_D30 73 74 DDR_B_D29
DDR_B_D31 DQ26 DQ30 DDR_B_D27
75 DQ27 DQ31 76
C C
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
<7> DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB <7>
81 VDD VDD 82
Layout Note: DDR_B_BS#2
83 NC NC/A15 84
DDR_B_MA14
<8> DDR_B_BS2 85 BA2 NC/A14 86
Place one cap close to every 2 pullup 87 88
DDR_B_MA12 VDD VDD DDR_B_MA11
resistors terminated to +0.9VS 89 A12 A11 90
DDR_B_MA9 91 92 DDR_B_MA7
DDR_B_MA8 A9 A7 DDR_B_MA6
93 A8 A6 94
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS#1
+0.9V A10/AP BA1 DDR_B_BS1 <8>
DDR_B_BS#0 107 108 DDR_B_RAS#
<8> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <8>
DDR_B_WE# 109 110 DDR_CS2_DIMMB#
<8> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <7>
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
<8> DDR_B_CAS# CAS# ODT0 M_ODT2 <7>
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_CS3_DIMMB# 115 116 DDR_B_MA13

<7> DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
1 1 1 1 1 1 1 1 1 1 1 1 1 M_ODT3 119 120
<7> M_ODT3 NC/ODT1 NC
121 VSS VSS 122
DDR_B_D32 123 124 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 DQ33 DQ37 126
2 2 2 2 2 2 2 2 2 2 2 2 2
127 VSS VSS 128
C176

C179

C186

C197

C213

C220

C183

C210

C199

C173

C218

C163

C177

DDR_B_DQS#4 129 130 DDR_B_DM4

DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D39
DDR_B_D34 VSS DQ38 DDR_B_D38
135 DQ34 DQ39 136
DDR_B_D35 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
B DDR_B_D40 DDR_B_D45 B
141 DQ40 DQ45 142
DDR_B_D41 143 144
DQ41 VSS DDR_B_DQS#5
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
Layout Note: 159 DQ49 DQ53 160
Place these resistor 161 VSS VSS 162
+0.9V 163 164 M_CLK_DDR2
closely JP10,all NC,TEST CK1 M_CLK_DDR2 <7>
165 166 M_CLK_DDR#2
DDR_B_DQS#6 VSS CK1# M_CLK_DDR#2 <7>
RP14 RP10 56_0404_4P2R_5% trace length Max=1.5" 167 DQS6# VSS 168
DDR_B_MA1 1 4 4 1 DDR_B_MA9 DDR_B_DQS6 169 170 DDR_B_DM6
DDR_B_MA3 DDR_B_MA12 DQS6 DM6
2 3 3 2 171 VSS VSS 172
DDR_B_D51 173 174 DDR_B_D54
RP17 56_0404_4P2R_5% RP11 56_0404_4P2R_5% DDR_B_D50 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
DDR_B_BS#0 1 4 4 1 DDR_B_MA14 177 178
DDR_B_MA10 DDR_B_MA11 DDR_B_D56 VSS VSS DDR_B_D60
2 3 3 2 179 DQ56 DQ60 180
DDR_B_D61 181 182 DDR_B_D57
RP16 56_0404_4P2R_5% RP12 56_0404_4P2R_5% DQ57 DQ61
183 VSS VSS 184
DDR_B_MA0 1 4 4 1 DDR_B_MA5 DDR_B_DM7 185 186 DDR_B_DQS#7
DDR_B_BS#1 DDR_B_MA8 DM7 DQS7# DDR_B_DQS7
2 3 3 2 187 VSS DQS7 188
DDR_B_D59 189 190
RP18 56_0404_4P2R_5% RP13 56_0404_4P2R_5% DDR_B_D58 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
DDR_B_RAS# 1 4 4 1 DDR_B_MA7 193 194 DDR_B_D63
DDR_CS2_DIMMB# 2 DDR_B_MA6 ICH_SMBDATA VSS DQ63
3 3 2 <13,15,26> ICH_SMBDATA 195 SDA VSS 196
ICH_SMBCLK 197 198 R257
<13,15,26> ICH_SMBCLK SCL SAO
RP19 56_0404_4P2R_5% RP15 56_0404_4P2R_5% 199 200 1 2 +3VM
+3VM VDDSPD SA1
DDR_B_CAS# 1 4 4 1 DDR_B_MA4 203 204
GND GND

1
10K_0402_5%
0.1U_0402_16V4Z

DDR_B_WE# DDR_B_MA2 10K_0402_5%

2.2U_0603_6.3V4Z

2 3 3 2 1 1

R254
A RP23 C301 FOX_ASOA426-M4R-TR A
56_0404_4P2R_5% RP21 56_0404_4P2R_5% C312 conn@
DDR_CS3_DIMMB# 2
M_ODT3
3 4 1 M_ODT2
DDR_B_MA13 2 2
SO-DIMM B
1 4 3 2
STANDARD

2
56_0404_4P2R_5% RP9
4 1 DDR_B_BS#2 Bottom side
DDR_CKE3_DIMMB 1 2 3 2 DDR_CKE2_DIMMB
R1743
56_0402_5% 56_0404_4P2R_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 14 of 57
5 4 3 2 1
 5 4 3 2 1

+3VM_CK505
FSLC FSLB FSLA CPU SRC PCI C353 2 1 CLK_48M_ICH
+3VM
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz 1
R1066
2
0_1206_5% 1 C357
5P_0402_50V8C
CLK_14M_ICH
1 1 1 1 1 1 2 1
C1165 C1166 C1167 C1168 C1169 C1170 C1171 4.7P_0402_50V8C
0 1 0 200 100 33.3 C372 2 1 CLK_PCI_ICH
10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7P_0402_50V8C
2 2 2 2 2 2 2 C373 CLK_14M_KBC
2 1
0 1 1 166 100 33.3 4.7P_0402_50V8C
C374 2 1 CLK_14M_SIO
4.7P_0402_50V8C
Place close to U7 C375 2 1 CLK_PCI_EC
FSB Frequency Selet: 4.7P_0402_50V8C
+1.25VM_CK505 C376 CLK_PCI_TCG
2 1
D R1068 0_1206_5% 4.7P_0402_50V8C D
CPU Driven Stuff R1107 R1135 R1083
+1.25VM 1 2 0.1U_0402_16V4Z 10U_0603_6.3V6M 0.1U_0402_16V4Z C378 2 1 CLK_PCI_PCM
1 1 1 1 1 1 4.7P_0402_50V8C
R1074 R1086 R1098 R1113 R1128 R1139 C1353 C1355 C379 CLK_PCI_SIO
*(Default) No Stuff
C1173 C1174 C1354
2 1
4.7P_0402_50V8C
C1172 C380 2 1 CLK_DEBUG_PORT
2 2 2 2 2 2 5P_0402_50V8C
Stuff R1086 R1139 R1135 R1074 R1139 R1135
10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z
667MHz
No Stuff R1083 R1107 R1128
R1113 R1098
Stuff
R1135 R1139
+3VM_CK505 U7
800MHz
No Stuff R1083 R1086 R1098 R1128 2 VDD_PCI NC 48
9 VDD48
R1074 R1107 R1113 16 VDDPLL3
61 VDDREF
SCLK 64
39 63 ICH_SMBCLK <13,14,26>
VDDSRC SDATA ICH_SMBDATA <13,14,26>
R1074 55 VDDCPU
@ 38
PCI_STOP# H_STP_PCI# <26>
1 2 +VCCP CPU_STOP# 37
12 H_STP_CPU# <26>
+1.25VM_CK505 VDD96_IO
R1078 56_0402_5% 20
2.2K_0402_5% VDDPLL3_IO
26 VDDSRC_IO
FSA 2 1 1 2 54
MCH_CLKSEL0 <7> CPU0 CLK_CPU_BCLK <4>
36 VDDSRC_IO CPU0# 53 CLK_CPU_BCLK# <4>
1 2 R1079 49
C <5> CPU_BSEL0 VDDCPU_IO C
R1083 1K_0402_5%
0_0402_5% 1111 Add CLRP4,CLRP5 for 667/800 FSB select
1

51 CLK_MCH_BCLK <7>
R1086 SHORT CLRP5, NO SHORT CLRP4 -- FSB 800 CPU1_F
50
CPU1#_F CLK_MCH_BCLK# <7>
SHORT CLRP4, NO SHORT CLRP5 -- FSB 667
@ 1K_0402_5% @ R1033 1 2 0_0402_5%
CLK_CPU_XDP <4>
47 R_CPU_XDP R1447 1 2 0_0402_5%
CLK_PCIE_Rob <31>
2

SRC8/ITP R_CPU_XDP# 0_0402_5%

SRC8#/ITP# 46 1 2 CLK_PCIE_Rob# <31>
R1448 1 2 0_0402_5%
CLK_CPU_XDP# <4>
475_0402_1%1 2 R1692 1 @R1143
@ R1143
+VCCP <26> CLKSATAREQ# PCI0/CR#_A
1 2 PCI_CLK1 3 35
<7> CLKREQ#_B PCI1/CR#_B SRC10# CLK_PCIE_DOCK# <39>
R1693 475_0402_1% 34
SRC10 CLK_PCIE_DOCK <39>
2

22_0402_5% 2 1 R1097 PCI2_TME 4

R1098 <31,36> CLK_DEBUG_PORT 12_0402_5% 2 PCI2/TME
<35> CLK_PCI_SIO 1 R1114 1 2 +3VS
12_0402_5% 1 2 R1140 PCI_CLK3 5 R1695 R149 10K_0402_5%
<36> CLK_PCI_TCG PCI3
@ 1K_0402_5% 12_0402_5% 1 2 R1110 33 CLKREQ#_H 2 1 475_0402_1%
<37> CLK_PCI_EC SRC11/CR#_H CPPE# <39>
12_0402_5% 1 2 R1141 27_SEL 6 32 R_CLKREQ#_G 2 1 475_0402_1%
CLKREQ#_G <31>
1

FSB <31> CLK_PCI_PCM PCI4/27_Select SRC11#/CR#_G R1694 R150 10K_0402_5%

1 2 MCH_CLKSEL1 <7>
22_0402_5% 1 2 R1117 ITP_EN 7 1 2 +3VS
<24> CLK_PCI_ICH PCIF5/ITP_EN
1 2 R1105
<5> CPU_BSEL1
R1107 1K_0402_5% 30
SRC9 CLK_PCIE_MCARD <31>
0_0402_5% 31
SRC9# CLK_PCIE_MCARD# <31>
1

CLK_XTAL_IN 60
@R1113
@ R1113 X1
1 2 +3VS
CLK_XTAL_OUT 59 R1900 475_0402_1% R1899 10K_0402_5%
0_0402_5% X2 R_CLKREQ#_F CLKREQ#_F
SRC7/CR#_F 44 2 1 CLKREQ#_F
43 R_CLKREQ#_E 2 1 CLKREQ#_E
CLKREQ#_E <19,31>
2

SRC7#/CR#_E @ R1901 475_0402_1% @ R1902 10K_0402_5%

1 2 +3VS

B +VCCP R1077 33_0402_5% 41 B

SRC6 CLK_PCIE_VGA <18>
1 2 FSA 10 40
<26> CLK_48M_ICH USB_48MHZ/FSLA SRC6# CLK_PCIE_VGA# <18>
2

R1128 FSB 57 FSLB/TEST MODE

SRC4 27 CLK_MCH_3GPLL <7>
R1130 @ 1K_0402_5% 28
SRC4# CLK_MCH_3GPLL# <7>
10K_0402_5% 33_0402_1% 1 2 R1087 FSC 62
1

FSC <26> CLK_14M_ICH 33_0402_1% 1 R1088 REF0/FSLC/TEST_SEL

2 1 1 2 MCH_CLKSEL2 <7> <35> CLK_14M_SIO 2
33_0402_1% 1 2 R1089
1 2 R1131 <37> CLK_14M_KBC 24
<5> CPU_BSEL2 SRC3/CR#_C CLK_PCIE_ICH <26>
R1135 1K_0402_5% +1.25VM_CK505 45 25
VDDSRC_IO SRC3#/CR#_D CLK_PCIE_ICH# <26>
0_0402_5%
1

@R1139
@ R1139 For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
SRC2/SATA 21 CLK_PCIE_SATA <25>
0_0402_5% For 27_SEL, 0 = Enable DOT96 & SRC1, 42 22
GNDSRC SRC2#/SATA# CLK_PCIE_SATA# <25>
2

1= Enable SRC0 & 27MHz 8 GNDPCI

For PCI2_TME, 0 = Overclocking of CPU and SRC Allowed 11 17 R_27MHz R1686 1 2 0_0402_5%
GND48 SRC1/SE1/27MHz_NonSS 27M_CLK <19>
18 R_27MSSC R1687 1 2 0_0402_5%
SRC1#/SE2/27MHz_SS 27M_SSC <19>
1 = Overclocking of CPU and SRC NOT allowed 15 GND
19 GND 11/20 For EMI request to install R1687
CLK_XTAL_OUT 13
+3VS +3VS +3VS SRC0/DOT96
52 GNDCPU SRC0/DOT96# 14
CLK_XTAL_IN
23 GNDSRC
2

14.31818MHZ_16P R1245 R1690 R1108 29

@ GNDSRC
10K_0402_5% 10K_0402_5% 10K_0402_5% CK_PWRGD/PD# 56
A
58 CK_PWRGD <26> A
Y6 GNDREF
1

2 1 ICS9LPRS355AKLFT_TSSOP64
ITP_EN 27_SEL PCI2_TME
* Internal Pull-Up Resistor
2 2 ** Internal Pull-Down Resistor
2

C509 C505 R1247 @ R1691 R1246

18P_0402_50V8J
1 1
18P_0402_50V8J 10K_0402_5% 10K_0402_5% 10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
@ Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title
Clock generator
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Routing the trace at least 10mil AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 15 of 57
5 4 3 2 1
 A B C D E

+5VS +RCRT_VCC +CRTVDD

CRT Connector F1 D18

W=40mils
<39> L_BLUE 1 2 2 1
BLUE_R
<39> L_GREEN 1.1A_6VDC_FUSE CH491D_SC59 GREEN_R
1 RED_R
C315

DAN217_SC59

DAN217_SC59

@ DAN217_SC59
<39> L_RED

D19

D20
2007,0125 change 0.1U_0402_16V4Z

1
2

150_0402_1%

D4
Place close to JP2

150_0402_1%
JP2
@ 6
R171 R174 R542 BK1608LL560-T_0603 11
1 RED_R @ @ 1
1 2 1

2
0315 add +CRTVDD
7

3
39P_0402_50V8C
@ R543 BK1608LL560-T_0603 12
1 2 GREEN_R 2

39P_0402_50V8C
C313
8
150_0402_1% R544 BK1608LL560-T_0603 13

C314
@R173
@ R173 1 2 BLUE_R 3
9

39P_0402_50V8C

18P_0402_50V8J

18P_0402_50V8J

18P_0402_50V8J
+5VS +5VS 14 16
2007,0125 change 1 1 1 @ 1 1 1 4 17

C310

C317

C316

C318
10
1 15
0.1U_0402_16V4Z @ 5 +3VS
C359 2 2 2 2 2 2
SUYIN_070912FR015S207CR
5
1

2 U33 @ conn@
SN74AHCT1G125GW_SOT353-5 R545 0315 add
P
OE#

2 4 HSYNC_G_A 1 2 D_HSYNC
<19> M_HSYNC A Y

2
R1921 2.2K_0402_5%

2.2K_0402_5%
0_0603_5%
G

5
1

D_HSYNC <39>

R1922
R546
P
OE#
3

2 4VSYNC_G_A 1 2 D_VSYNC +CRTVDD +CRTVDD

<19> M_VSYNC A Y 0_0603_5%

1
G

18P_0402_50V8J

18P_0402_50V8J
U54
D_VSYNC <39>

1
SN74AHCT1G125GW_SOT353-5 @ 1 1
3

C323

R162 R183

C322 2.2K_0402_5% 2.2K_0402_5%

Place close to docking connector
2 2 @

2
Q46

G
D_DDCDATA 1 3 DDC1_DATA <19>
2 <39> D_DDCDATA 2

S
2
RHU002N06_SOT323

G
Place close to docking connector
D_DDCCLK 1 3
<39> D_DDCCLK DDC1_CLK <19>

S
layout note: D_HSYNC & D_VSYNC should be routed to docking connector then to VGA connector Q52
RHU002N06_SOT323

Place close to JP1

TV-Out Connector DAN217_SC59 DAN217_SC59 DAN217_SC59 +3VS
@D3
@ D3 @ D5 @D1
@ D1
1

0_0603_5%
<19,39> LUMA
2

R547 1 2
<19,39> CRMA 0_0603_5%
R548 1 2
0_0603_5% JP1
<19,39> COMP
R549 1 2 1
2
5.6P_0402_50V8D

5.6P_0402_50V8D

3
1

3 @ R187
@R187 TV_LUMA 3
@ R184 4
1 1 1 5
150_0402_1%

TV_CRMA
6
150_0402_1%

@ @ @
TV_COMP 7
2

2 2 2
C333 C355 conn@
@ R185
@R185
0315 add 150_0402_1% 5.6P_0402_50V8D SUYIN_33007SR-07T1-C
C354

Close to JP1

layout note: TV-out signals should be routed to JP30 then to JP1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TVout Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 16 of 57
A B C D E
 5 4 3 2 1

B+_LCD
0802 (R1A) change for preventing 1206 Cap crack
LCD POWER CIRCUIT LCDVDD +3VALW
LVDS CONN C586 4.7U_0805_25V6K LCDVDD
Q8
AO3413_SOT23
1 2

S
1 3

1
JP35 1 2
C587 68P_0402_50V8J R19
R12
1 2

G
2
41 40 C1629 4.7U_0805_25V6K 100_0402_1% 1 2
41 40
42 39

1 2
D 42 39 1M_0402_5% D
43 43 38 38 2 1 B+ D
L62 KC FBM-L11-201209-221LMA30T_1210 R474 C28
44 44 37 37
45 36 Q5 2 1 2 E_STAR 1 2
45 36 G
46 46 35 35 +3VS
34 RHU002N06_SOT323 S 47K_0402_5% 1 1 0.1U_0402_16V7K 1

3
34 C29 C31 C20
33 33
32 32 LCDVDD E_STAR <41>

1
31 @ 4.7U_0805_10V4Z
31 Q6 2 2 2
30 30
29 +5VS_INV DTC124EK_SC59
29
28 28
27 BKLT_PWM ALS_EN <26> 2 0.1U_0402_16V4Z 4.7U_0805_10V4Z
27 <19> VGA_ENAVDD
26 26
25 DDC2_CLK <19>
25

2
24 DDC2_DATA <19>
24 R502
23 TXCLK_U+ <19>

3
23 100K_0402_1%
22 22 TXCLK_U- <19>
21 21
20 TXOUT_U2+ <19>

1
20
19 19 TXOUT_U2- <19>
18 18
17 17 TXOUT_U1+ <19>
16 16 TXOUT_U1- <19>
15 15
14 14 TXOUT_U0+ <19>
13 Q53
13 TXOUT_U0- <19>
12 DTA114YKA_SC59
12
11 11 TXOUT_L0- <19>
10 +3V_U43
10 TXOUT_L0+ <19>
9 9 +5VS 3 1 +5VS_INV
8 0_0402_5%

47K
8 TXOUT_L1- <19>
R1728 1

10K
7 7 TXOUT_L1+ <19> +3VALW 2
C C
6 6
5 @ 0_0402_5%
5 TXOUT_L2- <19>
4 +3VS R1729 1 2
TXOUT_L2+ <19>

2
4 U43A
3 3
SN74LVC08APW_TSSOP14

14
2 2 TXCLK_L- <19>
1 1 TXCLK_L+ <19>

1
LID_SW# D
1

P
<26,38> LID_SW# A
3 2 Q36
O G BSS138_SOT23
<19> OPT_BL_ENA 2 B

2
ACES_88316-4000 S

3
2
R360

7
conn@ 100K_0402_5%

1
R501

1
100K_0402_1%

B R102 0_0402_5% BKLT_PWM B

<19> BLON_PWM 1 2

Support 3V inverter

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 17 of 57
5 4 3 2 1
 5 4 3 2 1

D D

U80A
PART 1 OF 6
PEG_M_TXP0 AC30 AA28 PEG_M_RXP0 C1380 0.1U_0402_16V4Z PEG_RXP0
PEG_M_TXN0 PCIE_RX0P PCIE_TX0P PEG_M_RXN0 C1381 0.1U_0402_16V4Z PEG_RXN0
AC31 PCIE_RX0N PCIE_TX0N AA27

PEG_M_TXP1 AC29 P AA25 PEG_M_RXP1 C1382 0.1U_0402_16V4Z PEG_RXP1

PEG_M_TXN1 PCIE_RX1P PCIE_TX1P PEG_M_RXN1 C1383 0.1U_0402_16V4Z PEG_RXN1
AB29 AA24
PCIE_RX1N C PCIE_TX1N
I
PEG_M_TXP2 AB31 Y28 PEG_M_RXP2 C1384 0.1U_0402_16V4Z PEG_RXP2
PEG_M_TXN2 AB30
PCIE_RX2P - PCIE_TX2P
Y27 PEG_M_RXN2 C1385 0.1U_0402_16V4Z PEG_RXN2
PCIE_RX2N E PCIE_TX2N

PEG_M_TXP3
X PEG_M_RXP3 C1386 0.1U_0402_16V4Z PEG_RXP3
AA31 PCIE_RX3P PCIE_TX3P Y25
PEG_M_TXN3 AA30 PCIE_RX3N
P PCIE_TX3N Y24 PEG_M_RXN3 C1387 0.1U_0402_16V4Z PEG_RXN3
R
E <15> CLK_PCIE_VGA
PEG_M_TXP4 W30 V28 PEG_M_RXP4 C1388 0.1U_0402_16V4Z PEG_RXP4
PCIE_RX4P PCIE_TX4P <15> CLK_PCIE_VGA#
PEG_M_TXN4 W31 S V27 PEG_M_RXN4 C1389 0.1U_0402_16V4Z PEG_RXN4
PCIE_RX4N PCIE_TX4N
S PEG_RXP[0..15]
<9> PEG_RXP[0..15]
PEG_M_TXP5 W29 V25 PEG_M_RXP5 C1390 0.1U_0402_16V4Z PEG_RXP5
PEG_M_TXN5 PCIE_RX5P PCIE_TX5P PEG_M_RXN5 C1391 0.1U_0402_16V4Z PEG_RXN5 PEG_RXN[0..15]
V29 PCIE_RX5N PCIE_TX5N V24 <9> PEG_RXN[0..15]
I
N PEG_M_TXP[0..15]
<9> PEG_M_TXP[0..15]
PEG_M_TXP6 V31 T28 PEG_M_RXP6 C1392 0.1U_0402_16V4Z PEG_RXP6
PEG_M_TXN6 V30
PCIE_RX6P T PCIE_TX6P
T27 PEG_M_RXN6 C1393 0.1U_0402_16V4Z PEG_RXN6 PEG_M_TXN[0..15]
PCIE_RX6N PCIE_TX6N <9> PEG_M_TXN[0..15]
C
E C
PEG_M_TXP7 U31
R T25 PEG_M_RXP7 C1394 0.1U_0402_16V4Z PEG_RXP7
PCIE_RX7P PCIE_TX7P
PEG_M_TXN7 U30 PCIE_RX7N
F PCIE_TX7N T24 PEG_M_RXN7 C1395 0.1U_0402_16V4Z PEG_RXN7
A
PEG_M_TXP8 P30 PCIE_RX8P
C PCIE_TX8P P28 PEG_M_RXP8 C1396 0.1U_0402_16V4Z PEG_RXP8
PEG_M_TXN8 P31 P27 PEG_M_RXN8 C1397 0.1U_0402_16V4Z PEG_RXN8
PCIE_RX8N E PCIE_TX8N

PEG_M_TXP9 P29 P25 PEG_M_RXP9 C1398 0.1U_0402_16V4Z PEG_RXP9

PEG_M_TXN9 PCIE_RX9P PCIE_TX9P PEG_M_RXN9 C1399 0.1U_0402_16V4Z PEG_RXN9
N29 PCIE_RX9N PCIE_TX9N P24

PEG_M_TXP10 N31 M28 PEG_M_RXP10 C1400 0.1U_0402_16V4Z PEG_RXP10

PEG_M_TXN10 PCIE_RX10P PCIE_TX10P PEG_M_RXN10 C1401 0.1U_0402_16V4Z PEG_RXN10
N30 PCIE_RX10N PCIE_TX10N M27

PEG_M_TXP11 M31 M25 PEG_M_RXP11 C1402 0.1U_0402_16V4Z PEG_RXP11

PEG_M_TXN11 PCIE_RX11P PCIE_TX11P PEG_M_RXN11 C1403 0.1U_0402_16V4Z PEG_RXN11
M30 PCIE_RX11N PCIE_TX11N M24

PEG_M_TXP12 K30 L28 PEG_M_RXP12 C1404 0.1U_0402_16V4Z PEG_RXP12

PEG_M_TXN12 PCIE_RX12P PCIE_TX12P PEG_M_RXN12 C1405 0.1U_0402_16V4Z PEG_RXN12
K31 PCIE_RX12N PCIE_TX12N L27

PEG_M_TXP13 K29 L25 PEG_M_RXP13 C1406 0.1U_0402_16V4Z PEG_RXP13

PEG_M_TXN13 PCIE_RX13P PCIE_TX13P PEG_M_RXN13 C1407 0.1U_0402_16V4Z PEG_RXN13
J29 PCIE_RX13N PCIE_TX13N L24

PEG_M_TXP14 J31 J28 PEG_M_RXP14 C1408 0.1U_0402_16V4Z PEG_RXP14

PEG_M_TXN14 PCIE_RX14P PCIE_TX14P PEG_M_RXN14 C1409 0.1U_0402_16V4Z PEG_RXN14
J30 PCIE_RX14N PCIE_TX14N J27
B B
PEG_M_TXP15 H31 G28 PEG_M_RXP15 C1410 0.1U_0402_16V4Z PEG_RXP15
PEG_M_TXN15 PCIE_RX15P PCIE_TX15P PEG_M_RXN15 C1411 0.1U_0402_16V4Z PEG_RXN15
H30 PCIE_RX15N PCIE_TX15N G27

Clock Calibration
CLK_PCIE_VGA AD29
CLK_PCIE_VGA# PCIE_REFCLKP R1904 1 2K_0402_1%
AD30 PCIE_REFCLKN PCIE_CALRN AF25 2 PCIE_1.2V
AC28 AE25 R1887 1 2 562_0402_1%
RSVD PCIE_CALRP
AC27 RSVD
AE23 R1737 1 2 M62: R1887-->562 ohm 1%
PCIE_CALI 1.47K_0402_1% M72: R1887-->1.27k ohm 1%
<24> VGA_RST# AG25 PERSTB

216PTAKA13FG M62-S_BGA632
M62: R1737-->1.47k ohm 1%
M72: R1887-->10k ohm 1%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M62-S PCIE interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 18 of 57
5 4 3 2 1
 5 4 3 2 1

20070719 change for DVI high resolution issue 10K_0402_5%

U80B U80F
1 2
PART 6 OF 6 R1905
PART 2 OF 6 1 2
AH7 AK9 100_0402_1% R1740 +LVDDR AF20 AA7
VID_0 DVI_CLK- <39> +LVDDR BLON_PWM <17>
AG9 Integrated TXCM AL9 AG20
LVDDR_1 Control VARY_BL
Close to U80 AF9
VID_1 TMDS TXCP
1 2
DVI_CLK+ <39>
1
LVDDR_2
AC6
VID_2 DIGON VGA_ENAVDD <17>
AJ7 AJ9 100_0402_1% R1742 C1412
VID_3 TX0M DVI_TX0- <39>
BLM18PG121SN1D_0603 1U_0402_6.3V4Z AG7 AJ10 1U_0402_6.3V4Z AJ18
VID_4 TX0P DVI_TX0+ <39> LVDDC_1
2 1 MPVDD AF7 1 2 AH20 AD21
VID_5 2 LVDDC_2 TXCLK_UP TXCLK_U+ <17>
L93 1 1 1 AH6 AL10 100_0402_1% R1745 AE21
VGA_VCORE VID_6 TX1M DVI_TX1- <39> TXCLK_UN TXCLK_U- <17>
AG6 VID_7 V TX1P AK10 DVI_TX1+ <39> TXOUT_U0P AJ24 TXOUT_U0+ <17>
C10 1 2 AJ23
I TXOUT_U0N TXOUT_U0- <17>
C1437 C1450 AL6 AL11 100_0402_1% R1746 AF23 AK24
2 2 2 VHAD_0 TX2M DVI_TX2- <39> LVSSR_1 TXOUT_U1P TXOUT_U1+ <17>
D
AK6 VHAD_1 D TX2P AK11 DVI_TX2+ <39> AF21 LVSSR_2 TXOUT_U1N AL24 TXOUT_U1- <17> D
10U_0603_4V6M 0.1U_0402_16V4Z AL18 AG21
E LVSSR_3 TXOUT_U2P TXOUT_U2+ <17>
AK5 AL7 1U_0402_6.3V4Z +TPVDD AJ22 AH21

VIP / I2C
VPHCTL TPVDD LVSSR_4 TXOUT_U2N TXOUT_U2- <17>
O AK7 AJ25

LVDS channel
TPVSS 1 1 LVSSR_5 TXOUT_U3P AG23
AJ4 VPCLK0 AK18 LVSSR_6 TXOUT_U3N AH23
AJ5 AJ12 +TXVDDR C1415 Closed to U80 AK23
VIPCLK TXVDDR_1 LVSSR_7
& TXVDDR_2 AJ13 +TXVDDR
2 2
AK25 LVSSR_8 TXCLK_LP AL19 TXCLK_L+ <17>
AL5 AK13 C1414 AJ21 AK19
PSYNC TXVDDR_3 LVSSR_9 TXCLK_LN TXCLK_L- <17>
AL13 0.1U_0402_16V4Z AL23 AJ20
TXVDDR_4 LVSSR_10 TXOUT_L0P TXOUT_L0+ <17>
AD9 DVALID
M 1 AL25 LVSSR_11 TXOUT_L0N AJ19 TXOUT_L0- <17>
U TXVSSR_1 AJ8 TXOUT_L1P AK20 TXOUT_L1+ <17>
AA4 AH9 C1552 AL20
<17> DDC2_DATA SDA TXVSSR_2 TXOUT_L1N TXOUT_L1- <17>
<17> DDC2_CLK AA5 SCL
L TXVSSR_3 AH11 1U_0402_6.3V4Z
TXOUT_L2P AK21 TXOUT_L2+ <17>
R1752 2.2K_0402_5% 2
T TXVSSR_4 AJ11 TXOUT_L2N AL21 TXOUT_L2- <17>
+3VS 1 2 AK4 AK12 +LPVDD AG18 AK22
DVPCNTL_MVP_0 I TXVSSR_5 +LPVDD LPVDD TXOUT_L3P
Close to U80 1 2
AL3 DVPCNTL_MVP_1 TXVSSR_6 AL12 AH18 LPVSS TXOUT_L3N AL22

R1755 2.2K_0402_5%
M C1416
1 1
C1417
BLM18PG121SN1D_0603
V2
V1
DVPCNTL_0 E AE11
0906 change
DVPCNTL_1 NC_5 216PTAKA13FG M62-S_BGA632
L87 W3 D AF11 1U_0402_6.3V4Z
0.1U_0402_16V4Z +DPLL_PVDD DVPCNTL_2 NC_6 2 2
+2.5VS 2 1
170mA, 20mils 1 1 1 W1 I AK8 100N_0402_50V7M
C1427 DVPCLK NC_7
A NC_8 AL8
C1585 1U_0402_6.3V4Z Y1
C1584 DVPDATA_0
Y2 DVPDATA_1 NC_9 AG11
2 2 2
Y3 DVPDATA_2
10U_0603_6.3V6M AA2 DVPDATA_3
AA3 DVPDATA_4
AB1 DVPDATA_5 R AL28 VGA_RED
AB2 DVPDATA_6 RB AK28

VIP Host/External TMDS

AB3 DVPDATA_7
BLM18PG121SN1D_0603 AC1 DVPDATA_8 G AL27 VGA_GRN
10U_0603_6.3V6M AC3 AK27
C PCIE_PVDD DVPDATA_9 GB C
PCIE_1.2V 2 1 AD1 DVPDATA_10
R1797 1 1 1 AD2 DAC / CRT AL26 VGA_BLU
DVPDATA_11 B
AD3 DVPDATA_12 BB AK26
C1428 C9 AF3
1U_0402_6.3V4Z C6 DVPDATA_13
2 2 2
AG3
AH3
DVPDATA_14 HSYNC AK29
AK30
M_HSYNC <16> Note: CRT / TV-out should route to JP30 first then to the
T88 PAD DVPDATA_15 VSYNC M_VSYNC <16>
0.1U_0402_16V4Z
T89 PAD AG1 DVPDATA_16 +AVDD JP1 & JP2 on system side.
T90 PAD AH2 DVPDATA_17 RSET AJ28 1 2 1
Place Closed to U80
AH1 R1775 470_0402_1% C1418

BLM18PG121SN1D_0603
R1891
<23>
T91
T92
VRAM_ID0
PAD
PAD AJ3
AJ1
DVPDATA_18
DVPDATA_19
DVPDATA_20
AVDD AL29
2
1U_0402_6.3V4Z
CRT Termination/EMI Filter L28 L31
<23> VRAM_ID1 AJ2 DVPDATA_21
PCIE_1.2V 2 1 DPLL_VDDC AK2 AH28 VGA_RED 1 2 C_RED_L 1 2
<23> VRAM_ID2 DVPDATA_22 AVSSQ RED <39>
1 1 AK3 HLC0603CSCC39NJT_0603 HLC0603CSCCR11JT_0603
<23> VRAM_ID3 DVPDATA_23
AJ27 VDDDI_25 L35 L34
C1435 C1436 VDD1DI VGA_GRN C_GRN_L
1 1 2 1 2 GREEN <39>
1U_0402_6.3V4Z AJ26 HLC0603CSCC39NJT_0603 HLC0603CSCCR11JT_0603
2 2 VSS1DI C1421 L27 L26
<23> GPIO0 Y4 GPIO_0

R1764
1U_0402_6.3V4Z V3 1U_0402_6.3V4Z VGA_BLU 1 2 C_BLU_L 1 2
<23> GPIO1 GPIO_1 2 BLUE <39>
V4 AL17 HLC0603CSCC39NJT_0603 HLC0603CSCCR11JT_0603
GPIO_2 R2
V5 GPIO_3 R2B AK17

1
75_0402_1%
GPIO4 U3 GPIO_4

75_0402_1%
<23> GPIO5 U2 GPIO_5 G2 AL15 1 1 1 1 1 1

75_0402_1%
T4 AK15 C237 C232 @ C195
<23> GPIO6 GPIO_6 G2B
T5 C193
<17> OPT_BL_ENA GPIO_7_BLON
T7 AL14 22P_0402_50V8J 22P_0402_50V8J @C245
@ C245

2
+3VS GPIO_8_ROMSO B2 2 2 2 2 2 2 10P_0402_50V8J
T113PAD T8 GPIO_9_ROMSI B2B AK14
T115PAD R1 GPIO_10_ROMSCK

R1765
R2 AJ17 VGA_CRMA R1763 22P_0402_50V8J 10P_0402_50V8J @ C244
<23> GPIO11 GPIO_11 C
1

R1760 R3 General
T114PAD GPIO_12 Purpose
499_0402_1% P1 AJ15 VGA_LUMA 10P_0402_50V8J
<23> GPIO13 GPIO_13 I/O DAC2 (TV/CRT2) Y
P3 GPIO_14_HPD2
B VGA_COMP B
<51> POW_SW N1 GPIO_15_PWRCNTL_0 COMP AJ14
N2 Note: TV-out should route to JP30 first then to the JP1 & JP2
2

VGA_VREF <15> 27M_SSC GPIO_16_SSIN

P4 GPIO_17_THERMAL_INT V2SYNC AE16
@ R1787 10K_0402_5% P7 GPIO_18_HPD3 H2SYNC AF16 on system side.
1

1 +3VS 2 1 P8 GPIO_19_CTF
P5 GPIO_20_PWRCNTL_1 A2VDD AH14 1 +A2VDD
R1769 C2 V7
499_0402_1%
2
0.1U_0402_16V4Z N3
Y5
GPIO_21_BB_EN
GPIO_22_ROMCSB
AH16
C1422
1U_0402_6.3V4Z TV-Out Termination/EMI Filter Place close to U80
2

<15,31> CLKREQ#_E GPIO_23_CLKREQB A2VDDQ 2

PAD M4 GPIO_24_TRST
T98 PAD M5 GPIO_25_TDI A2VSSQ AG16
1

M62S: R1769-->499 ohm 1% T97 M7 VGA_COMP L38 1 2 COMP <16,39>

T99 PAD GPIO_26_TCK
M72S: R1769-->249 ohm 1% R1791 M8 AF18 VDDDI_25 CHB1608U301_0603
T100PAD GPIO_27_TMS VDD2DI
1K_0402_5% L8 1
T101PAD GPIO_28_TDO
Place those components AE18 1U_0402_6.3V4Z VGA_LUMA L37 1 2 LUMA <16,39>
VSS2DI C1426 CHB1608U301_0603
T102PAD Y8
2

as close as U80 within 500 GENERICA

T103PAD Y7 GENERICB R2SET AG14 1 2
R1793 715_0402_1% 2 VGA_CRMA L17 1
mils. VGA_VREF
V8 GENERICC 2
CHB1608U301_0603
CRMA <16,39>
AC11 VREFG HPD1 AA8 DVI_DETECT <39>

5.6P_0402_50V8D

5.6P_0402_50V8D
1 1 1

5.6P_0402_50V8D

5.6P_0402_50V8D
DDC1DATA AJ29 DDC1_DATA <16> 1 1 1

1
75_0402_1%

75_0402_1%
+DPLL_PVDD AH12 AH29 C253
DPLL_PVDD Monitor DDC1CLK
DDC1_CLK <16>

75_0402_1%
AG12 R1796 2 1 +3VS C251
DPLL_PVSS Interface 2 2 2
DDC2DATA AC5 DVI_DAT <39> DVI
PCIE_PVDD 4.7K_0402_5% 2 2 2 C243
AH31 PCIE_PVDD DDC2CLK AC4 DVI_CLK <39>
AH30 R1799 2 1 +3VS C238

2
PCIE_PVSS 4.7K_0402_5% C8
DDC3DATA AF4 ICH_SM_DA <4,23,26,31> thermal

R1780
MPVDD A9 AH4 C7 5.6P_0402_50V8D 0314 change design
MPVDD DDC3CLK ICH_SM_CLK <4,23,26,31>

R1778
B9 5.6P_0402_50V8D
110_0402_1% MPVSS
TS_FDO AE14
1 2 XIN AJ31 PLL & R1779
<15> 27M_CLK R1449 XOUT XTALIN XTAL Thermal VGA_THERMDA
AJ30 XTALOUT DPLUS AE5 VGA_THERMDA <23>
1

A VGA_THERMDC A
R1449 Close to C1565 DMINUS AE4 VGA_THERMDC <23>
DPLL_VDDC AE12 DPLL_VDDC
TESTEN AH26 2 1
XIN XOUT R1450 AD11 Test R1800 1K_0402_5%
82_0402_5% NC_10
1 1 AD12
2

18P_0402_50V8J PLLTEST
18P_0402_50V8J C1566 @ 216PTAKA13FG M62-S_BGA632
C1565 @
2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
2006/09/25 2006/09/25 Title
Issued Date Deciphered Date M62-S CRT/LVDS/TV-OUT
M62S: R1450-->330 ohm 1% > ~ 1.1V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Close to U80 AJ31 and AJ30 pins DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 19 of 57
5 4 3 2 1
 5 4 3 2 1

U80C

Part 3 of 6

MDB[63..32] MAB[11..0] <22>

MDB0 E29 B14 MAB0
<22> MDB[63..32] DQ_0 MA_0
MDB1 E30 A14 MAB1
MDB[31..0] MDB2 DQ_1 MA_1 MAB2
<22> MDB[31..0] E31 DQ_2 MA_2 B13
MDB3 D31 E14 MAB3
MDB4 DQ_3 MA_3 MAB4
C29 DQ_4 MA_4 B17
MDB5 B29 A17 MAB5
MDB6 DQ_5 MA_5 MAB6
B30 C15

MEMORY INTERFACE
MDB7 DQ_6 MA_6 MAB7
A29 DQ_7 MA_7 G16
MDB8 E26 E16 MAB8
MDB9 DQ_8 MA_8 MAB9
D26 DQ_9 MA_9 C14
D MDB10 MAB10 D
E25 DQ_10 MA_10 A12
MDB11 D25 B12 MAB11
DQ_11 MA_11 BA[2..0] <22>
MDB12 G23 B15
MDB13 DQ_12 MA_A12 BA0
G21 DQ_13 MA_BA0 C12
MDB14 E21 D14 BA1
MDB15 DQ_14 MA_BA1 BA2
D21 DQ_15 MA_BA2 G14
MDB16 C28 DQ_16 DQMB[3..0] <22>
MDB17 B28 D30 DQMB0
MDB18 DQ_17 DQMB_0 DQMB1
B27 DQ_18 DQMB_1 G25
MDB19 A27 C26 DQMB2
MDB20 DQ_19 DQMB_2 DQMB3
C25 DQ_20 DQMB_3 C21 DQMB[7..4] <22>
MDB21 A25 C5 DQMB4
MDB22 DQ_21 DQMB_4 DQMB5
C24 D6

A
MDB23 DQ_22 DQMB_5 DQMB6
B24 DQ_23 DQMB_6 D2
MDB24 C23 K3 DQMB7
MDB25 DQ_24 DQMB_7
B23 DQ_25 RDQS[3..0] <22>
MDB26 A23 C30 RDQS0
MDB27 DQ_26 QS_0 RDQS1
B22 DQ_27 QS_1 D23
MDB28 C20 B26 RDQS2
MDB29 DQ_28 QS_2 RDQS3

read strobe
B20 DQ_29 QS_3 B21 RDQS[7..4] <22>
MDB30 A20 B6 RDQS4
MDB31 DQ_30 QS_4 RDQS5
C19 DQ_31 QS_5 E7
MDB32 C8 E2 RDQS6
MDB33 DQ_32 QS_6 RDQS7
C7 DQ_33 QS_7 J2 WDQS[3..0] <22>
MDB34 B7
MDB35 DQ_34 WDQS0
A7 DQ_35 QS_0B C31
MDB36 A5 E23 WDQS1
MDB37 DQ_36 QS_1B WDQS2
C4 A26

write strobe
MDB38 DQ_37 QS_2B WDQS3
B4 DQ_38 QS_3B A21 WDQS[7..4] <22>
MDB39 A3 A6 WDQS4
MDB40 DQ_39 QS_4B WDQS5
G9 DQ_40 QS_5B D7
MDB41 E9 E1 WDQS6
C MDB42 DQ_41 QS_6B WDQS7 C
D9 DQ_42 QS_7B J1
MDB43 G7
MDB44 DQ_43 ODT0
G5 DQ_44 ODT0 E20 ODT0
MDB45 F5 C11 ODT1
DQ_45 ODT1 ODT1
MDB46 G4
MDB47 DQ_46 CLKA0
F4 DQ_47 CLK0 A18 CLKA0 <22>
MDB48 B3 A11 CLKA1
DQ_48 CLK1 CLKA1 <22>
MDB49 B2
MDB50 DQ_49 CLKA0#
C2 DQ_50 CLK0B B18 CLKA0# <22>
MDB51 C1 B11 CLKA1#
DQ_51 CLK1B CLKA1# <22>
MDB52 E3
MDB53 DQ_52 RASA0#
F3 DQ_53 RAS0B G20 RASA0# <22>
MDB54 F2 D12 RASA1#
DQ_54 RAS1B RASA1# <22>
MDB55 F1
VDD_MEM18 MDB56 DQ_55 CASA0#
G2 DQ_56 CAS0B D20 CASA0# <22>
MDB57 G1 E12 CASA1#
DQ_57 CAS1B CASA1# <22>
MDB58 H3 DQ_58
1

MDB59 H2 E18 CSA0_0#

DQ_59 CS0B_0 CSA0_0# <22>
R1801 MDB60 K2 G18
40.2_0402_1% MDB61 DQ_60 CS0B_1
L3 DQ_61
MDB62 L2 G11 CSA1_0#
DQ_62 CS1B_0 CSA1_0# <22>
MDB63 L1 E11
2

DQ_63 CS1B_1
VDD_MEM18_REFD F30 D18 CKEA0
MVREFD CKE0 CKEA0 <22>
VDD_MEM18_REFS F31 G12 CKEA1
MVREFS CKE1 CKEA1 <22>
1 C1429
1

0.1U_0402_16V4Z D16 WEA0#

WE0b WEA0# <22>
R1802 L5 C10 WEA1#
TEST_MCLK WE1b WEA1# <22>
100_0402_1% L7
2 TEST_YCLK
J7 MEMTEST DRAM_RST J5 DRAM_RST# <22>
2

R1803 0904 Add

B 216PTAKA13FG M62-S_BGA632 B

1
VDD_MEM18 4.7K_0402_5% R1804
1

R1805
4.7K_0402_5% 4.7K_0402_5%
2
1

R1806
2

40.2_0402_1% R1807
2

243_0402_1%
2

2
1

1
R1808
100_0402_1% C1430
0.1U_0402_16V4Z
2
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M62-S MEM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 20 of 57
5 4 3 2 1
 5 4 3 2 1

U80E U80D
Part 5 of 6
PART 4 OF 6
VDD_MEM18
VSS_33 B25 1.1A
AA26 J8 10U_0603_6.3V6M 10U_0603_6.3V6M A15 AF30
PCIE_VSS_1 VSS_34 VDDR1_1 PCIE_VDDR_1
AA29 PCIE_VSS_2 VSS_35 B5 1 1 1 1 A22 VDDR1_2 PCIE_VDDR_2 AF31
AC26 PCIE_VSS_3 VSS_36 D11 A28 VDDR1_3 PCIE_VDDR_3 AF29
AD31 C17 C1431 C1432 C1433 C1434 A4 AF27
PCIE_VSS_4 VSS_37 VDDR1_4 PCIE_VDDR_4
AE29 PCIE_VSS_5 VSS_38 C22 A8 VDDR1_5 PCIE_VDDR_5 AF28
2 2 2 2
AE30 PCIE_VSS_6 VSS_39 C27 B8 VDDR1_6 PCIE_VDDR_6 AG29
AE31 PCIE_VSS_7 VSS_40 D29 C9 VDDR1_7 PCIE_VDDR_7 AG30 1.54A

Memory I/O
F28 C3 10U_0603_6.3V6M 10U_0603_6.3V6M D1 AG31
PCIE_VSS_8 VSS_41 VDDR1_8 PCIE_VDDR_8 L80
G26 PCIE_VSS_9 VSS_42 C6 H1 VDDR1_9
D 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z PCIE_VDDC D
G29 PCIE_VSS_10 VSS_43 D3 H11 VDDR1_10 PCIE_VDDC_1 AA23 2 1 PCIE_1.2V

PCI-Express GND
G30 D28 1 1 1 1 H12 AC24 1 1 1 1 0_0805_5%
PCIE_VSS_11 VSS_44 VDDR1_11 PCIE_VDDC_2
G31 PCIE_VSS_12 VSS_45 F29 H14 VDDR1_12 PCIE_VDDC_3 AC25

PCI-Express
H29 D4 C1438 C1439 C1440 C1441 H16 AE26 C1442 C1443 C1444 C1445
PCIE_VSS_13 VSS_46 VDDR1_13 PCIE_VDDC_4 0.1U_0402_16V4Z
J25 PCIE_VSS_14 VSS_47 F11 H18 VDDR1_14 PCIE_VDDC_5 AE27
2 2 2 2 2 2 2 2
J26 PCIE_VSS_15 VSS_48 F12 H20 VDDR1_15 PCIE_VDDC_6 AE28
L26 F14 H21 L23 10U_0603_6.3V6M 1U_0402_6.3V4Z
PCIE_VSS_16 VSS_49 1U_0402_6.3V4Z 1U_0402_6.3V4Z VDDR1_16 PCIE_VDDC_7
L29 PCIE_VSS_17 VSS_50 F16 B31 VDDR1_17 PCIE_VDDC_8 M23
L30 PCIE_VSS_18 VSS_51 F18 M1 VDDR1_18 PCIE_VDDC_9 P23
L31 F20 1U_0402_6.3V4Z 1U_0402_6.3V4Z T23
PCIE_VSS_19 VSS_52 PCIE_VDDC_10 VGA_VCORE
M26 PCIE_VSS_20 VSS_53 F21 J11 VDD_CT_1 PCIE_VDDC_11 V23
M29 F23 1 1 1 1 J20 Y23 PAD-OPEN 4x4m 1.5A
PCIE_VSS_21 VSS_54 VDD_CT_2 PCIE_VDDC_12
P26 PCIE_VSS_22 VSS_55 F25 J21 VDD_CT_3
C1446 C1447 C1448 C1449 PJP19
R29 PCIE_VSS_23 VSS_56 F7 L9 VDD_CT_4
R30 F9 L11 VGA_VCORE 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 2 VDD_CORE
PCIE_VSS_24 VSS_57 2 2 2 2 VDDC_1
R31 PCIE_VSS_25 VSS_58 G3 AA9 VDD_CT_5 VDDC_2 L14 1 1 1 1
T26 PCIE_VSS_26 VSS_59 G6 Y9 VDD_CT_6 VDDC_3 L17
U29 H23 1U_0402_6.3V4Z 1U_0402_6.3V4Z V9 L20 C1451 C1452 C1453 C1454
PCIE_VSS_27 VSS_60 VDD_CT_7 VDDC_4
V26 PCIE_VSS_28 VSS_61 J3 110mA T9 VDD_CT_8 VDDC_5 M12
2 2 2 2
Y26 J4 1 2 VDD_CT M15
PCIE_VSS_29 VSS_62 +2.5VS VDDC_6
Y29 J6 R1809 0_0603_5% AC18 M18 10U_0603_6.3V6M 1U_0402_6.3V4Z

I/O Internal
PCIE_VSS_30 VSS_63 VDDR3_1 VDDC_7
Y30 PCIE_VSS_31 VSS_64 K1 1 1 AC16 VDDR3_2 VDDC_8 M21
Y31 L12 C12 AC14 AC20 1U_0402_6.3V4Z 1U_0402_6.3V4Z
PCIE_VSS_32 VSS_65 10U_0603_6.3V6M C1456 VDDR3_3 VDDC_9
VSS_66 L15 AC12 VDDR3_4 VDDC_10 P14 1 1 1 1
L18 1U_0402_6.3V4Z P17
VSS_67 2 2 VDDC_11 C1457 C1458 C1459 C1460
VSS_68 L21 AF1 VDDR4_1 P VDDC_12 P20
VSS_69 L6 0906 add 10uF AF2 VDDR4_2 VDDC_13 R12
2 2 2 2
A13 VSS_1 VSS_70 M11 150mA O VDDC_14 R15

Core
A2 M14 AE1 R18 10U_0603_6.3V6M 1U_0402_6.3V4Z
VSS_2 VSS_71 VDDR5_1 VDDC_15
C18 VSS_3 VSS_72 M17 M62_VDDR 1U_0402_6.3V4Z 1U_0402_6.3V4Z AE2 VDDR5_2 W VDDC_16 R21
A24 M20 1 1 1 1 AD20 1U_0402_6.3V4Z 1U_0402_6.3V4Z
VSS_4 VSS_73 E VDDC_17
A30 VSS_5 VSS_74 M6 VDDC_18 U14 1 1 1 1
C C1462 C1463 C1464 C1465 C
AA1 P12 M2 U17
AA11
VSS_6 VSS_75
P15 10U_0603_6.3V6M M3
NC_1 R VDDC_19
U20 C1466 C1467 C1468 C1469
VSS_7 VSS_76 2 2 2 2 NC_2 VDDC_20
AA14 VSS_8 VSS_77 P18 L4 NC_3 VDDC_21 V12
2 2 2 2
AA17 VSS_9 VSS_78 P21 AE7 NC_4 VDDC_22 V15
AA20 P6 1U_0402_6.3V4Z V18 10U_0603_6.3V6M 1U_0402_6.3V4Z
VSS_10 VSS_79 VDDC_23
AA6 VSS_11 VSS_80 AC21 VDDC_24 V21
AC2 R14 Y11 1U_0402_6.3V4Z 1U_0402_6.3V4Z
VSS_12 VSS_81 PJP17 VDDC_25
AC7 VSS_13 VSS_82 R17 VDD_MEM_CLK0 A10 VDDRH_1 VDDC_26 Y14 1 1 1 1
AE3 R20 2 1 10U_0603_6.3V6M 1U_0402_6.3V4Z A19 Y17
VSS_15 VSS_83 VDD_MEM_CLK1 VDDRH_2 VDDC_27

Clock
I/O
Memory
AL4 T6 Y20 C1471 C1472 C1473 C1474
VSS_16 VSS_84 PAD-OPEN 2x2m VDDC_28
AD14 VSS_17 VSS_85 U1 1 1 1 1 VDDC_29 AA12
C1480 2 2 2 2
AF12 VSS_18 VSS_86 U12 B10 VSSRH_1 VDDC_30 AA15
AF14 U15 PJP18 C1476 C1477 C1478 0.1U_0402_16V4Z B19 AA18 10U_0603_6.3V6M 1U_0402_6.3V4Z
VSS_19 VSS_87 VSSRH_2 VDDC_31
AD16 VSS_20 VSS_88 U18 VDD_MEM18 2 1 VDDC_32 AA21
2 2 2 2
AD18 VSS_21 VSS_89 U21 VDDC_33 P9
AE6 AE20 @PAD-OPEN 2x2m
VSS_22 VSS_90 1U_0402_6.3V4Z 1U_0402_6.3V4Z
AG2 VSS_23 VSS_91 V14 V11 BBN_1

Back Bias
AE9 V17 U11 J12 VDDCI 1 1U_0402_6.3V4Z 2 1
VSS_24 VSS_92 BBN_2 VDDCI_1 C1481 L81
AH25 VSS_25 VSS_93 V20 VDDCI_2 J14 1 1 1
AK1 P2 0904 change power rail Q130 J16 C1482 C1483 CHB1608U301_0603
VSS_26 VSS_94 VDDCI_3
AK31 VSS_27 VSS_95 V6 R11 BBP_1 VDDCI_4 J18
2 C1484
S

AJ6 W2 1 3 P11
D

VSS_28 VSS_96 +3VS BBP_2 2 2 2

AL2 VSS_29 VSS_97 Y12
AL30 Y15 SI2301BDS_SOT23 0.1U_0402_16V4Z 10U_0603_6.3V6M
VSS_30 VSS_98
2

B1 Y18 R1813
G

216PTAKA13FG M62-S_BGA632
2

VSS_31 VSS_99 100K_0402_5%

C13 VSS_32 VSS_100 Y21
VSS_101 Y6
VSS_102 M9
PLACE ALL CAPS ON THIS PAGE CLOSE TO ASIC
1

B
CORE GND B
216PTAKA13FG M62-S_BGA632 @ R1897
1

0_0402_5% D

<26,31,37,40,41,49,50> PWR_GD 2 1 2
G
20K_0402_5% S Q129
3

VDD_MEM18 2 1 RHU002N06_SOT323
2
R1898

C1605
0.1U_0402_16V4Z 1

VDD_MEM18 VDD_MEM_CLK0
0_0603_5%
1 2
R1879 1 1 1.1A
C1553 C1555
2 2

1U_0402_6.3V4Z 10U_0603_6.3V6M

A A
VDD_MEM_CLK1
0_0603_5%
1 2
R1880 1 1 1.1A
C1557 C1558
2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title
1U_0402_6.3V4Z 10U_0603_6.3V6M
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M62-S POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 21 of 57
5 4 3 2 1
 5 4 3 2 1

DDR3 VRAM: 8Mx32/16Mx32 FBGA_136P 2 pcs

VDD_MEM18

1
R1816
2.37K_0402_1%

2
G11

G11
D12

D12
B12

P12

B12

P12
T12

T12
L11

L11
G2

G2
10mil

D1
D4
D9

D1
D4
D9
VREFB

B1
B4
B9

P1
P4
P9

B1
B4
B9

P1
P4
P9
Place VREF divider and CAP

T1
T4
T9

T1
T4
T9
L2

L2
U81 U82
close to memory

1
D D
3

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
6 1 C1489
R1817 0.1U_0402_16V4Z
<20> MAB[11..0] <20> MAB[11..0]
5.49K_0402_1%
MAB4 K4 B2 MDB24 MDB[31..24] <20> MAB0 K4 B2 MDB48 MDB[55..48] <20>

2
MAB5 H2 A0 DQ0 MDB25 MAB1 A0 DQ0 MDB49 2
A1 DQ1 B3 H2 A1 DQ1 B3
MAB6 K3 C2 MDB26 MAB2 K3 C2 MDB50
MAB9 M4 A2 DQ2 MDB27 MAB3 A2 DQ2 MDB51
A3 DQ3 C3 M4 A3 DQ3 C3
MAB0 K9 E2 MDB28 MAB4 K9 E2 MDB52
MAB1H11 A4 DQ4 MDB29 MAB5 H11 A4 DQ4 MDB53
MAB2 K10 A5 DQ5 F3
MDB30 MAB6 K10 A5 DQ5 F3
MDB54
4
MAB11 L9 A6 DQ6 F2
G3 MDB31
1 MAB7 L9
A6 DQ6 F2
G3 MDB55
MAB10K11 A7 DQ7 MDB8 MDB[15..8] <20> MAB8 K11 A7 DQ7 MDB32 MDB[39..32] <20>
A8/AP DQ8 B11 A8/AP DQ8 B11 Place VREF divider and CAP
MAB3 M9 B10 MDB9 MAB9 M9 B10 MDB33
MAB8 K2 A9 DQ9 MDB10 MAB10 K2 A9 DQ9 MDB34
close to memory
A10 DQ10 C11 A10 DQ10 C11
MAB7 L4 C10 MDB11 MAB11 L4 C10 MDB35
A11 DQ11 MDB12 A11 DQ11 MDB36
DQ12 E11 DQ12 E11
F10 MDB13 F10 MDB37 VDD_MEM18
<20> DQMB[3..0] DQ13 <20> DQMB[7..4] DQ13
F11 MDB14 F11 MDB38 5
DQMB3 E3 DQ14 MDB15 DQMB6 DQ14 MDB39
DM0 DQ15 G10 E3 DM0 DQ15 G10

1
DQMB1 E10 M11 MDB16 MDB[23..16] <20> DQMB4 E10 M11 MDB40 MDB[47..40] <20>
DQMB2 N10 DM1 DQ16 MDB17 DQMB5 DM1 DQ16 MDB41
DQMB0 N3 DM2 DQ17 L10
N11 MDB18
2 DQMB7
N10
N3
DM2 DQ17 L10
N11 MDB42 R1819
DM3 DQ18 MDB19 DM3 DQ18 MDB43 2.37K_0402_1%
DQ19 M10 DQ19 M10
R11 MDB20 R11 MDB44

2
DQ20 MDB21 DQ20 MDB45
DQ21 R10 DQ21 R10
MDB22 MDB46 10mil VREFA
DQ22 T11
T10 MDB23 MDB[7..0] <20> DQ22 T11
T10 MDB47
7
DQ23 DQ23

1
H1 M2 MDB0 H1 M2 MDB56 MDB[63..56] <20>
VREFA VREF DQ24 MDB1 VREFB VREF DQ24 MDB57
H12 VREF DQ25 L3 0 H12 VREF DQ25 L3 1 C1490
N2 MDB2 N2 MDB58 R1823 0.1U_0402_16V4Z
DQ26 MDB3 DQ26 MDB59 5.49K_0402_1%
DQ27 M3 DQ27 M3
C MDB4 MDB60 C
J2 R2 J2 R2

2
NC DQ28 MDB5 NC DQ28 MDB61 2
DQ29 R3 DQ29 R3
BA2 H3 T2 MDB6 RASA1# H3 T2 MDB62
<20> BA2 RAS# DQ30 <20> RASA1# RAS# DQ30
CSA0_0# F4 T3 MDB7 CASA1# F4 T3 MDB63
<20> CSA0_0# CAS# DQ31 <20> CASA1# CAS# DQ31
CKEA0 H9 WEA1# H9 VDD_MEM18
<20> CKEA0 WE# <20> WEA1# WE#
CASA0# F9 E1 VDD_MEM18 CSA1_0#
F9 E1
<20> CASA0# CS# VDDQ <20> CSA1_0# CS# VDDQ
VDDQ A1 VDDQ A1
WEA0# H4 A12 CKEA1 H4 A12
<20> WEA0# CKE VDDQ <20> CKEA1 CKE VDDQ
VDDQ C1 VDDQ C1
CLKA0 J11 C4 CLKA1 J11 C4
<20> CLKA0 CK VDDQ <20> CLKA1 CK VDDQ
CLKA0# J10 C9 CLKA1# J10 C9
<20> CLKA0# CK# VDDQ <20> CLKA1# CK# VDDQ
VDDQ C12 <20> BA[2..0] VDDQ C12
BA1 G4 E4 BA0 G4 E4 VDD_MEM18
<20> BA1 BA0 VDDQ BA0 VDDQ
BA0 G9 E9 BA1 G9 E9
<20> BA0 BA1 VDDQ BA1 VDDQ
RASA0# H10 E12 0904 Add BA2 H10 E12 R1818 121_0402_1%
<20> RASA0# BA2 VDDQ R1830 BA2 VDDQ
243_0402_1% J4 J4 RASA0# 1 2
R1881 1 VDDQ VDDQ
2 ZQ01 A4 ZQ VDDQ J9 1 2 ZQ02 A4 ZQ VDDQ J9
VDD_MEM18 1 2 A9 N1 A9 N1 R1820 121_0402_1%
R13 1K_0402_5% J3 MF VDDQ 243_0402_1% MF VDDQ RASA1#
RFU VDDQ N4 J3 RFU VDDQ N4 1 2
U4 SEN VDDQ N9 U4 SEN VDDQ N9
U9 N12 U9 N12 R1821 121_0402_1%
<20> DRAM_RST# RES VDDQ <20> DRAM_RST# RES VDDQ
0904 Add R1 R1 CASA0# 1 2
VDDQ <20> RDQS[7..4] VDDQ
RDQS3 D3 R4 RDQS6 D3 R4
RDQS1 RDQS0 VDDQ RDQS4 RDQS0 VDDQ R1822 121_0402_1%
<20> RDQS[3..0] D10 RDQS1 VDDQ R9 D10 RDQS1 VDDQ R9
RDQS2 P10 R12 RDQS5 P10 R12 CASA1# 1 2
RDQS0 RDQS2 VDDQ RDQS7 RDQS2 VDDQ
P3 RDQS3 VDDQ U1 P3 RDQS3 VDDQ U1
WDQS3 D2 U12 WDQS6 D2 U12 R1824 121_0402_1%
WDQS1 WDQS0 VDDQ WDQS4 WDQS0 VDDQ WEA0#
D11 WDQS1 VDD A2 D11 WDQS1 VDD A2 1 2
WDQS2 P11 A11 WDQS5 P11 A11
WDQS0 WDQS2 VDD WDQS7 WDQS2 VDD R1825 121_0402_1%
P2 WDQS3 VDD F1 P2 WDQS3 VDD F1
F12 F12 WEA1# 1 2
<20> WDQS[3..0] VDD <20> WDQS[7..4] VDD
VDD K1 VDD K1
B R1826 121_0402_1% B
VDD K12 VDD K12
M1 M1 CSA0_0# 1 2
VDD
VDD

VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD VDD
VDD M12 VDD M12
R1827 121_0402_1%
HY5RS573225AFP-16_FBGA_136P HY5RS573225AFP-16_FBGA_136P CSA1_0# 1 2
A3
A10
G1
G12
J1
J12
L1
L12
U3
U10

U11
U2

A3
A10
G1
G12
J1
J12
L1
L12
U3
U10

U11
U2
VRAM@ VRAM@
R1828 121_0402_1%
CKEA0 1 2

R1829 121_0402_1%
CKEA1 1 2
VDD_MEM18 R1831 60.4_0402_1%
CLKA0 1 2
0.01U_0402_16V7K 0.1U_0402_16V4Z
R1834 60.4_0402_1%
CLKA0# 1 2
Place close to U81 1 1 1
C1497
1 1 1
0.1U_0402_16V4Z R1835 60.4_0402_1%
C1493 C1494 C1496 C1498 C1499 CLKA1 1 2
2 2 2 2 2 2
R1836 60.4_0402_1%
VDD_MEM18 1U_0402_6.3V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 10U_0603_6.3V6M 0.1U_0402_16V4Z CLKA1# 1 2
VDD_MEM18
1 1 1 1 1 1
C1506
1U_0402_6.3V4Z 10U_0603_6.3V6M
C1502 C1503 C1504 C1507 C1508
2 2 2 2 2 2 Place close to U82 1 1 1 1
C1515
0.1U_0402_16V4Z 1000P_0402_50V7K 10U_0603_6.3V6M 0.1U_0402_16V4Z
C1511 C1512 C1513
A 2 2 2 2 A

VDD_MEM18 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1
C1520

C1516 C1517 C1519

2 2 2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title
0.1U_0402_16V4Z 10U_0603_6.3V6M
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M62-S VRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 22 of 57
5 4 3 2 1
 5 4 3 2 1

+3VS

10K_0402_5% R1844
2 1 GPIO0 <19>
STRAPS PIN DESCRIPTION OF RECOMMENDED SETTING RECOMMENDED
10K_0402_5% R1847
2 1 GPIO1 <19>
TX_PWRS_ENB GPIO0 FULL SWING internal pull down 1 Closed to U80
Transmitter De-emphasis Enable 1
TX_DEEMPH_EN GPIO1
R1853 10K_0402_5% internal pull down
2 1 BLM18PG121SN1D_0603 110mA,20mils
GPIO5 <19>
+2.5VS 2 1 VDDDI_25
D 10K_0402_5% @ R1855 0 L89 D
GPIO4 Strap to set the debug muxes to bring out 1 1
2 1 GPIO6 <19> DEBUG_ACCESS DEBUG signals even if registers are inaccessible
C1586
internal pull down 10U_0603_6.3V6M C1592
2 2 1U_0402_6.3V4Z

PLL_IBIAS_RD GPIO[6:5] Bias Currentfor the PCIE PHY PLL GPIO6-->0

GPIO5-->1 L82 280mA, 20mils
2 1 +LVDDR
BLM18PG121SN1D_0603 1 1

10K_0402_5% @ R1857 C1569

2 1 10U_0603_6.3V6M 2 2
GPIO11 <19> 0 0 0 X
No ROM , with 128M frame buffer C1570
10K_0402_5% R1859 0.1U_0402_16V4Z
2 1 GPIO
GPIO13 <19> 0 1 0 X
ROMIDCFG[3:0] [9,13,12,11] No ROM , with 64M frame buffer
L83
internal pull down 2 1 +LPVDD
10K_0402_5% @ R1869 BLM18PG121SN1D_0603 1
2 1 VRAM_ID0 <19> 20mA, 10mils
C1572
1 2 10U_0603_6.3V6M
R1883 10K_0402_5% 2
10K_0402_5% @ R1870
2 1 VRAM_ID1 <19>
1 2 L84
R1884 10K_0402_5% VRAM_ID 0, 1, 2, 3
HYN@ R1871 2 1
C Samsung 8Mx32 1.8V 0 0 0 0 BLM18PG121SN1D_0603 1 +TPVDD C
2 1 VRAM_ID2 <19>
10K_0402_5% DVPDATA 60mA, 10mils
1 2 VRAM_ID[0:3] (20,21,22,23) Samsung 16Mx32 1.8V 0 0 0 1 C1575
R1885 10K_0402_5% 10U_0603_6.3V6M
SAM@ Hynix 8Mx32 1.8V 0 0 1 0 2
128M@ R1872
2 1 Hynix 16Mx32 1.8V 0 0 1 1
VRAM_ID3 <19>
10K_0402_5%
1 2
R1886 10K_0402_5% BLM18PG121SN1D_0603
64M@
Closed to U80 2 1
1 1
+TXVDDR
L85 100mA, 20 mils
C1578 C1580
VDD_MEM18 10U_0603_6.3V6M 0.001U_0402_50V7M
2 2
ZZZ5 ZZZ4
1 1
C1594 C1595
10U_0603_6.3V6M 0.1U_0402_16V4Z L86
2 2
2 1 +AVDD
Samsung VRAM group Hynix VRAM group BLM18PG121SN1D_0603 1
100mA, 20mils
Samsung@ Hynix@ C1581
10U_0603_6.3V6M
2

VGA Thermal Sensor ADM1032ARMZ

B Closed to U80 +3VS B

2
C1599
2

0.1U_0402_16V4Z R1893
1
10K_0402_5%
U84
1 8 ICH_SM_CLK BLM18PG121SN1D_0603
1

VDD SCLK
2 1 +A2VDD
<19> VGA_THERMDA VGA_THERMDA 2 7 ICH_SM_DA
C1600 D+ SDATA L88 1 120mA, 20mils
1 2 VGA_THERMDC 3 6 THERM_SCI#
D- ALERT# THERM_SCI# <4,26>
C1588
2200P_0402_50V7K THERM#_VGA 4 5 10U_0603_6.3V6M
<19> VGA_THERMDC THERM# GND 2
R1894 10K_0402_5%
+3VS 1 2 ADM1032ARMZ REEL_MSOP8

@ R1906 0_0402_5%
1 2

<4,19,26,31> ICH_SM_CLK ICH_SM_CLK

+3VS ICH_SM_DA
<4,19,26,31> ICH_SM_DA
2

R1896
<4,7,25> H_THERMTRIP#
10K_0402_5%
1

D
1

A Q31 A
2
RHU002N06_SOT323 G 0802 (R1A) add for VGA thermal function
1

D
S
3

2 THERM#_VGA <4>
G
S RHU002N06_SOT323
3

Q30
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M62-S Filters / Strap
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 23 of 57
5 4 3 2 1
 5 4 3 2 1

+3VS

1 2 PCI_DEVSEL#
R1514 8.2K_0402_5%
1 2 PCI_STOP#
R1515 8.2K_0402_5% <31> PCI_AD[0..31]
1 2 PCI_TRDY# U26B
R1516 8.2K_0402_5% PCI_AD0 D20 A4 PCI_REQ0#
PCI_FRAME# PCI_AD1 AD0 REQ0# PCI_GNT0#
D
1
R1517
2
8.2K_0402_5% PCI_AD2
E19
D19
AD1 PCI GNT0# D7
E18 PCI_REQ1# D
PCI_PLOCK# PCI_AD3 AD2 REQ1#/GPIO50
1 2 A20 AD3 GNT1#/GPIO51 C18 MDC_DIS
R1518 8.2K_0402_5% PCI_AD4 D17 B19 PCI_REQ2#
AD4 REQ2#/GPIO52 PCI_REQ2# <31>
1 2 PCI_IRDY# PCI_AD5 A21 F18 PCI_GNT2#
AD5 GNT2#/GPIO53 PCI_GNT2# <31>
R1519 8.2K_0402_5% PCI_AD6 A19 A11 PCI_REQ3#
PCI_SERR# PCI_AD7 AD6 REQ3#/GPIO54 PCI_GNT3#
1 2 C19 AD7 GNT3#/GPIO55 C10
R1520 8.2K_0402_5% PCI_AD8 A18
PCI_PERR# PCI_AD9 AD8 PCI_CBE#0
1 2 B16 AD9 C/BE0# C17 PCI_CBE#0 <31>
R1521 8.2K_0402_5% PCI_AD10 A12 E15 PCI_CBE#1
AD10 C/BE1# PCI_CBE#1 <31>
1 2 MBAY_DET# PCI_AD11 E16 F16 PCI_CBE#2
AD11 C/BE2# PCI_CBE#2 <31>
R1585 10K_0402_5% PCI_AD12 A14 E17 PCI_CBE#3
AD12 C/BE3# PCI_CBE#3 <31>
1 2 MDC_DIS PCI_AD13 G16
R1748 10K_0402_5% PCI_AD14 AD13 PCI_IRDY#
A15 AD14 IRDY# C8 PCI_IRDY# <31>
PCI_AD15 B6 D9 PCI_PAR
AD15 PAR PCI_PAR <31>
PCI_AD16 C11 G6 PCI_PCIRST#
+3VS PCI_AD17 AD16 PCIRST# PCI_DEVSEL#
A9 AD17 DEVSEL# D16 PCI_DEVSEL# <31>
PCI_AD18 D11 A7 PCI_PERR#
AD18 PERR# PCI_PERR# <31>
PCI_AD19 B12 B7 PCI_PLOCK#
PCI_PIRQA# PCI_AD20 AD19 PLOCK# PCI_SERR#
1 2 C12 AD20 SERR# F10 PCI_SERR# <31,37>
R1522 8.2K_0402_5% PCI_AD21 D10 C16 PCI_STOP#
AD21 STOP# PCI_STOP# <31>
1 2 PCI_PIRQB# PCI_AD22 C7 C9 PCI_TRDY#
AD22 TRDY# PCI_TRDY# <31>
R1523 8.2K_0402_5% PCI_AD23 F13 A17 PCI_FRAME#
AD23 FRAME# PCI_FRAME# <31>
1 2 PCI_PIRQC# PCI_AD24 E11
R1524 8.2K_0402_5% PCI_AD25 AD24 PCI_PLTRST#
E13 AD25 PLTRST# AG24 PCI_PLTRST# <31>
1 2 PCI_PIRQD# PCI_AD26 E12 B10 CLK_PCI_ICH
AD26 PCICLK CLK_PCI_ICH <15>
R1525 8.2K_0402_5% PCI_AD27 D8 G7 PCI_PME#
AD27 PME# PCI_PME#
1 2 PCI_PIRQE# PCI_AD28 A6 R1527
R1526 8.2K_0402_5% PCI_AD29 AD28
E8 AD29 1 2 +3VALW
1 2 PCI_PIRQG# PCI_AD30 D6 8.2K_0402_5%
R10 8.2K_0402_5% PCI_AD31 AD30
A3 AD31
2 1 PIRQH#
R189 8.2K_0402_5%
C
1 2 PCI_REQ0# PCI_PIRQA# F9
Interrupt I/F F8 PCI_PIRQE# C
PIRQA# PIRQE#/GPIO2 PCI_PIRQE# <31>
R1530 8.2K_0402_5% PCI_PIRQB# B5 G11 MBAY_DET#
PIRQB# PIRQF#/GPIO3 MBAY_DET# <28>
1 2 PCI_REQ1# PCI_PIRQC# C5 F12
<31> PCI_PIRQC# PIRQC# PIRQG#/GPIO4 PCI_PIRQG# <31>
R1531 8.2K_0402_5% PCI_PIRQD# A10 B3 PIRQH# 2 1
<31> PCI_PIRQD# PIRQD# PIRQH#/GPIO5 ACCEL_INT <31>
1 2 PCI_REQ2# 0_0402_5% 0601 change
R1532 8.2K_0402_5% ICH8M REV 1.0 R188 0301 change
1 2 PCI_REQ3#
R1533 8.2K_0402_5%

+3V_U43

14
4 VGARST#

P
A VGARST# <26>
<18> VGA_RST# 6 O
5 PLT_RST#
B PLT_RST# <7,28,36>

G
U43B

7
SN74LVC08APW_TSSOP14

PCI_GNT3#
1

R1534
@
1K_0402_5%
Boot BIOS Strap
2

B B
+3VALW

PCI_GNT0# SPI_CS#1 Boot BIOS Location

5
U56
PCI_PCIRST# 1

P
B PCI_RST#
4
0 1 SPI * 2 A
Y PCI_RST# <28,31>

1
A16 swap override Strap @ TC7SH08FU_SSOP5 R192

3
R1051
Low= A16 swap override Enble 1 0 PCI 0_0402_5%
100K_0402_5%

2 1
PCI_GNT3# High= Default*

2
1 1 LPC +3VALW

5
U59
PCI_GNT0# SPI_CS1#_R PCI_PLTRST# 1

P
<26> SPI_CS1#_R B
4 PLT_RST#
Y PLT_RST# <7,28,36>
Place closely pin B10 2 A
1

1
R1536 @ TC7SH08FU_SSOP5 R191

3
CLK_PCI_ICH R1535 @ 100K_0402_5%
1K_0402_5% 1K_0402_5% R1057
2

0_0402_5%
2 2

2
R1537 2 1

@ 10_0402_5% J35
PAD-NO SHORT 2x2m
1

A A
1
C1177
1

@ 8.2P_0402_50V
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(1/4)-PCI/INT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 24 of 57
5 4 3 2 1
 5 4 3 2 1

+3VS

R1538
GATEA20 2 1

10K_0402_5%

R1539
KB_RST# 2 1

10K_0402_5%
D +RTCVCC D

R1540 330K_0402_1%
1 2 LAN100_SLP +VCCP
R1541
R1542 1M_0402_5% H_FERR# 2 1
1 2 SM_INTRUDER# LPC_AD[0..3] <35,36,37>
U26A 56_0402_5%
R1543 330K_0402_1% ICH_RTCX1 AG25 E5 LPC_AD0 R1544 @
RTCX1 FWH0/LAD0
1 2 ICH_INTVRMEN ICH_RTCX2 AF24 RTCX2 FWH1/LAD1 F5 LPC_AD1 H_DPRSTP# 2 1
R1545 G8 LPC_AD2
ICH_RTCRST# FWH2/LAD2 LPC_AD3 56_0402_5%
+RTCVCC 1 2 AF23 RTCRST# FWH3/LAD3 F6
R1546 @
20K_0402_5% SM_INTRUDER# AD22 C4 LPC_FRAME# H_DPSLP# 2 1
INTRUDER# FWH4/LFRAME# LPC_FRAME# <35,36,37>
2 CLRP1

RTC
LPC
C1178 SHORT PADS ICH_INTVRMEN AF25 G9 LPC_DRQ0# 56_0402_5%
INTVRMEN LDRQ0# LPC_DRQ#0 <35>
LAN100_SLP AD21 E6
1U_0603_10V4Z LAN100_SLP LDRQ1#/GPIO23 T39 PAD
11/20 For RTC Accuracy fail to change

1
1 GLAN_CLK GATEA20
<29> GLAN_CLK B24 GLAN_CLK A20GATE AF13 GATEA20 <37>
AG26 H_A20M#
A20M# H_A20M# <4>
LAN_RSTSYNC D22
<29> LAN_RSTSYNC LAN_RSTSYNC
AF26 H_DPRSTP_R# 2 1 H_DPRSTP#
DPRSTP# H_DPRSTP# <5,7,49>
ICH_RTCX1 <29> LAN_RXD0 LAN_RXD0 C21 AE26 R1548 0_0402_5%
R1733 LAN_RXD1 LAN_RXD0 DPSLP#
<29> LAN_RXD1 B21 LAN_RXD1 H_DPSLP# <5>
1 2 ICH_RTCX2 <29> LAN_RXD2 LAN_RXD2 C22 AD24 H_FERR#
LAN_RXD2 FERR# H_FERR# <4>

LAN / GLAN
10M_0402_5% LAN_TXD0 D21 AG29 H_PWRGOOD
<29> LAN_TXD0 LAN_TXD0 CPUPWRGD/GPIO49 H_PWRGOOD <5>
1 1 LAN_TXD1 E20
<29> LAN_TXD1 LAN_TXD1
LAN_TXD2 C20 AF27 H_IGNNE#
<29> LAN_TXD2 LAN_TXD2 IGNNE# H_IGNNE# <4>
C528 C516 within 2" from R1557
15P_0402_50V8J 15P_0402_50V8J AH21 AE24 H_INIT#
2 2 <30> ENERGY_DET GLAN_DOCK#/GPIO13 INIT# H_INIT# <4> +VCCP
AC20 H_INTR
INTR H_INTR <4>

CPU
C R1549 1 GLAN_COMP KB_RST# C
+1.5VS 2 24.9_0402_1% D25 GLAN_COMPI RCIN# AH14 KB_RST# <37>
C25 GLAN_COMPO

1
<38> HDA_BITCLK_MDC R1551 33_0402_5% 1 2 HDA_BITCLK AD23 H_NMI
NMI H_NMI <4>
<32> HDA_BITCLK_CODEC R1550 33_0402_5% 1 2 AJ16 AG28 H_SMI# R1552
HDA_BIT_CLK SMI# H_SMI# <4>
R1553 33_0402_5% 1 2 AJ15
<32> HDA_SYNC_CODEC HDA_SYNC
Y4 R1554 33_0402_5% 1 2 HDA_SYNC AA24 H_STPCLK# 56_0402_5%
<38> HDA_SYNC_MDC STPCLK# H_STPCLK# <4>
1 4 R1555 33_0402_5% 1 2 HDARST# AE14
<32> HDA_RST#_CODEC

2
R1556 33_0402_5% HDA_RST# THRMTRIP_ICH# R1557 24_0402_1%
<32,38> HDA_RST#_MDC 1 2 THRMTRIP# AE27 1 2 H_THERMTRIP# <4,7,23>
2 3 HDA_SDIN0 AJ17
<32> HDA_SDIN0 HDA_SDIN0
HDA_SDIN1 AH17 AA23
<38> HDA_SDIN1 HDA_SDIN1 TP8 PD_D[0..15] <28>
32.768KHZ_12.5P_MC-146 AH15 HDA_SDIN2 PD_D0 placed within 2" from ICH8M

IHDA
AD13 HDA_SDIN3 DD0 V1
R1558 33_0402_5% 1 2 HDA_SDOUT U2 PD_D1
<38> HDA_SDOUT_MDC DD1
R1559 33_0402_5% 1 2 AE13 V3 PD_D2
+3VS <32> HDA_SDOUT_CODEC HDA_SDOUT DD2
R1560 T1 PD_D3
10K_0402_5% DD3 PD_D4
2 1 1 2 AE10 HDA_DOCK_EN#/GPIO33 DD4 V4
2 1 IDE_LED# SHORT PADS R1935 PAD T38 AG14 T5 PD_D5
HDA_DOCK_RST#/GPIO34 DD5
1

CLRP2 1K_0402_5% AB2 PD_D6

CHP202U_SC70 SATA_LED# DD6 PD_D7
AF10 SATALED# DD7 T6
Q144 T3 PD_D8
DD8 PD_D9
<28> SATA_RXN0_C AF6 SATA0RXN DD9 R2
3900P_0402_50V7K AF5 T4 PD_D10
<28> SATA_RXP0_C SATA0RXP DD10
HDA_BITCLK SATA_TXN0 C1179 1 2 SATA_TXN0_C AH5 V6 PD_D11
<28> SATA_TXN0 SATA0TXN DD11
SATA_TXP0 C1180 1 2 SATA_TXP0_C AH6 V5 PD_D12
<28> SATA_TXP0
2

SATA0TXP DD12
2

+3VS U1 PD_D13
R1561 3900P_0402_50V7K DD13 PD_D14 +3VS
AG3 SATA1RXN DD14 V2
10_0402_5% AG4 U6 PD_D15
SATA1RXP DD15

IDE
@ <31,37> GREEN_BATLED# AJ4 SATA1TXN
AJ3 AA4 PD_A0
PD_A0 <28>
1

SATA1TXP DA0 PD_A1 PD_IORDY# R1562 1

DA1 AA1 PD_A1 <28> 2 4.7K_0402_5%

SATA
AF2 AB3 PD_A2 PD_IRQ R1563 1 2 8.2K_0402_5%
SATA2RXN DA2 PD_A2 <28>
1 AF1 SATA2RXP
B PD_CS1# B
2007,0125 change AE4 SATA2TXN DCS1# Y6 PD_CS1# <28>
C1181

AE3 Y5 PD_CS3#
SATA2TXP DCS3# PD_CS3# <28>
2 CLK_PCIE_SATA# PD_IOR#
@ 10P_0402_25V8K <15> CLK_PCIE_SATA# AB7 SATA_CLKN DIOR# W4 PD_IOR# <28>
CLK_PCIE_SATA AC6 W3 PD_IOW# BATT1
<15> CLK_PCIE_SATA SATA_CLKP DIOW# PD_IOW# <28>
Y2 PD_DACK#
DDACK# PD_DACK# <28>
R1564 AG1 Y3 PD_IRQ
SATARBIAS# IDEIRQ PD_IRQ <28>
1 2 AG2 Y1 PD_IORDY#
SATARBIAS IORDY PD_IORDY# <28>
W5 PD_DREQ#
DDREQ PD_DREQ# <28>
24.9_0402_1%
+5VS +3VS ICH8M REV 1.0 CR2032 RTC BATTERY
Within 500 mils
1

R88
R90 +RTCVCC +3VL JP42
10K_0402_5%
10K_0402_5% ACES_85205-0200
BATT1.1
+
2

1
2
D14
R981 W=20mils 2
SATA_LED# 1 2 IDE_LED# 1 2 1 R976
D15 CH751H-40_SC76 IDE_LED# <31> W=20mils
0_0402_5%
3
W=20mils
1 2 W=20mils
-
MB2_LED#1 2 2 DAN202U_SC70 1K_0402_5%
<28> MB2_LED#
D16 CH751H-40_SC76
C665 conn@
1U_0603_10V4Z
1

A A
XOR CHAIN ENTRANCE STRAP:RSVD

+3VS R1567
1K_0402_5%
2 1 HDA_SDOUT_CODEC
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(2/4)_LAN,HD,IDE,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 25 of 57
5 4 3 2 1
 5 4 3 2 1

+3VS 10K_0402_5% R1929 11/20 For detect CPU and system power saving +3VS
+3VALW 1 2
1 2 SIRQ 0904 change
R1576 10K_0402_5% 1 2 LAN_PHYPC_R
<41> VCC_IDL

2
1 2 PM_CLKRUN# @ 0_0402_5% R1930
R1578 8.2K_0402_5% R1570 2.2K_0402_5%
1 2 GPIO39 R1571 2.2K_0402_5% U26C 10K_0402_5% 10K_0402_5%
R1579 10K_0402_5% 10K_0402_5% +3VALW 1 2 ICH_SMB_CLK AJ26 SMBCLK SATA0GP/GPIO21 AJ12 MB_PWR <28> R1767
@ R434
1 2 THERM_SCI# 10K_0402_5%
R1573 1 2 ICH_SMB_DATA AD19 AJ10 HDD_HALTLED

1
@ R1582 8.2K_0402_5% LINKALERT# SMBDATA SATA1GP/GPIO19
2 CK_PWRGD

SATA
AG21 AF11 2 1 1

GPIO
R1572 <31> CL_RST#1 LINKALERT# SATA2GP/GPIO36 NPCI_RST# <35,37> <21,31,37,40,41,49,50> PWR_GD

SMB
1 2CLKSATAREQ# 2 1 ME_EC_CLK1 AC17 SMLINK0 SATA3GP/GPIO37 AG11 GPIO37 @ 0_0402_5% R147

1
R1600 10K_0402_5% ME_EC_DATA1 D
+3VALW 2 1 AE19 SMLINK1 1
1 2 GPIO37 <37> ME_EC_CLK1 CLK14 AG9 CLK_14M_ICH
CLK_14M_ICH <15> <49> CLK_EN# 2 1 2 VRMPWRGD
R1595 8.2K_0402_5% ICH_RI# CLK_48M_ICH 0_0402_5% R146

Clocks
AF17 G5 G
<37> ME_EC_DATA1 RI# CLK48 CLK_48M_ICH <15>
1 2 GPIO18 Q20 S

3
D R1601 8.2K_0402_5% ICH_SUSCLK RHU002N06_SOT323 2 @ D
<36> LPC_PD# F4 D3 T14 PAD

2
SUS_STAT#/LPCPD# SUSCLK
1 2 VGARST# <4> XDP_DBRESET#
XDP_DBRESET# AD15 SYS_RESET#
R1757
R1602 8.2K_0402_5% AG23 100K_0402_5%
SLP_S3# SLP_S3# <29,32,33,37,39,40,47,48,49,50,51,52>
1 2 GPIO20 10K_0402_5% @
R1581 <7> PM_BMBUSY#
PM_BMBUSY# AG12 BMBUSY#/GPIO0 SLP_S4# AF21 SLP_S4# <40,48>
R1617 8.2K_0402_5% 10K_0402_5% @ @R1727
@ R1727 AD18 @ C1620
R1580 SLP_S5# SLP_S5# <40,48>
1 2 IDE_RESET# +3VM 2 1 <29,30,39> LED_LINK_LAN# 1 2GPIO11_SBAG22 SMBALERT#/GPIO11
0.22U_0402_10V4Z
R11 8.2K_0402_5% 2 1 0_0402_5% AH27 S4_STATE#
S4_STATE#/GPIO26 S4_STATE# <34>
2 NPCI_RST# H_STP_PCI#

GPIO
1 <15> H_STP_PCI# AE20 STP_PCI#/GPIO15

SYS
R3 8.2K_0402_5% 2 1 R_STP_CPU# AG18 AE23 PM_PWROK
<15> H_STP_CPU# STP_CPU#/GPIO25 PWROK PM_PWROK <37>
1 2 MB_PWR R179 0_0402_5% 1 2 R1583
R6 8.2K_0402_5% AH11 AJ14 DPRSLPVR 10K_0402_5%
<31,35,36,37> PM_CLKRUN# CLKRUN#/GPIO32 DPRSLPVR/GPIO16 DPRSLPVR <7,49>

Power MGT
1 2 ALS_EN#
R16 8.2K_0402_5% ICH_PCIE_WAKE# AE17 AE21 ICH_LOW_BAT# 2 1
<31> ICH_PCIE_WAKE# WAKE# BATLOW# LOW_BAT# <37>
1 2 PM_BMBUSY# 11/20 solve auto-turn on <31,35,36,37> SIRQ
SIRQ AF12 SERIRQ
CH751H-40PT_SOD323-2 D22
R9 8.2K_0402_5% THERM_SCI# AC13 C2 ON/OFFBTN#
<4,23> THERM_SCI# THRM# PWRBTN# ON/OFFBTN# <38> 1 2 +3VL
1 2 OCP# R1722 R1630
R1590 10K_0402_5% 1 2 VRMPWRGD AJ20 AH20 1 2 100K_0402_5%
<7,37> VGATE VRMPWRGD LAN_RST# LAN_RST# <41>
@R145
@ R145 0_0402_5% 0_0402_5%
+3VALW SST_CTL AJ22 AG27 EC_RMRST# 1 2 PM_RSMRST#
PAD T15 TP7 RSMRST#
11/20 For detect CPU and system power saving R1586 100_0402_5%
1 2 LINKALERT# <4,50> OCP#
OCP# AJ8 TACH1/GPIO1 CK_PWRGD E1 CK_PWRGD_R 1 2 CK_PWRGD CK_PWRGD <15>
R1587 @ 10K_0402_5% RUNSCI_EC# AJ9 R148 0_0402_5%
<37> RUNSCI_EC# TACH2/GPIO6
1 2 LID_SW# <39> ISO_PREP# ISO_PREP# AH9 E3 M_PWROK
TACH3/GPIO7 CLPWROK M_PWROK <7,41>
R1593 10K_0402_5% <17,38> LID_SW# AE16 GPIO8
2 1ICH_LOW_BAT# <29> LAN_PHYPC 1 2 LAN_PHYPC_R AC19 GPIO12 SLP_M# AJ25 PM_SLP_M# PM_SLP_M# <37,40,47,48,52>
3.24K_0402_1% R1588
R1594 8.2K_0402_5% 0_0402_5% R349@ ALS_EN# AG8 1 2 +3VM
TACH0/GPIO17

1
1 2ICH_PCIE_WAKE# SPI_CS1# 2 1 GPIO18 AH12 GPIO18 CL_CLK0 F23 CL_CLK0 <7> 1
R1584 1K_0402_5% 0_0402_5% R1927 GPIO20 AE11 AE18 C1184 R1592
GPIO20 CL_CLK1 CL_CLK1 <31>

GPIO
Controller Link
1 2 ICH_RI# AG10 453_0402_1%
<24> VGARST# SCLOCK/GPIO22
R1597 10K_0402_5% PAD T48 AH25 F22
QRT_STATE0/GPIO27 CL_DATA0 CL_DATA0 <7> 2
1 2LAN_PHYPC <38> Cap_RST#_SB
Cap_RST#_SB AD16 AF19 CL_DATA1 <31>

2
R1603 10K_0402_5% QRT_STATE1/GPIO28 CL_DATA1 0.1U_0402_16V4Z
<15> CLKSATAREQ# AG13 SATACLKREQ#/GPIO35
C
1 2XDP_DBRESET# 2 1 R1591 GPIO38 AF9 D24 CL_VREF0_ICH +3VS C
<39> DOCK_ID SLOAD/GPIO38 CL_VREF0
R1589 1K_0402_5% +3VS 1 2 @ 0_0402_5% GPIO39 AJ11 AH23 CL_VREF1_ICH 1 2 +3VALW
SDATAOUT0/GPIO39 CL_VREF1

1
1 2S4_STATE# R1632
<28> IDE_RESET#
IDE_RESET# AD10 SDATAOUT1/GPIO48 1 R1596

2
R1631 10K_0402_5% 8.2K_0402_5% AJ23 0.1U_0402_16V4Z 3.24K_0402_1%
CL_RST# CL_RST# <7>
2 1 XMIT_OFF <32> SB_SPKR
SB_SPKR AD9 SPKR
C1185 R433
R1608 10K_0402_5% AJ27 XMIT_OFF
MEM_LED/GPIO24 XMIT_OFF <31> 2

MISC
2 1 USB_OC#5 <7> MCH_ICH_SYNC#
MCH_ICH_SYNC# AJ13 AJ24 CB_IN# 330_0402_5%

2
R1609 10K_0402_5% MCH_SYNC# ME_EC_ALERT/GPIO10
AF22 1 2 AMT ADP_PRES <37>

1
ICH_RSVD EC_ME_ALERT/GPIO14 R1738 R1598
ICH_RSVD AJ21 TP3 WOL_EN/GPIO9 AG19 LAN_WOL_EN <40> ALS_EN <17>
5 4 USB_OC#6 0_0402_5% 453_0402_1%

1
USB_OC#1 ICH8M REV 1.0 D
6 3
USB_OC#2 +3VALW J36 ALS_EN# 2
7 2
+3VALW
0612 Change GPIO pin assignment
8 1 USB_OC#4 SN74AHC1G08DCKR_SC70 U92 2 1 G Q45
CABLE_DETECT <30>
5

3
1

10K_1206_8P4R_5% RP55 1 low-->default PAD-SHORT 2x2m RHU002N06_SOT323

P

<29,32,33,37,39,40,47,48,49,50,51,52> SLP_S3# IN1

5 4 USB_OC#7 O 4 R1928 +3VS 1 2 SB_SPKR
6 3 USB_OC#8 +3VM_LAN 2 IN2
R1723 @ 10K_0402_5% High -->No boot
G

7 2 USB_OC#9 U26D
8 1 USB_OC#0 10K_0402_5% P27 V27 DMI_RXN0 DMI_RXN0 <7>
3

PERN1 DMI0RXN
2
G

P26 V26 DMI_RXP0 DMI_RXP0 <7> Place closely pin G5 Place closely pin AG9
10K_1206_8P4R_5% RP56 PERP1 DMI0RXP DMI_TXN0
N29 PETN1 DMI0TXN U29 DMI_TXN0 <7>
2 1 WXMIT_OFF# <29,30,39> LED_LINK_LAN# 3 GPIO11_SB
1 N28 U28 DMI_TXP0 DMI_TXP0 <7>

Direct Media Interface

R1944 10K_0402_5% RHU002N06_SOT323 PETP1 DMI0TXP CLK_48M_ICH CLK_14M_ICH
S

Q143 PCIE_RXN2 M27 Y27 DMI_RXN1 DMI_RXN1 <7>

<31> PCIE_RXN2 PERN2 DMI1RXN

1
R1604 100K_0402_5% 11/06 follow UMA SI-2 design change PCIE_RXP2 M26 Y26 DMI_RXP1 DMI_RXP1 <7>
<31> PCIE_RXP2 PERP2 DMI1RXP
1 2 DPRSLPVR WLAN <31> PCIE_TXN2 0.1U_0402_16V4Z 2 1 C710 PCIE_C_TXN2 L29 PETN2 DMI1TXN W29 DMI_TXN1 DMI_TXN1 <7> R1574 R1575
<31> PCIE_TXP2 0.1U_0402_16V4Z 2 1 C711 PCIE_C_TXP2 L28 W28 DMI_TXP1 DMI_TXP1 <7>
ICH_RSVD PETP2 DMI1TXP @ 10_0402_5% @ 10_0402_5%
2 1

PCI-Express
@ R1568 1K_0402_5% K27 AB26 DMI_RXN2 DMI_RXN2 <7>

2
PERN3 DMI2RXN DMI_RXP2
K26 PERP3 DMI2RXP AB25 DMI_RXP2 <7> 1 1
1 2 HDD_HALTLED 2007,0125 change J29 PETN3 DMI2TXN AA29 DMI_TXN2 DMI_TXN2 <7> C1182 C1183
R15 8.2K_0402_5% J28 AA28 DMI_TXP2 DMI_TXP2 <7>
B PETP3 DMI2TXP @ 4.7P_0402_50V8C @ 4.7P_0402_50V8C B
+3VM PCIE_RXN4 DMI_RXN3 2 2
<31> PCIE_RXN4 H27 PERN4 DMI3RXN AD27 DMI_RXN3 <7>
Robson PCIE_RXP4 H26 AD26 DMI_RXP3 DMI_RXP3 <7>
0316 change design <31> PCIE_RXP4 PERP4 DMI3RXP
<31> PCIE_TXN4 0.1U_0402_16V4Z 2 1 C708 PCIE_C_TXN4 G29 PETN4 DMI3TXN AC29 DMI_TXN3 DMI_TXN3 <7>
<31> PCIE_TXP4 0.1U_0402_16V4Z 2 1 C709 PCIE_C_TXP4 G28 AC28 DMI_TXP3 DMI_TXP3 <7>
PETP4 DMI3TXP
1

2.2K_0402_5%
2.2K_0402_5% R206 R204 PCIE_RXN5 F27 T26 CLK_PCIE_ICH#
<39> PCIE_RXN5 PERN5 DMI_CLKN CLK_PCIE_ICH# <15>
Q24 PCIE_RXP5 F26 T25 CLK_PCIE_ICH
<39> PCIE_RXP5 PERP5 DMI_CLKP CLK_PCIE_ICH <15>
RHU002N06_SOT323 Dock <39> PCIE_TXN5 0.1U_0402_16V4Z 2 1C1609 PCIE_C_TXN5 E29 PETN5
R1569 10K_0402_5%
<39> PCIE_TXP5 0.1U_0402_16V4Z 2 1C1610 PCIE_C_TXP5 E28 Y23 DMI_IRCOMP 1 2 +1.5VS 1 2
2

PETP5 DMI_ZCOMP
S

3 1 Y24 R1016 Within 500 mils PM_RSMRST#

<13,14,15> ICH_SMBDATA ICH_SMB_DATA <31> DMI_IRCOMP PM_RSMRST#
GLAN_RXN D27 24.9_0402_1%
<29> GLAN_RXN PERN6/GLAN_RXN
S

3 1 GLAN_RXP D26 G3 USB20_N0

<13,14,15> ICH_SMBCLK ICH_SMB_CLK <31> <29> GLAN_RXP PERP6/GLAN_RXP USBP0N USB20_N0 <34>
GLAN 0.1U_0402_16V4Z 1 C1186 GLAN_TXN_C USB20_P0
USB20_P0 <34>Right side
G

<29> GLAN_TXN 2 C29 G2

2

Q25 0.1U_0402_16V4Z PETN6/GLAN_TXN USBP0P

<29> GLAN_TXP 2 1 C1187 GLAN_TXP_C C28 PETP6/GLAN_TXP USBP1N H5 USB20_N1
USB20_N1 <36>
RHU002N06_SOT323 USB20_P1
USB20_P1 <36>Fingerprint
G

H4
2

15_0402_5% SPI_CLK_R USBP1P

1 2 R1605 C23 H2
+3VM <36> SPI_CLK
<36> SPI_CS0#
15_0402_5% 1 2 R1606 SPI_CS0#_R B23
SPI_CLK
SPI_CS0#
USBP2N
USBP2P H1 RSMRST circuit
15_0402_5% 1 2 R1607 SPI_CS1#_R E22 J3 R1908
<36> SPI_CS1# SPI_CS1# SPI USBP3N 0_0402_5%
+3VS <24> SPI_CS1#_R USBP3P J2 0619 change
0_0402_5% 2 1 R1640 SPI_SI_R D23 K5 USB20_N4 1 2
<36> SPI_SI SPI_MOSI USBP4N USB20_N4 <34>
0_0402_5% 1 R1641 SPI_SO_R USB20_P4 PM_RSMRST#
<34>Left side

C
2 F21 SPI_MISO USBP4P K4 USB20_P4 3 1
<36> SPI_SO USB20_N5 <37> RSMRST_EC

E
USBP5N K2 USB20_N5 <34>
1

2.2K_0402_5% USB_OC#0 USB20_P5 @ BAV99DW-7_SOT363 @ MMBT3906_SOT23

AJ19 OC0# USBP5P K1 USB20_P5 <34>Left side
2.2K_0402_5% R207 R205 R352 1 USB_OC#1 USB20_N6 Q137

B
2 AG16 L3 USB20_N6 <34>

12
OC1#/GPIO40 USBP6N

2
<34> BT_OFF 0_0402_5% USB_OC#2 USB20_P6
AG15 OC2#/GPIO41 USB USBP6P L2 USB20_P6 <34>Bluetooth
Q26 RHU002N06_SOT323 WXMIT_OFF# AE15 M5 USB20_N7 R1909 D68B D68A @
<31> WXMIT_OFF# OC3#/GPIO42 USBP7N USB20_N7 <39>
USB_OC#4 USB20_P7 @ 2.2K_0402_5% BAV99DW-7_SOT363
AF15 M4 USB20_P7 <39>Dock1
2

OC4#/GPIO43 USBP7P
S

3 1 ICH_SMB_DATA USB_OC#5 AG17 M2 USB20_N8

<4,19,23,31> ICH_SM_DA OC5#/GPIO29 USBP8N USB20_N8 <31>
USB_OC#6 USB20_P8
AD12 M1 USB20_P8 <31>WWAN

1
OC6#/GPIO30 USBP8P
S

<4,19,23,31> ICH_SM_CLK 3 1ICH_SMB_CLK USB_OC#7 AJ18 N3 USB20_N9

USB20_N9 <39> R1751

6
0_0402_5% USB_OC#8 OC7#/GPIO31 USBP9N USB20_P9
<39>Dock2
G

AD14 N2 USB20_P9 1 2
2

A CB_IN# USB_OC#9 OC8# USBP9P A

<37> GPIO29 1 2 AH18 OC9#
Q29 R161 USBRBIAS @ 2.2K_0402_5%
G

F2 1 2
2

RHU002N06_SOT323 USBRBIAS#
+5VS USBRBIAS F3
1 2 +3VALW R1019 22.6_0402_1%
+3VALW 10K_0402_5% R1599 ICH8M REV 1.0
2007,0125 change +3VS
Within 500 mils
HDD_HALTLED# <31>
1

R1007 R1008 Security Classification Compal Secret Data Compal Electronics, Inc.
1

D
Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title
10K_0402_5% 10K_0402_5% HDD_HALTLED 2 Q114
D57
G RHU002N06_SOT323 ICH8(3/4)_PM,USB,GPIO
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1 2 ISO_PREP# S AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
<30,32,39> PREP#
3

CH751H-40_SC76 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 26 of 57
5 4 3 2 1
 5 4 3 2 1

+RTCVCC U26E
20 mils A23 VSS[001] VSS[099] K7

0.1U_0402_16V4Z

0.1U_0402_16V4Z
A5 VSS[002] VSS[100] L1
1 1 AA2 VSS[003] VSS[101] L13

C1188

C1189
AA7 VSS[004] VSS[102] L15
+VCCP A25 L26
VSS[005] VSS[103]
AB1 VSS[006] VSS[104] L27
2 2
AB24 VSS[007] VSS[105] L4
U26F 0.1U_0402_16V4Z AC11 L5
VSS[008] VSS[106]
AD25 VCCRTC VCC1_05[01] A13 AC14 VSS[009] VSS[107] M12
VCC1_05[02] B13 AC25 VSS[010] VSS[108] M13
ICH_V5REF_RUN A16 C13 1 1 AC26 M14
V5REF[1] VCC1_05[03] C1192 C1193 0.1U_0402_16V4Z VSS[011] VSS[109]
T7 V5REF[2] VCC1_05[04] C14 AC27 VSS[012] VSS[110] M15
R1372 VCC1_05[05] D14 AD17 VSS[013] VSS[111] M16
ICH_V5REF_SUS G4 E14 AD20 M17
D 10U_0805_10V4Z V5REF_SUS VCC1_05[06] 2 2 VSS[014] VSS[112] D
+1.5VS 1 2 40 mils VCC1_05[07] F14 AD28 VSS[015] VSS[113] M23
1 AA25 VCC1_5_B[01] VCC1_05[08] G14 AD29 VSS[016] VSS[114] M28
CHB1608U301_0603 1 1 1 AA26 L11 AD3 M29
+ C1195 C1196 C1197 VCC1_5_B[02] VCC1_05[09] VSS[017] VSS[115]
AA27 VCC1_5_B[03] VCC1_05[10] L12 AD4 VSS[018] VSS[116] M3

C1194
AB27 VCC1_5_B[04] VCC1_05[11] L14 AD6 VSS[019] VSS[117] N1
220U_D2_4VM AB28 L16 AE1 N11
2 2 2 2 VCC1_5_B[05] VCC1_05[12] CHB1608U301_0603 VSS[020] VSS[118]
AB29 VCC1_5_B[06] VCC1_05[13] L17 R1370 AE12 VSS[021] VSS[119] N12
+5VS +3VS D28 L18 AE2 N13
10U_0805_10V4Z 2.2U_0603_6.3V4Z VCC1_5_B[07] VCC1_05[14] 0.01U_0402_16V7K VSS[022] VSS[120]
D29 VCC1_5_B[08] VCC1_05[15] M11 1 2 +1.5VS AE22 VSS[023] VSS[121] N14

CORE
E25 VCC1_5_B[09] VCC1_05[16] M18 AD1 VSS[024] VSS[122] N15
1

E26 VCC1_5_B[10] VCC1_05[17] P11 1 1 AE25 VSS[025] VSS[123] N16

R1610 D55 E27 P18 C1199 10U_0805_10V4Z AE5 N17
VCC1_5_B[11] VCC1_05[18] VSS[026] VSS[124]
F24 VCC1_5_B[12] VCC1_05[19] T11 AE6 VSS[027] VSS[125] N18
100_0402_5% CH751H-40_SC76 F25 T18 C1198 AE9 N26
VCC1_5_B[13] VCC1_05[20] 2 2 VSS[028] VSS[126]
20 mils G24 U11 AF14 N27
2

VCC1_5_B[14] VCC1_05[21] VSS[029] VSS[127]

H23 VCC1_5_B[15] VCC1_05[22] U18 AF16 VSS[030] VSS[128] N4
ICH_V5REF_RUN H24 V11 AF18 N5
VCC1_5_B[16] VCC1_05[23] VSS[031] VSS[129]
1 J23 VCC1_5_B[17] VCC1_05[24] V12 AF3 VSS[032] VSS[130] N6
C1190 J24 V14 +1.25VS AF4 P12
VCC1_5_B[18] VCC1_05[25] VSS[033] VSS[131]
K24 VCC1_5_B[19] VCC1_05[26] V16 AG5 VSS[034] VSS[132] P13
0.47U_0402_6.3V6K K25 V17 AG6 P14
2 VCC1_5_B[20] VCC1_05[27] VSS[035] VSS[133]

22U_0805_6.3VAM
L23 VCC1_5_B[21] VCC1_05[28] V18 AH10 VSS[036] VSS[134] P15
L24 VCC1_5_B[22] 1 AH13 VSS[037] VSS[135] P16

VCCA3GP

C1201
L25 VCC1_5_B[23] VCCDMIPLL R29 AH16 VSS[038] VSS[136] P17
M24 VCC1_5_B[24] AH19 VSS[039] VSS[137] P23
M25 VCC1_5_B[25] VCC_DMI[1] AE28 AH2 VSS[040] VSS[138] P28
2 +VCCP
N23 VCC1_5_B[26] VCC_DMI[2] AE29 AF28 VSS[041] VSS[139] P29
+5VALW +3VALW N24 AH22 R11
VCC1_5_B[27] VSS[042] VSS[140]
N25 VCC1_5_B[28] V_CPU_IO[1] AC23 AH24 VSS[043] VSS[141] R12
P24 VCC1_5_B[29] V_CPU_IO[2] AC24 AH26 VSS[044] VSS[142] R13
1

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
P25 VCC1_5_B[30] AH3 VSS[045] VSS[143] R14
R1611 D56 R24 AF29 0.1U_0402_16V4Z +3VS 1 1 1 AH4 R15
VCC1_5_B[31] VCC3_3[01] VSS[046] VSS[144]

C1202

C1203

C1204
C (DMI) C
R25 VCC1_5_B[32] 1 AH8 VSS[047] VSS[145] R16
10_0402_5% CH751H-40_SC76 R26 AD2 0.1U_0402_16V4Z +3VS AJ5 R17
VCC1_5_B[33] VCC3_3[02] (SATA) C1205 VSS[048] VSS[146]
R27 1 B11 R18
2

ICH_V5REF_SUS VCC1_5_B[34] 2 2 2 VSS[049] VSS[147]

T23 VCC1_5_B[35] VCC3_3[03] AC8 +3VS B14 VSS[050] VSS[148] R28
2

C1206
20 mils T24 VCC1_5_B[36] VCC3_3[04] AD8 B17 VSS[051] VSS[149] R4

VCCP_CORE
1 T27 VCC1_5_B[37] VCC3_3[05] AE8 B2 VSS[052] VSS[150] T12
C1200 +3VS 2
T28 VCC1_5_B[38] VCC3_3[06] AF8 B20 VSS[053] VSS[151] T13
T29 VCC1_5_B[39] B22 VSS[054] VSS[152] T14
0.1U_0402_16V4Z U24 AA3 0.1U_0402_16V4Z B8 T15
2 VCC1_5_B[40] VCC3_3[07] VSS[055] VSS[153]
U25 VCC1_5_B[41] VCC3_3[08] U7 1 C24 VSS[056] VSS[154] T16
V23 V7 C1207 C26 T17
VCC1_5_B[42] VCC3_3[09] VSS[057] VSS[155]
V24 VCC1_5_B[43] VCC3_3[10] W1 C27 VSS[058] VSS[156] T2
V25 W6 C6 U12
IDE
VCC1_5_B[44] VCC3_3[11] 2 +3VS VSS[059] VSS[157]
W25 VCC1_5_B[45] VCC3_3[12] W7 D12 VSS[060] VSS[158] U13
R1366 Y25 VCC1_5_B[46] VCC3_3[13] Y7 D15 VSS[061] VSS[159] U14
D18 VSS[062] VSS[160] U15
+1.5VS 1 2 AJ6 VCCSATAPLL VCC3_3[14] A8 D2 VSS[063] VSS[161] U16

0.1U_0402_16V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1U_0603_10V4Z

VCC3_3[15] B15 1 1 1 D4 VSS[064] VSS[162] U17

10U_0805_10V4Z

CHB1608U301_0603 AE7 B18 E21 U23

+1.5VS VCC1_5_A[01] VCC3_3[16] VSS[065] VSS[163]

C1208

C1209

C1210
1 1 AF7 VCC1_5_A[02] VCC3_3[17] B4 E24 VSS[066] VSS[164] U26
ARX
C1211

C1212

1 AG7 VCC1_5_A[03] VCC3_3[18] B9 E4 VSS[067] VSS[165] U27

C1213 2 2 2
AH7 VCC1_5_A[04] VCC3_3[19] C15 E9 VSS[068] VSS[166] U3
AJ7 D13 F15 U5
PCI

2 2 1U_0603_10V4Z VCC1_5_A[05] VCC3_3[20] VSS[069] VSS[167]

VCC3_3[21] D5 E23 VSS[070] VSS[168] V13
2
AC1 VCC1_5_A[06] VCC3_3[22] E10 F28 VSS[071] VSS[169] V15
AC2 VCC1_5_A[07] VCC3_3[23] E7 F29 VSS[072] VSS[170] V28
ATX

AC3 VCC1_5_A[08] VCC3_3[24] F11 F7 VSS[073] VSS[171] V29

AC4 VCC1_5_A[09] +3VS G1 VSS[074] VSS[172] W2
AC5 AC12 0.1U_0402_16V4Z E2 W26
VCC1_5_A[10] VCCHDA VSS[075] VSS[173]
1 G10 VSS[076] VSS[174] W27
AC10 AD11 0.1U_0402_16V4Z +3VALW G13 Y28
+1.5VS VCC1_5_A[11] VCCSUSHDA C1214 VSS[077] VSS[175]
1 AC9 VCC1_5_A[12] 1 G19 VSS[078] VSS[176] Y29
B C1216 B
VCCSUS1_05[1] J6 G23 VSS[079] VSS[177] Y4
T28 C1215 2
AA5 VCC1_5_A[13] VCCSUS1_05[2] AF20 G25 VSS[080] VSS[178] AB4
1U_0603_10V4Z T29
AA6 VCC1_5_A[14] G26 VSS[081] VSS[179] AB23
2 2
VCCSUS1_5[1] AC16 VCCSUS1_5_ICH_1 G27 VSS[082] VSS[180] AB5
T17
G12 VCC1_5_A[15] H25 VSS[083] VSS[181] AB6
G17 J7 VCCSUS1_5_ICH_2 +3VALW H28 AD5
VCC1_5_A[16] VCCSUS1_5[2] T18 VSS[084] VSS[182]
H7 VCC1_5_A[17] H29 VSS[085] VSS[183] U4
VCCSUS3_3[01] C3 0.1U_0402_16V4Z H3 VSS[086] VSS[184] W24
AC7 VCC1_5_A[18] 1 1 H6 VSS[087]

0.1U_0402_16V4Z
AD7 AC18 J1 A1 ICHGND1 1 2
VCC1_5_A[19] VCCSUS3_3[02] VSS[088] VSS_NCTF[01]
C1217

C1218 R138 0_0402_5%

VCCSUS3_3[03] AC21 J25 VSS[089] VSS_NCTF[02] A2
+1.5VS D1 VCCUSBPLL VCCSUS3_3[04] AC22 J26 VSS[090] VSS_NCTF[03] A28
VCCPSUS

2 2
+1.5VS VCCSUS3_3[05] AG20 J27 VSS[091] VSS_NCTF[04] A29 ICHGND2 1 2
1 1 F1 AH28 J4 AH1 R152 0_0402_5%
VCC1_5_A[20] VCCSUS3_3[06] VSS[092] VSS_NCTF[05]
USB CORE

C1219 C1220 L6 J5 AH29

VCC1_5_A[21] +3VALW VSS[093] VSS_NCTF[06]
L7 VCC1_5_A[22] VCCSUS3_3[07] P6 K23 VSS[094] VSS_NCTF[07] AJ1 ICHGND3 1 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z M6 P7 K28 AJ2 R153 0_0402_5%
2 2 VCC1_5_A[23] VCCSUS3_3[08] VSS[095] VSS_NCTF[08]
M7 VCC1_5_A[24] VCCSUS3_3[09] C1 K29 VSS[096] VSS_NCTF[09] AJ28
VCCSUS3_3[10] N7 1 K3 VSS[097] VSS_NCTF[10] AJ29 ICHGND4 1 2
+1.5VS W23 P1 C1222 K6 B1 R137 0_0402_5%
VCC1_5_A[25] VCCSUS3_3[11] VSS[098] VSS_NCTF[11]
VCCSUS3_3[12] P2 VSS_NCTF[12] B29
T30 VCC_LAN1_05_INT_ICH_1 F17 P3 4.7U_0603_6.3V6M
VCCLAN1_05[1] VCCSUS3_3[13]
VCCPUSB

+3VM T31 VCC_LAN1_05_INT_ICH_2 2 ICH8M REV 1.0

G18 VCCLAN1_05[2] VCCSUS3_3[14] P4
P5 +3VL
VCCSUS3_3[15] +3VS +3VS +3VS
F19 VCCLAN3_3[1] VCCSUS3_3[16] R1
G20 R3 +3VS
1 VCCLAN3_3[2] VCCSUS3_3[17]

2
C1223 CHB1608U301_0603 R5 @ R1718
VCCSUS3_3[18]

100K_0402_5%

100K_0402_5%

100K_0402_5%
1 2 A24 VCCGLANPLL VCCSUS3_3[19] R6
2

2
0.1U_0402_16V4Z +1.5VS R1365 R1371 4.7U_0805_10V4Z @ CRACK_GPIO28 CRACK_GPIO28 CRACK_GPIO28 R1715
2
GLAN POWER

G22 VCCCL1_05_ICH R1716 @ @ R1719

2.2U_0603_6.3V4Z

1 1 +1.5VS 2 1 A26 VCCGLAN1_5[1] VCCCL1_05 T19 100K_0402_5% R1717

1 A27

1 1
C1224 CHB1608U301_0603 VCCGLAN1_5[2] 1U_0603_10V4Z 1 100K_0402_5% CRACK_GPIO28 <11,37>
B26 VCCGLAN1_5[3] VCCCL1_5 A22
1

1
A C1225 D D D D A
B27
1

1
2 2 VCCGLAN1_5[4]
C1229
10U_0805_10V4Z

C1228 B28 F20 +3VM ICHGND3 2 ICHGND4 2 ICHGND2 2 ICHGND1 2

2 VCCGLAN1_5[5] VCCCL3_3[1] G G G G
VCCCL3_3[2] G21
2 @ Q124 @ Q125 @ Q126 @ Q127
+3VS B25 @ S S S S
3

3
VCCGLAN3_3 RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323
ICH8M REV 1.0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(4/4)_POWER&GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 27 of 57
5 4 3 2 1
 5 4 3 2 1

+3V_U43 Multi Bay II connector

1 2
<26> IDE_RESET#
C641 0.1U_0402_16V4Z conn@ JP5

14
JP45 conn@ 1
R301 1
S1 9 2

P
GND A 2
RX+ S2 SATA_TXP0 <25> O 8 2 1 ODD_RST# 3 3
S3 PLT_RST_B# 2 1 10 33_0402_5% 4
RX- SATA_TXN0 <25> B 4

G
S4 R1036 0_0402_5% 5 ODD_RST#
GND 5 PD_D[0..15] <25>
S5 SATA_RXN0 3900P_0402_50V7K 1 2 C474 U43C 6 PD_D8
SATA_RXN0_C <25>

7
TX- SATA_RXP0 3900P_0402_50V7K 6 PD_D7
TX+ S6 1 2 C475 SATA_RXP0_C <25>
SN74LVC08APW_TSSOP14
7 7
S7 2 1 8 PD_D9
GND <24,31> PCI_RST# 8
R1037 @ 0_0402_5% 9 PD_D6
D 9 PD_D10 D
close SATA connector 10 10
P1 11 PD_D5
3.3V 11 PD_D11
3.3V P2 12 12
P3 13 PD_D4
3.3V 13 PD_D12
GND P4 14 14
P5 15 PD_D3
GND 15 PD_D13
GND P6 16 16
P7 17 PD_D2
5V 17 PD_D14
5V P8 18 18
P9 10U_0805_10V4Z 0.1U_0402_16V4Z +5VS 19 PD_D1
5V 19 PD_D15
GND P10 20 20
P11 21 PD_D0
Rsv 21 PD_DREQ
GND P12 1 1 1 1 1 22 22 PD_DREQ# <25>
12V P13 23 23
P14 C1235 24 PD_IOR# PD_IOR# <25>
12V C1232 C1234 C1236 C1233 1U_0402_6.3V4Z 24 PD_IOW#
12V P15 25 25 PD_IOW# <25>
2 2 2 2 2
26 26
27 PD_IORDY
GND
GND

PD_IORDY# <25>
boss
boss

27 PD_DACK#
28 28 PD_DACK# <25>
29 PD_IRQ PD_IRQ <25>
0.1U_0402_16V4Z 1000P_0402_50V7K 29
30
26
25

24
23

30 PD_A1
31 31 PD_A1 <25>
OCTEK_SAT-22DD1G 32
32 PD_A0
33 33 PD_A0 <25>
34 PD_A2 PD_A2 <25>
34 PD_CS#1
35 35 PD_CS1# <25>
36 PD_CS#3 PD_CS3# <25>
36 MB2_LED#
37 37 MB2_LED# <25>
38 38
39 39
+3VS 40
40
41 41
C C
42 42 +5VS_MB

1
43 43
RR72 44
4.7K_0402_5% 44 MBAY_DET#
45 45
46 46
47

2
47
48 48

1
MBAY_DET# 49
<24> MBAY_DET# 49
1 50 R1032
C628 50 0_0402_5%
55 GND 51 51
56 GND 52 52
0.1U_0402_16V4Z 57 53

2
2 GND 53
58 GND 54 54

JAE_WM2M054JKB

+5VS
+5VS +5VS_MB
Q92
AO4407_SO8
1 8

1
1 2 7 1 1
R83 C640 3 6 C625
470K_0402_5% 5
10U_0805_10V4Z 0.1U_0402_16V4Z
2 C624 2 2

4
10U_0805_10V4Z
1 2

1
D
220K_0402_5% 1C633
<26> MB_PWR 2
B G R93 B
Q38 S 0.1U_0402_16V4Z

3
RHU002N06_SOT323 2

+5VS_MB

+5VS_MB
1 1
C626 C627

1
R98 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
100_0402_5%

1 2
D
2
G
Q39 S
Place close to JP29

3
RHU002N06_SOT323
+3V_U43
ZZZ2 ZZZ3

14
<7,24,36> PLT_RST# 12 A
P
Audio-wire PCB-MB
11 PLT_RST_B# PLT_RST_B# <31,35,36>
O
13 B
G

A A
U43D
7

SN74LVC08APW_TSSOP14

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & CDROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 28 of 57
5 4 3 2 1
 5 4 3 2 1

11/20 Enable ACBS (power management for NIC)

@R1612
@R1612 0_1206_5%
1 2
+3VM 40 mils

S
1000P_0402_50V7K 3

D
1 +3VM_LAN

2
SI2301BDS_SOT23

G
2

2
R1613 Q102 C1242
1M_0402_5% C1243 4.7U_0603_6.3V6M
2
D 1 D

1
R1614
1 2

100K_0402_5%

1
D
20 mils
<26> LAN_PHYPC 2 Q103 0.1U_0402_16V4Z +1.8VM_LAN
G BSS138_SOT23
S

3
2 2 2 2 2

1
4.7U_0603_6.3V6M C1245 C1246 C1247 470P_0402_50V7K

1
D R1730 C1244 C1248
<37,44,45,46,50> ADP_PRES 2 0_0402_5%
G 1 1 1 1 1
@ Q104 S
3

2
RHU002N06_SOT323
0.1U_0402_16V4Z 470P_0402_50V7K
1
D

<26,32,33,37,39,40,47,48,49,50,51,52> SLP_S3# 2
G
@ Q105 S
3

RHU002N06_SOT323

20 mils +V1.0_LAN_M
4.7U_0603_6.3V6M 0.1U_0402_16V4Z

XTAL1 2 2 2 2 2
near U74 XTAL2 C1250 C1251 C1252 470P_0402_50V7K
C1249 C1253
C C

H5
H6
R1615 33_0402_5% U74 1 1 1 1 1
1 2 GLANCLK E2 J9

XTAL2-X2
XTAL1-X1
<25> GLAN_CLK JKCLK-JCLK VSSA[17]-NC
VSSA[16]-NC J8
<25> LAN_RSTSYNC E3 J5 0.1U_0402_16V4Z 470P_0402_50V7K
JRSTSYNC VSSA[15]-VSSA2
VSSA[14]-VSS J3
<25> LAN_TXD0 LAN_TXD0 D1 J1
LAN_TXD1 JTXD0 LCI VSSA[13]-NC
<25> LAN_TXD1 F3 JTXD1 VSSA[12]-VSS G9
<25> LAN_TXD2 LAN_TXD2 F1 G8
JTXD2 VSSA[11]-VSS
VSSA[10]-VSS G6
<25> LAN_RXD0 LAN_RXD0 D3 F6
LAN_RXD1 JRXD0 VSSA[09]-VSS
<25> LAN_RXD1 D2 JRXD1 VSSA[08]-VSS E9
<25> LAN_RXD2 LAN_RXD2 C1 D6
JRXD2 VSSA[07]-VSS
VSSA[06]-VSS C9
C490 0.1U_0402_16V4Z C8 +3VM_LAN Q106 +1.8VM
GLAN_RXP_CH2 VSSA[05]-VSS BCP69_SOT223
<26> GLAN_RXP 1 2 GLAN_TXP-NC VSSA[04]-VSS C7
<26> GLAN_RXN 1 2 GLAN_RXN_C J2 C6 4
C1319 0.1U_0402_16V4Z GLAN_TXN-NC VSSA[03]-VSSR 0.1U_0402_16V4Z
VSSA[02]-NC A9 3 2
GLCI

<26> GLAN_TXP GLAN_TXP J4 A8

GLAN_TXN GLAN_RXP-NC VSSA[01]-VSS
<26> GLAN_TXN H4 GLAN_RXN-NC VSS[04]-VSS F4 2 2 2 1
2

10N_0603_50V7K
E1 C1256
1.4K_0402_1% R1616 LAN_KBIAS_P VSS[03]-VSSP C1257
G7 C4 1

1
LAN_KBIAS_N KBIAS_P-RBIAS100 VSS[02]-VSS C1254 C1255 10U_0805_10V4Z
H7 KBIAS_N-RBIAS10 VSS[01]-NC A1
4.7U_0603_6.3V6M1 1 1 2
C1258
1

LED_LINK_LAN# +V1.0_LAN_M 2
<26,30,39> LED_LINK_LAN# A4 LED0-LINK_UP_N VDD1P0[03]-VCCA F7
<30,39> LED_ACT_LAN# LED_ACT_LAN# B4 E8 R1618 0.1U_0402_16V4Z
LED1-ACT_LED_N VDD1P0[02]-VCCT LAN_CTRL_18
A5 LED2-SPEED_LED_N VDD1P0[01]-VCCR D7 1 2 +V1.0M_LAN
0_0603_5%
<30> LAN_MDI0P LAN_MDI0P B8 E5
LAN_MDI0N MDI_PLUS[0]-TDP VCCF1P0-VCC
<30> LAN_MDI0N B9 MDI_MINUS[0]-TDN
B 0_0603_5% B
MDI

<30> LAN_MDI1P LAN_MDI1P D9 H3 R1619

LAN_MDI1N MDI_PLUS[1]-RDP VCCFC1P0-VCC
<30> LAN_MDI1N D8 MDI_MINUS[1]-RDN 1 2 +3VM_LAN
F2 +3.3V_LAN C1611
LAN_MDI2P VCC3P3[02]-VCCP 1U_0402_6.3V4Z
<30> LAN_MDI2P F9 MDI_PLUS[2]-NC VCC3P3[01]-VCC B3 2 1
<30> LAN_MDI2N LAN_MDI2N F8 Q128
MDI_MINUS[2]-NC R1620 0_0603_5% +3VM_LAN +V1.0M_LAN
<30> LAN_MDI3P LAN_MDI3P H8 G5 +1.8VM_LAN 1 2 +1.8VM BCP69_SOT223
LAN_MDI3N MDI_PLUS[3]-NC VCC1P8[04]-NC R1734
<30> LAN_MDI3N H9 MDI_MINUS[3]-NC VCC1P8[03]-NC F5 4
D5 1 2 V1P_OUT 0.1U_0402_16V4Z 3 2
VCC1P8[02]-NC 0_0402_5%
VCC1P8[01]-NC C2
IEEE_TEST_P A7 2 1 2 2 2 1
IEEE_TEST_P-NC
1 2IEEE_TEST_N B7 IEEE_TEST_N-NC VCC1P0-VCCA2 G4 +V1.0_LAN_M +V1.0_LAN_M

10N_0603_50V7K
1 2 LAN_KBIAS_P R1621 @ 0_0402_5% C1612 C1357 1

1
@ R1622 649_0402_5% J6 E4 1U_0402_6.3V4Z 4.7U_0603_6.3V6M 10U_0805_10V4Z
RSVD_J6-NC VCC[02] C1356 1 1 1 2 C1359
LAN_KBIAS_N
closed to E6 pin J7 RSVD_J7-NC JTAG VCC[01] D4
C1360
1 2
@ R1623 619_0402_5% R1625 1.4K_0603_1% V1P_OUT 2
V1P0_OUT-NC B1
2 1 E7 0.1U_0402_16V4Z
JTAG_TMS-ISOL_EXEC

RBIAS_P-NC C1358
JTAG_TCK-ISOL_TCK

E6 RBIAS_N-NC
C3 LAN_CTRL_10 LAN_CTRL_10
JTAG_TDI-ISOL_TI

CTRL_10-NC
JTAG_TDO-TOUT

B2 LAN_CTRL_18
CTRL_18-NC
B5 RSVD_B5-NC
A6 RSVD_A6-ADV10/LAN_DIS_N
C5 A2 LAN_THERM_D_P
RSVD_C5-NC THERM_D_P-NC LAN_THERM_D_N 1
1 2 B6 TEST_EN THERM_D_N-NC A3 2
R1627 100_0402_5% @ R1628 0_0603_5%

RU82566DM B0 Q870 BGA 81P

G1
H1
G3
G2

@ R1629 200_0402_5%
A A
1 2 +3VM_LAN
T68 PAD PAD T69
Y9 XTAL1 T70 PAD PAD T71

+3VM_LAN 1 2
1 2 XTAL2_R 1 2 XTAL2 @ R1634 200_0402_5%

C1263
2
25MHZ_20P_1BG25000CK1A
2
C1264
R1936
30_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

1
27P_0402_50V8J
1
27P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Intel 82566 Nineveh
2007,0125 change AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 29 of 57
5 4 3 2 1
 5 4 3 2 1

LAN_MDI0N 12
T66
TD4- MX4- 13 MDO0- RJ-45 CONN.
+1.8VM LAN ENERGY DET
LAN_MDI0P 11 14 MDO0+
TD4+ 1:1 MX4+ +3VM
2 1 TRM_CT 10 15 MCT0 2 R269 1
C330 TCT4 MCT4 75_0402_1%
0.1U_0402_16V4Z LAN_MDI1N 9 16 MDO1- 100K_0402_5% 200K_0402_5% 1.5K_0402_5%
TD3- MX3-

1
1

1
D
02/27 change D
@ R1636 C1265
LAN_MDI1P 8 17 MDO1+ R1635 R1637 0.1U_0402_16V4Z
TD3+ 1:1 MX3+ C344 C1266 0.01U_0402_16V7K 2

5
2 1 TRM_CT 7 18 MCT1 2 R270 1 1 2 U75

2
C327 TCT3 MCT3 75_0402_1% LAN_MDI0P 2 R55 1 ED_ACT
1 2 1

P
0.1U_0402_16V4Z LAN_MDI2N 6 MDO2- 1000P_1808_3KV7K 10K_0402_5% 10P_0402_50V8J IN+
TD2- MX2- 19 O 4 1 2
ED_VREF 3 ENERGY_DET <25>
IN-

G
LAN_MDI1P 2 1 R69 1 2 1 R51 0_0402_5%

1
10K_0402_5% R1638

2
C1267 0.01U_0402_16V7K C1268 R1639
LAN_MDI2P 5 20 MDO2+ 100K_0402_5% 1.87K_0402_1% LMV331IDCKRG4_SC70-5~D
TD21+ 1:1 MX2+ 2

2
2 1 TRM_CT 4 21 MCT2 2 R271 1

2
C328 TCT2 MCT2 75_0402_1%
0.1U_0402_16V4Z LAN_MDI3N 3 22 MDO3-
TD1- MX1-
CAP closed to LAN_MDIO bus

LAN_MDI3P 2 23 MDO3+
TD1+ 1:1 MX1+ C320
2 1 TRM_CT 1 24 MCT3 2 R272 1 1 2
C329 TCT1 MCT1 75_0402_1%
0.1U_0402_16V4Z 24HST1041A-3_24P 1000P_1808_3KV7K
@D73
@ D73

MDO3+ 1 5 MDO1+

0.1U_0402_16V4Z 1 2 C56 R50 1 2 49.9_0402_1% LAN_MDI0N <29> 2

C R63 1 49.9_0402_1% C
2 LAN_MDI0P <29>
0.1U_0402_16V4Z 1 2 C54 R45 1 2 49.9_0402_1% LAN_MDI1N <29>
R48 1 2 49.9_0402_1% LAN_MDI1P <29>
0.1U_0402_16V4Z 1 2 C50 R42 1 2 49.9_0402_1% LAN_MDI2N <29> MDO3- 3 4 MDO1-
R44 1 2 49.9_0402_1% LAN_MDI2P <29>
0.1U_0402_16V4Z 1 2 C49 R40 1 2 49.9_0402_1% LAN_MDI3N <29>
R41 1 2 49.9_0402_1% LAN_MDI3P <29>
APL5301-18BC-TRL_SOT23-5

Layout Notice : Place

termination as close as @ D74
Intel 82566 as possible
MDO2+ 1 5 MDO0+
Note: MDO[3..0]+/- signals should route to JP4 first then to JP30.
2

JP4
+3VM_LAN_LED R266 2 1 300_0402_5% 13 Yellow LED+ MDO2- MDO0-
3 4
LED_ACT_LAN# 14
<29,39> LED_ACT_LAN# Yellow LED-
1 SHLD1 16
MDO3- 8
<39> MDO3- PR4-
@ C1625 9
330P_0402_50V7K MDO3+ DETECT PIN1 CABLE_DETECT <26> APL5301-18BC-TRL_SOT23-5
<39> MDO3+ 7 PR4+
2
MDO1- 6
B <39> MDO1- PR2- B
1
MDO2- 5 C579
<39> MDO2- PR3-
MDO2+ 4 0.1U_0402_16V4Z
<39> MDO2+ PR3+ 2
MDO1+ 3
<39> MDO1+ PR2+
MDO0- 2
<39> MDO0- PR1-
DETCET PIN2 10
MDO0+ 1
<39> MDO0+ PR1+
SHLD1 15
+3VM_LAN_LED R265 2 1 300_0402_5% 11 Green LED+
LED_LINK_LAN# 12
<26,29,39> LED_LINK_LAN# Green LED-
1
FOX_JM36113-P1122-7F
@C1624
@C1624 conn@
330P_0402_50V7K
2

20 mils
+3VM_LAN +3VM_LAN_LED
S

3 1
1

Q60
R525 AO3413_SOT23
G
2

A A
100K_0402_5%
2

<26,32,39> PREP# 2
G
Q61 S
Security Classification Compal Secret Data Compal Electronics, Inc.
3

RHU002N06_SOT323 2006/09/25 2006/09/25 Title

Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Magnetic & RJ45/RJ11
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 30 of 57
5 4 3 2 1
 A B C D E

B/B connector with PCI / LED / FIR / SC interface Mini-Express Card---WLAN

0824 Add +1.5VS_WLAN
0811 Isolate SLOT power from SYSTEM power.
+1.5VS_WLAN
+3VALW +3VS +3VS_WLAN
JP13 0915 Change 1394 signals 0.01U_0402_16V7K 4.7U_0805_10V4Z
XTPA0- 1 2 XTPB0- +3VS_WLAN R72
<34> XTPA0- 1 2 XTPB0- <34>
XTPA0+ 3 4 XTPB0+ 1 1 1 1 2
<34> XTPA0+ 3 4 XTPB0+ <34>
5 6 0.1U_0402_16V4Z C293 C294 C533 1 0_1206_5%
CLK_PCIE_Rob# 5 6 PCI_PIRQG# C954
<15> CLK_PCIE_Rob# 7 7 8 8 PCI_PIRQG# <24>
<15> CLK_PCIE_Rob CLK_PCIE_Rob 9 10 PCI_PIRQD# 1 1
9 10 PCI_PIRQD# <24> 2 2 2
R37 0_0402_5% 11 12 PCI_REQ2# C538 C542 0.1U_0402_16V4Z
<26> PCIE_RXN4 11 12 PCI_REQ2# <24> 2 +1.5VS +1.5VS_WLAN
PCIE_RXN4 2 1 NF_RXN 13 14 PCI_PLTRST#
<26> PCIE_RXP4 13 14 PCI_PLTRST# <24>
PCIE_RXP4 2 1 NF_RXP 15 16 CLKREQ#_E CLKREQ#_E <15,19> 0.1U_0402_16V4Z
1 R36 0_0402_5% 15 16 PCI_PIRQE# 2 2 R71 1
17 17 18 18 PCI_PIRQE# <24>
<26> PCIE_TXN4 PCIE_TXN4 19 20 PCI_PIRQC# 4.7U_0805_10V4Z 1 2
<26> PCIE_TXP4 19 20 PCI_PIRQC# <24>
PCIE_TXP4 21 22 PCI_RST# 0_1206_5%
21 22 PCI_RST# <24,28>
PCI_GNT2# 0821 Install R1364

55
56
23 23 24 24 PCI_GNT2# <24> JP44
CLK_PCI_PCM 25 26 SIRQ conn@
<15> CLK_PCI_PCM 25 26 SIRQ <26,35,36,37>
PCI_AD31 27 28 PWR_GD ICH_PCIE_WAKE# 1 2 +3VS_WLAN

DIP1
DIP2
27 28 PWR_GD <21,26,37,40,41,49,50> <26> ICH_PCIE_WAKE# 1 2
PCI_AD29 29 30 PCI_AD30 CH_DATA 3 4
29 30 <34> CH_DATA 3 4
PCI_AD27 31 32 PCI_AD28 CH_CLK 5 6 +1.5VS_WLAN
31 32 <34> CH_CLK 5 6
PCI_AD25 33 34 PCI_AD26 <15> CLKREQ#_G 1 2 CLKREQD#_MC 7 8
PCI_CBE#3 33 34 PCI_AD24 R1336 0_0402_5% 7 8
<24> PCI_CBE#3 35 35 36 36 9 9 10 10
PCI_AD23 37 38 PCM_SPK CLK_PCIE_MCARD# 11 12
37 38 PCM_SPK <32> <15> CLK_PCIE_MCARD# 11 12
PCI_AD21 39 40 PCI_AD22 CLK_PCIE_MCARD 13 14 0906 Remove debug resistors
39 40 <15> CLK_PCIE_MCARD 13 14
PCI_AD19 41 42 PCI_AD20 15 16
PCI_AD17 41 42 PCI_PAR 15 16
43 43 44 44 PCI_PAR <24> 0906 Remove debug resistors 17 17 18 18
PCI_CBE#2 45 46 PCI_AD18 19 20 XMIT_OFF#
<24> PCI_CBE#2 45 46 <15,36> CLK_DEBUG_PORT 19 20
PCI_IRDY# 47 48 PCI_AD16 R1348 0_0402_5% 21 22 0_0402_5%
<24> PCI_IRDY# 47 48 21 22 PLT_RST_B# <28,35,36>
PM_CLKRUN# 49 50 PCI_FRAME# <26> PCIE_RXN2 PCIE_RXN2 1 2 PCIE_C_RXN2 23 24 R1363 1 2 +3VALW
<26,35,36,37> PM_CLKRUN# 49 50 PCI_FRAME# <24> 23 24
PCI_SERR# 51 52 PCI_TRDY# <26> PCIE_RXP2 PCIE_RXP2 1 2 PCIE_C_RXP2 25 26 1 2 +3VM
<24,37> PCI_SERR# 51 52 PCI_TRDY# <24> 25 26
PCI_PERR# 53 54 PCI_STOP# R1349 0_0402_5% 27 28 @ R1364 0_0402_5%
<24> PCI_PERR# 53 54 PCI_STOP# <24> 27 28
PCI_CBE#1 55 56 PCI_DEVSEL# 29 30
<24> PCI_CBE#1 55 56 PCI_DEVSEL# <24> 29 30 ICH_SMB_CLK <26>
PCI_AD14 57 58 PCI_AD15 PCIE_TXN2 31 32
57 58 <26> PCIE_TXN2 31 32 ICH_SMB_DATA <26>
PCI_AD12 59 60 PCIE_TXP2 33 34
PCI_AD10 59 60 PCI_AD13 <26> PCIE_TXP2 33 34
61 61 62 62
+3VS_WLAN
35 35 36 36 0612 change power plane
PCI_AD8 63 64 PCI_AD11 0821 Change +3VS to +3VS_WLAN 37 38
PCI_AD7 63 64 PCI_AD9 R197 37 38
65 65 66 66 <26> CL_CLK1 2 1 0_0402_5% 39 39 40 40 @ R1754
PCI_AD5 67 68 PCI_CBE#0 R195 2 1 0_0402_5% 41 42 WW_LED#_R
1 2WW_LED# 0_0402_5%
67 68 PCI_CBE#0 <24> <26> CL_DATA1 41 42 WW_LED# <36>
PCI_AD3 69 70 PCI_AD6 R194 2 1 0_0402_5% 43 44 WL_LED#
69 70 <26> CL_RST#1 43 44 WL_LED# <36>
PCI_AD1 71 72 PCI_AD4 45 46 WP_LED#_R
1 2WP_LED#
71 72 45 46 WP_LED# <36>
73 74 PCI_AD2 47 48 @ R1913
HDD_HALTLED# 73 74 PCI_AD0 47 48 0_0402_5%
<26> HDD_HALTLED# 75 75 76 76 49 49 50 50 0627 Add 0 ohm on PIN 42,46
+3VL 77 77 78 78 51 51 52 52
WL_BLUE_LED# 79 80 IRRX
2 <36,38> WL_BLUE_LED# 79 80 IRRX <35> 2
GREEN_BATLED# 81 82 IRTXOUT 0622 change to support AMT 53 54
<25,37> GREEN_BATLED# 81 82 IRTXOUT <35> GND1GND2
AMBER_BATLED# 83 84 IRMODE 0627 PIN37,43 connected to GND
<37> AMBER_BATLED# 83 84 IRMODE <35>
LED_STB# 85 86 MOLEX 67910-0002 52P
<37,38,39> LED_STB# IDE_LED# 87
85 86
88 SC_CD# PIN39,41 connected to +3VS +3VALW
<25> IDE_LED# 87 88 SC_CD# <34>
89 89 90 90 +3VS
+1.5VS 91 92 SC_CLK 0811 No install R1418,R1358,R1359,R1360
91 92 SC_CLK <34>
+3VS 93 94 SC_RST
93 94 SC_RST <34>

1
95 95 96 96 +SC_PWR 0906 Remove debug resistors
+5VS 97 98 SC_DATA R517
97 98 SC_DATA <34>

1
99 99 100 100
R516 @ 100K_0402_5%

2
101 102 @ 10K_0402_5% XMIT_OFF#
GND GND PCI_AD[0..31]
PCI_AD[0..31] <24> D72

1
D

<26> XMIT_OFF 1 2 2
G
ACES_88394-1A71 CH751H-40_SC76 Q58 S

3
@ RHU002N06_SOT323
0731 Install R1383 and no install R1382, do not support wake on WWAN card 0811 HP request
1 2
0811 Isolate SLOT power from SYSTEM power. R1422 0_0402_5%
+3VS_WWAN

Mini-Express Card--WWAN 0.01U_0402_16V7K 4.7U_0805_10V4Z

+3VALW +3VS +3VS_WWAN +3VS +3VS_ACL +3VS_ACL_IO
R82 C295
1
C540
1
C544
1
ACCELEROMETER R1355 R1356 +3VS_ACL
55
56

JP46
1 1 2 1 2 1 2
C959 1 2 0_1206_5% @ 0_0805_5% 0_0603_5%
DIP1
DIP2

1 2 2 2 2
3 3 4 4
5 5 6 6 2 1 1 1 1
3 2 UIM_PWR 0.1U_0402_16V4Z D64 C994 C995 C996 3
7 7 8 8
9 10 UIM_DATA +3VS CH751H-40_SC76
0.1U_0402_16V4Z 9 10 UIM_CLK U72 @ 0.01U_0402_16V7K 10U_0805_10V4Z
11 11 12 12
UIM_RST 0313 change design 2 2 2
13 13 14 14 1 CH1 CH4 6
15 16 UIM_VPP U64
15 16 0.1U_0402_16V4Z
17 17 18 18 2 Vn Vp 5
19 20 M_WXMIT_OFF#
19 20
21 21 22 22 3 CH2 CH3 4 <24> ACCEL_INT 1 INT/RDY GND 16
23 23 24 24 1 2 +3VALW R1361
25 26 @R1382
@R1382 0_0402_5% S DIO(BR) NUP4301MR6T1 TSOP-6
25 26
27 27 28 28 1 2 +3VS_WWAN 2 SDD RES 15 1 2
+3VS_WWAN 29 30 R1383 0_0402_5% DAN217_SC59 +3VS
29 30 @D13
@ D13 0_0402_5%
31 31 32 32
33 34 JP50 3 14
33 34 <4,19,23,26> ICH_SM_DA SDA/SDI/SPC GND
35 35 36 36 USB20_N8 <26> 3
37 38 4 1 UIM_PWR 1
37 38 USB20_P8 <26> GND VCC
1 2 39 40 UIM_VPP 5 2 UIM_RST 2 +3VS_ACL_IO 4 13 +3VS_ACL
R1071 39 40 VPP RST VDD_IO VDD
1 20_0603_5% 41 41 42 42 WW_LED#
WW_LED# <36>
UIM_DATA 6 I/O CLK 3 UIM_CLK
R1073 0_0603_5% 43 44 7 R1362
43 44 DET C554
45 45 46 46 <4,19,23,26> ICH_SM_CLK 5 SCL/SPC RES 12 1 2 +3VS_ACL
0.1U_0402_16V4Z

47 48 4.7U_0805_10V4Z
47 48 10K_0402_5% 0_0402_5%
49 49 50 50
51 51 52 52 GND 8 1 1 +3VS_ACL 2 1 6 CS VDD 11
9 C960 R1359 0619 Follow ST Demo circuit
GND
2

53 54 @ R1923 R1357
GND1GND2
7 NC RES 10 1 2 +3VS_ACL_IO
MOLEX 67910-0002 52P 10K_0402_5% 2 2
0619 Follow ST Demo circuit
conn@ 0_0402_5%
0821 Change +3VS to +3VS_WWAN 8 9
1

CK GND

2
0811 Pins 37 and 43 connect to GND and remove +1.5VS UIM_PWR TAITW_PMPAT6-06GLBS7N14N0
D66
R1391
4 M_WXMIT_OFF# LIS3LV02DL-TR _LGA16 4
<26> WXMIT_OFF#
1 2 2007,0125 change 0_0402_5%
CH751H-40_SC76 Must be placed in the center of the system.
0811 Reserve for SIM card does not meet rise time and a pull-up resistor is needed.
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title
0821 Delete SW1,C986,R521,D65,R200 Mini-Card/Mini-PCI/Accelerometer
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 31 of 57
A B C D E
 A B C D E F G H

VDDA_CODEC V_CODEC

1
+5VAMP<26,29,33,37,39,40,47,48,49,50,51,52> SLP_S3#

1
R329
U18 R456
10K_0402_5% 1
C390 R341 IN 49.9K_0402_1% 1
1 5

2
10K_0402_5% MONO_IN OUT
1 2 1 2 1 2 2 2 3 1

2
C430 0.1U_0402_16V4Z + C548 C552 C551 EN + C309 C307
ADJ 4

1
D 0.1U_0402_16V4Z 150K_0402_1% 100P_0402_50V8J
2 2 GND

1
<31> PCM_SPK 2 R330 C377 22U_B_10V 1U_0603_10V4Z 2 22U_B_10V 0.1U_0402_16V4Z
G 2 1 1 MIC5205BM5_SOT23-5 C553 R457 2 2
1 2
1 Q35 S 0.01U_0402_16V7K R258 1

3
RHU002N06_SOT323 1 0_0805_5% 0.01U_0402_16V7K 143K_0402_1%

2
1

2
VDDA_CODEC
Place R258 between DGND & AGND & close to U14
1

R350

10K_0402_5% 10K_0402_5%
C396 R359 @ 10K_0402_5%
R57 R35 R1914
2

1 2 1 2 0_0402_5% @
2 1 2 1 1 2
1

D 0.1U_0402_16V4Z 150K_0402_1%
<26> SB_SPKR 2 4.7U_0603_6.3V6M

D
G @C4
@ C4

S
<33> R_C_HP 1 3 3 1 HP_R_JACK <33>
Q68 S 1 2
3

RHU002N06_SOT323 RHU002N06_SOT323 Q138 Q139@

@ R61 @ RHU002N06_SOT323

G
G
2

2
+5VS 1 2
300K_0402_5%

2
D RHU002N06_SOT323

G
@ R62 RHU002N06_SOT323 RHU002N06_SOT323

G
+3VS 1 2 2 Q140@ @ Q141 @ Q142
10K_0402_5% G <33> L_C_HP 1 3 3 1 HP_L_JACK <33>

D
Place close to U14 S

S
3
R1400 <25,38> HDA_RST#_MDC 1 2
1 2 1 2 1 1 2
2 1 1K_0402_5% R1915
@R70
@ R70 C3 10K_0402_5% 0_0402_5%
R1916 R1917
0_1206_5% 0.47U_0402_10V4Z~D 10K_0402_5%
2 2 @ 2
@ @
V_CODEC VDDA_CODEC +3VS
2 1
C409 0.1U_0402_16V4Z 0_0603_5% R1399
1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS_CODEC 1 2
0_0805_5%
2 1 R159 1 1 1 1 2 1 1 1
C427 0.1U_0402_16V4Z C395 C147 C417 C148 C402 C156 C175
C393
0.1U_0402_16V4Z 10U_0805_10V4Z
2 2 2 2 1 2 2 2

25

38
2 1

9
C431 0.1U_0402_16V4Z U14
0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z

AVDD1

AVDD2

DVDD1

DVDD2
GND GNDA 14 35 LINE_OUTL LINE_OUTL <33>
T24 PAD AUX_L LINE_OUT_L
15 36 LINE_OUTR LINE_OUTR <33>
T21 PAD AUX_R LINE_OUT_R
<33> INT_MIC INT_MIC C425 1 2 1U_0603_10V4Z 16 37 T20
MIC3 MONO_OUT PAD
C426 1 2 1U_0603_10V4Z 17 39 L_HP L_HP <33>
MIC4 HP_LOUT_L
<39> DLINE_IN_L R370 2 1 6.04K_0402_5% DLINE_IN_R_L C423 1 2 1U_0603_10V4Z DLINE_IN_RC_L 23 41 R_HP R_HP <33>
R375 2K_0402_5% LINE_IN_L HP_LOUT_R @ 10P_0402_25V8K
1 2 2 1 1 2
<39> DLINE_IN_R R369 2 1 6.04K_0402_5% DLINE_IN_R_R C422 1 2 1U_0603_10V4Z DLINE_IN_RC_R 24 R1038 @ 33_0402_5% C1064
R374 2K_0402_5% LINE_IN_R
1 2 BIT_CLK 6 HDA_BITCLK_CODEC <25>
18 CD_L
T23 PAD 8 HDA_SDIN0_CODEC 2 R373 1
SDATA_IN HDA_SDIN0 <25>
2007,0125 change 20 33_0402_5%
T25 PAD CD_R
3 3
19 CD_GND
T26 PAD 43 R168 1 2 @ 4.7K_0402_5%
GPIO_0 PORT_A_SNS <33>
<33> MIC1 MIC1 1 2 MIC1_C 21 44 R167 1 2 @ 4.7K_0402_5% PORT PLACE TO
C204 1U_0603_10V4Z MIC1 GPIO_1 R136 10K_0402_5%
GPIO_2 2 1 2
<33> MIC2 MIC2 1 2 MIC2_C 22 3 R32 1 2 @ 4.7K_0402_5% MONO_OUT X
MIC2 GPIO_3 PREP# <26,30,39>
C205 1U_0603_10V4Z
SENSE_A 13 PORT A HP OUT, DOCK HP LO
SENSE_B SENSEA
VDDA_CODEC 1 2 34 SENSEB
R231 2.2K_0402_1% PORT B M/B MIC
1 2
R169 @ 0_0402_5% 27 AUD_REF PORT C DOCK LI
VREF
<25> HDA_RST#_CODEC 11 RESET# 1 1
28 T27 C424 C416 PORT D M/B SPK
MIC_BIAS_B T13 PAD
<25> HDA_SYNC_CODEC 10 SYNC MIC_BIAS_C 29
30 T12 PAD 1U_0603_10V4Z 0.1U_0402_16V4Z PORT E X
MIC_BIAS_F T11 PAD 2 2
<25> HDA_SDOUT_CODEC 5 SDATA_OUT MIC_BIAS_D 32
VDDA_CODEC 12 MONO_IN PAD PORT F Internal MIC
PCBEEP
31 T7 PAD
N/C T8 PAD
N/C 33
<33,37> EAPD L53 1 2 47 40 T10 PAD
EAPD N/C
2

FBM-L10-160808-301-T_0603 45 T6 PAD
R969 NC T9 PAD
48 SPDIFO NC 46
2.67K_0402_1% T22 PAD
4 DVSS1 AVSS1 26
7 42
1

DVSS2 AVSS2
1 2 SENSE_A_A <33>
R970 39.2K_0402_1% AD1981HDJSTZ-REEL_LQFP48
VDDA_CODEC
SENSE_A 1 2 SENSE_A_B <33>
R972 20K_0402_1%
2

4 4
2

1 2 SENSE_A_C R974
R980 R973 10K_0402_1% @ 0_0402_5%
@ 0_0402_5% 2
1

Q97 D
1

C977 2 LINE_IN_SENSE LINE_IN_SENSE <39>

1

SENSE_B @ 1U_0402_6.3V4Z G 1
2

1 S C978
Security Classification Compal Secret Data Compal Electronics, Inc.
3

2N7002_SOT23 R988
0.1U_0402_16V4Z 2006/09/25 2006/09/25 Title
2 Issued Date Deciphered Date
AC97 CODEC AD1981B
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
100K_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 32 of 57
A B C D E F G H
 A B C D E

AMP. FOR INTERNAL SPEAKER AMP. FOR INTERNAL MICROPHONE

+5VALW +5VAMP Place close to U14 audio CODEC D62
C230
1 2
R443 C659
1 2 10U_0805_10V4Z 2 680P_0402_50V7K
1 R190
C1098 1 0_1206_5% 1 1 1 1 3 1 2
C660 C539
C662 + conn@ @ MIC_REF VDDA_CODEC 100K_0402_5%
PACDN042_SOT23~D

0.1U_0402_16V4Z
10U_0805_10V4Z @ 0.1U_0402_16V4Z JP36
2 150U_D_6.3VM 2 2 2
2

100P_0402_50V8J
1U_0603_10V4Z INT_MIC_2 1
1

C441
1 C585 1

12

18
2 1

C446
10 dB U39 1 2
Keep 10 mil width ACES_85205-0200

VDD
PVDD1
PVDD2
C503 R1410 @ 1200P_0402_50V7K 2
LINE_C_OUTR 1 LINE_C_R_OUTR C1044 2
<32> LINE_OUTR 1 2 2 5 INR BIAS 2 1 2 1U_0603_10V4Z
U27A

8
0.1U_0402_16V4Z 10K_0402_5% R1405 VDDA_CODEC
1 2 LINE_C_R_OUTR L57 TLV2462_SO8
15K_0402_5% 10 dB HLC0603CSCCR11JT_0603 3

P
C502 R1411 R_SPK+ R196 R193 C231 R388 + INT_MIC
OUTR+ 7 O 1
<32> LINE_OUTL 1 2 LINE_C_OUTL 1 2 LINE_C_R_OUTL 1 1 2INT_MIC_1 1 2 1 2INT_MIC_3
1 2 1 2 INT_MIC_4 2
INL -

G
9 R_SPK- 3K_0402_5% 1
0.1U_0402_16V4Z 10K_0402_5% OUTR- 3K_0402_5% 1 C226 0.22U_0603_10V7K C571 10K_0402_5%

4
10 dB R1406 1 2 LINE_C_R_OUTL INT_MIC <32>
R1407 15K_0402_5% 10 dB 68P_0402_50V8J
L_SPK+ 4.7U_0805_10V4Z 2
2 1 4 MUTE OUTL+ 19
0_0402_5% 2
17 L_SPK-
OUTL-

3 C488
NC1
10 1 2
<26,29,32,37,39,40,47,48,49,50,51,52> SLP_S3# R430 1 2 10K_0402_5% 14 SHDN
NC2
NC3 13
16
C471
0.01U_0402_16V7K
AMP. FOR EXTERNAL MICROPHONE 100P_0402_50V8J

PGND1
PGND2
PGND3
PGND4
PGND5
NC4 R413
MUTE_LED# 1 2
2 1 1 2
1

R1421 @ 0_0402_5% D
MAX9710ETP_QFN20 JJ_MIC_REF J_VDDA_CODEC 100K_0402_5%
<32,37> EAPD 2

6
11
15
20
21
G
Q28 S
Place close to JP15
3

100P_0402_50V8J
@ RHU002N06_SOT323
1
1

C249
2 2
<37> A_SD 2
G
Q32 S 2 U46A
3

RHU002N06_SOT323 MIC_REF

8
TLV2462_SO8
VDDA_CODEC VDDA_CODEC
3

P
+
1 C982 C276 L58 R211
O 1 J_MIC1
EXT_MICA 1 2 EXT_MICA_1 1 2 1 2 EXT_MICA_2 2 -
1

G
HLC0603CSCCR10JT_0603
Place close to U14 audio CODEC R426 4.7U_0805_10V4Z 0.22U_0603_10V7K 1 C57210K_0402_5%

4
R978 2
VDDA_CODEC 47K_0402_5% 100_0402_5%

8
68P_0402_50V8J
2

1
1

J_VDDA_CODEC 2
5
P
R995 + C489
O 7
1

100K_0402_5% 2 6 1 2
-
G

1
C493 R428 U27B
TLV2462_SO8 conn@ R427 100P_0402_50V8J
1 2

<32> PORT_A_SNS Q48 47K_0402_5% JP9 R414

D RHU002N06_SOT323 4.7U_0805_10V4Z 1 MIC1 47K_0402_5%
1 1 2 1 JJ_MIC_REF 1 2
2

<32> MIC1 R1424 0_0402_5%

2 2 2

2
G MIC2 JJ_MIC_REF J_VDDA_CODEC 100K_0402_5%
<32> MIC2 3 3
S 4 4
3

1
VDDA_CODEC 5 5 2 1
<32> SENSE_A_A MIC_REF 2 J_MIC_REF

100P_0402_50V8J
MIC_SENSE 6 6 C492 R429 R1423 @ 0_0402_5%
1

D R_HP
<32> R_HP 7 7 1
1

VDDA_CODEC

C248
2 <32> L_HP L_HP 8 8 47K_0402_5%
Q49 G R423 9 9 4.7U_0805_10V4Z 1

2
RHU002N06_SOT323 S 10 10
3

<39> DLINE_OUT_L
1

100K_0402_5% 2 U46B
<39> DLINE_OUT_R 11 11
R251 VDDA_CODEC 12 12
2

8
TLV2462_SO8
3 <39> DOCK_HPS# 100K_0402_5% ACES_87213-1200 3
5

P
+
1

D R255 C275 L61 R210 J_MIC2

7
2

Q44 DLINE_OUT_L EXT_MICB EXT_MICB_1 1 EXT_MICB_2 O

1 2 1 2 1 2 2 1 2 6 -

G
C527 G 1 1 HLC0603CSCCR10JT_0603 1
S C536 100K_0402_5% @C526
@C526 0.22U_0603_10V7K 1 10K_0402_5% C470
3

4
0.1U_0603_50V4Z
2 2.2U_0603_6.3V4Z 1U_0603_10V4Z C575 0.1U_0402_16V4Z
2 2 68P_0402_50V8J 2
RHU002N06_SOT323 2

VDDA_CODEC
R261 CHB1608B121_0603
JP24

2
1 2 R_CR_HP 1 2 R_CRL_HP
<32> HP_R_JACK 60.4_0805_1% L52 R979
5 8 <32> SENSE_A_B
J_DLINE_OUT_R 7 47K_0402_5%
J_DLINE_OUT_L 4

1
D

1
R253 L51 3 Q50 2 MIC_SENSE
1 2 L_CR_HP 1 2 6 RHU002N06_SOT323 G 2
150U_D_6.3VM <32> HP_L_JACK 60.4_0805_1% CHB1608B121_0603 L_CRL_HP 2 S
J_R_HP 1 3 C984
+

2 R_C_HP <32> 1 JP15

C577 Place close to JP24 0.1U_0402_16V4Z
J_L_HP 1 J_MIC_SENSE
+

1 2 L_C_HP <32> 1 1 5 8
1

C581 C563 C564 SUYIN_010030FR006G101ZL_6P R424 7

150U_D_6.3VM R445 R446 conn@ R418 3.9K_0402_1% 4
470P_0402_50V7K 470P_0402_50V7K J_VDDA_CODEC 1 2 1 2 EXT_MICB 1 2
U73 1K_0402_1% 1K_0402_1% 2 2 470_0402_5% L46
Place close to U14 3
1 6 CHB1608B121_0603 6
2

CH1 CH4 EXT_MICA

1 2 1 2 1 2 2
2 5 +3VS R425 L47 1
Vn Vp 470_0402_5% R421 CHB1608B121_0603 1 1
4 conn@ JP27 3.9K_0402_1% C508 C522 4
3 CH2 CH3 4
J_MIC1 SUYIN_010030FR006G101ZL_6P
@ S DIO(BR) NUP4301MR6T1 TSOP-6 1 1
2
Place close to JP24 C487
1 1
C486 470P_0402_50V7K 470P_0402_50V7K conn@
2 J_MIC2 2 2
3 3
JP21 conn@ 4 10U_0805_10V4Z 10U_0805_10V4Z
L_SPK+ 4 conn@ JP28 2 2
1 1 5 5 J_MIC_REF
L_SPK- 2 6 J_MIC_SENSE 1 J_R_HP
R_SPK+ 2 6 1 J_L_HP
3 2
R_SPK- 100P_0402_50V8J 4
3
4
ACES_87213-0600 2
3 3
J_DLINE_OUT_L
Security Classification Compal Secret Data Compal Electronics, Inc.
1 1 1 1 4 4 Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title
C506 C514 C507 C518 E&T_3801-04 Place close to JP15 5 J_DLINE_OUT_R
5
6 6 J_VDDA_CODEC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMP & Audio Jack
100P_0402_50V8J 100P_0402_50V8J AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2 2 2 2 ACES_87213-0600 1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64
100P_0402_50V8J MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 33 of 57
A B C D E
 5 4 3 2 1

Left side USB CONNECTOR 1

Left side USB CONNECTOR 0

+5VALW USB_VCCA USB_VCCA

U57

1 8 W=100mils JP23 conn@ conn@JP25

conn@ JP25
GND OUT 0_0603_5% R604 0_0603_5% R606
2 IN OUT 7 1 1 1 1

1000P_0402_50V7K
150U_D_6.3VM
D D

0.1U_0402_16V4Z
3 6 1 USB20_N4 1 2USB20_N4_R 2 2 USB20_N5_R 1 2USB20_N5 USB20_N5 <26>
IN OUT <26> USB20_N4 USB20_P4 1 2 2
1 4 EN# OC# 5 1 1 <26> USB20_P4 2USB20_P4_R 3 3 3 3 USB20_P5_R 1 2USB20_P5 USB20_P5 <26>

C567
+

C515

C519
C550 0_0603_5% R605 4 4 0_0603_5% R607
4 4
5 GND GND 5
4.7U_0805_10V4Z G548A2P1U 6 6
2 2 2 2 GND GND
7 GND GND 7
2 1 8 GND GND 8 2 1

0_0805_5% SUYIN_020173MR004S558ZL R4 USB20_P5

S4_STATE R73 SUYIN_020173MR004S558ZL 0_0805_5% USB20_N5
USB20_P4 0904 change for EMI
1 2 +5VALW USB20_N4

2
R163
10K_0402_5% 0904 change for EMI

2
D51
2 1 PJDLC05_SOT23~D
D52 R56
PJDLC05_SOT23~D

1
0_0805_5%

1
Right side USB CONNECTOR 0
+5VALW
1394 connector 11/06 fix DB2 1394 can not detect issue
USB_VCCC
U65
1 8 W=60mils JP26 conn@
C GND OUT 0_0603_5% R617 C
2 IN OUT 7 1 1
1000P_0402_50V7K
150U_D_6.3VM

0.1U_0402_16V4Z

3 IN OUT 6 1 <26> USB20_N0 1 2USB20_N0_R 2 2

1 4 EN# OC# 5 1 1 <26> USB20_P0 1 2USB20_P0_R 3 3 2007,0125 change
C569

+
C517

C558 0_0603_5% R614 4 4

C521

TPS2061IDGN_MSOP8~N 5 conn@
4.7U_0805_10V4Z GND
6 JP19
2 2 2 2 GND XTPB0- 0_0402_5% R1697 R_XTPB0-
7 GND <31> XTPB0- 1 2 1 XTPB0-
8 XTPB0+ 0_0402_5% 1 2 R1696 R_XTPB0+ 2
GND <31> XTPB0+ XTPA0- 0_0402_5% R1699 R_XTPA0- XTPB0+
<31> XTPA0- 1 2 3 XTPA0-
SUYIN_020173MR004S558ZL XTPA0+ 0_0402_5% 1 2 R1698 R_XTPA0+ 4
<31> XTPA0+ XTPA0+
5 GND
+5VALW 6 GND
1 2 +5VALW 7 GND
R164 USB20_P0 8 GND
1

10K_0402_5% USB20_N0
AMP_440168-2

2
10K_0402_5%
2

<36> S4_STATE S4_STATE R1 D61

PJDLC05_SOT23~D
1

<26> S4_STATE# 2

1
G
Q132 S conn@ JP22
3

RHU002N06_SOT323 +3VAUX_BT
1 R562
2 USB20_P6_R
3 2 1 0_0402_5% USB20_P6
USB20_P6 <26>
USB20_N6_R 2 1 0_0402_5% USB20_N6
4 USB20_N6 <26>
R586
5 BT_LED <36>
@ R458 1
@R458 2 1K_0402_5%
6 @R459
@ R459 1 1K_0402_5% CH_DATA <31>
7 2 CH_CLK <31>
B B
8

2
ACES_87212-0800 D53

@ PACDN042_SOT23~D

SMART Card connector +SC_PWR

1
BT Connector
JP3 conn@ 1
1 C367 +3VALW +3VAUX_BT
1 11 11 SC_CLK Q51 SI2301BDS_SOT23
2 2 12 12 SC_CLK <31>
3 SC_RST 0.1U_0402_16V4Z
3 13 13 SC_RST <31> 2

D
4 4 14 14 +SC_PWR 3 1
5 SC_CD#
5 15 15 SC_CD# <31>
6 6 16 16

G
7 17 17 1 1 1 1

2
7 C306 R518 C546 C545 C549
8 8 18 18
9 SC_DATA 4.7U_0805_10V4Z
9 19 19 SC_DATA <31>
1U_0603_10V4Z 100K_0402_5% 0.1U_0402_16V4Z
10 10 20 20 2 2 2 2

2
ACES_85203-1002
0.01U_0402_16V7K
C556
R454
<26> BT_OFF 1 2 1 2
47K_0402_5%
0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB & BT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 34 of 57
5 4 3 2 1
 A B C D E

1 1
+3VS
RP3
DCD#1 1 8
RI#1 2 7
CTS#1 3 6
DSR#1 4 5
+5VS
4.7K_1206_8P4R_5%

2
IRRX 1 2
R76 D36
1K_0402_5%
CH751H-40_SC76

1
+5VS_PRN

RXD1 <39>
RP51
U8 R64 1K_0402_5% LPD3 1 8
<25,36,37> LPC_AD0 LPC_AD0 10 62 RXD1 1 2 LPD2 2 7
LPC_AD1 LAD0 RXD1 TXD1 LPD1
12 63 3 6

SERIAL I/F
<25,36,37> LPC_AD1 LAD1 TXD1 TXD1 <39>
<25,36,37> LPC_AD2 LPC_AD2 13 64 DSR#1 LPD0 4 5
LAD2 DSR1# DSR#1 <39>
<25,36,37> LPC_AD3 LPC_AD3 14 1 RTS#1
LAD3 RTS1# RTS#1 <39>
2 CTS#1 4.7K_1206_8P4R_5%
RP6 CTS1# CTS#1 <39>
<25,36,37> LPC_FRAME# LPC_FRAME# 15 3 DTR#1
LFRAME# DTR1# DTR#1 <39>
8 1 SIO_GPIO12 LPC_DRQ#0 16 4 RI#1 RP52
<25> LPC_DRQ#0 LDRQ# RI1# RI#1 <39>

LPC I/F
7 2 SIO_GPIO10 R108 1 2 0_0402_5% 5 DCD#1 LPD7 1 8
<26,37> NPCI_RST# DCD1# DCD#1 <39>
6 3 SIO_GPIO44 R109 1 2 @ 0_0402_5% SIO_RST# 17 LPD6 2 7
<28,31,36> PLT_RST_B# PCI_RESET#
5 4 SIO_GPIO43 +3VS R99 1 2 10K_0402_5% SIO_PD# 18 37 IRRX LPD5 3 6
LPCPD# IRRX2 IRRX <31>
FIR 38 LPD4 4 5
2 IRTX2 IRTXOUT <31> 2
10K_1206_8P4R_5% PM_CLKRUN# 19 39
<26,31,36,37> PM_CLKRUN# CLKRUN# IRMODE/IRRX3 IRMODE <31>
R120 CLK_PCI_SIO 20 4.7K_1206_8P4R_5%
<15> CLK_PCI_SIO PCI_CLK
1 2 SIO_IRQ SIRQ 21 41 LPTINIT#
R121 10K_0402_5% <26,31,36,37> SIRQ SIO_PME# SER_IRQ INIT# LPTSLCTIN# LPTINIT# <39> RP53
+3VS 1 2 6 IO_PME# SLCTIN# 42 LPTSLCTIN# <39>
1 2 SIO_DPIO45 R67 10K_0402_5% 44 LPD0 LPTACK# 1 8
PD0 LPD0 <39>
10K_0402_5% CLK_14M_SIO 9 46 LPD1 LPTBUSY 2 7
<15> CLK_14M_SIO CLK14 PD1 LPD1 <39>
CLOCK 47 LPD2 LPTPE 3 6
PD2 LPD2 <39>
SIO_GPIO40 23 48 LPD3 LPTSLCT 4 5
GPIO40 PD3 LPD3 <39>

PARALLEL I/F
PID0 24 49 LPD4
+3VS GPIO41 PD4 LPD4 <39>
PID1 25 50 LPD5 4.7K_1206_8P4R_5%
GPIO42 PD5 LPD5 <39>
R119 SIO_GPIO43 27 51 LPD6
GPIO43 PD6 LPD6 <39>
CARD_ID# SIO_GPIO44 LPD7 RP54

GPIO
1 2 28 GPIO44 PD7 53 LPD7 <39>
SIO_DPIO45 29 55 LPTSLCT 1 8
GPIO45 SLCT LPTSLCT <39>
10K_0402_5% CARD_ID# 30 56 LPTPE LPTSTB# 2 7
GPIO46 PE LPTPE <39>
SER_SHD 31 57 LPTBUSY LPTAFD# 3 6
<39> SER_SHD GPIO47 BUSY LPTBUSY <39>
SIO_GPIO10 32 58 LPTACK# LPTERR# 4 5
GPIO10 ACK# LPTACK# <39>
SIO_GPIO11 33 59 LPTERR#
SIO_GPIO12 GPIO11/SYSOPT ERROR# LPTAFD# LPTERR# <39> 4.7K_1206_8P4R_5%
34 GPIO12/IO_SMI# ALF# 60 LPTAFD# <39>
SIO_IRQ 35 61 LPTSTB#
GPIO13/IRQIN1 STROBE# LPTSTB# <39>
R68 36 R480
EXPCRD_RST# EXPCRD_RST# GPIO14/IRQIN2 LPTSLCTIN#
1 2 40 GPIO23 1 2
<39> EXPCRD_RST#
10K_0402_5% 8 7 +3VS 4.7K_0402_5%
+3VS VSS VTR R481
22 VSS VCC 11
R77 43 POWER 26 LPTINIT# 1 2
PID0 VSS VCC
1 2 52 VSS VCC 45
54 1 1 1 1 4.7K_0402_5%
10K_0402_5% VCC C84 C88 C76 C57
LPC47N217_STQFP64

R79 Base I/O Address 2 2 2 2

1 2 PID1 0 = 02Eh
3 * 1 = 04Eh 3
10K_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 4.7U_0805_10V4Z

R80
1 2 SIO_GPIO11

10K_0402_5%

R100
1 2 SIO_GPIO40

10K_0402_5% CLK_PCI_SIO CLK_14M_SIO

1
R96 R81
@ 10_0402_5% @ 10_0402_5%
2

2
1 1
C94 C70
@18P_0402_50V8J @10P_0402_25V8K
2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SUPER I/O LPC47N217
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 35 of 57
A B C D E
 5 4 3 2 1

BIOS ROM 20mils

Debug port JP52
R1945 0_0402_5% 1
U66 Ground
<15,31> CLK_DEBUG_PORT 2 LPC_PCI_CLK
2007,0125 change +3VM 2 1 1 8 VCC VSS 4 3 Ground
@ R118 0_0402_5% 4
<25,35,37> LPC_FRAME# LPC_FRAME#
SPI_WP# 3 +3VS 1 2 5
C989 W @ R123 0_0402_5% +V3S
<7,24,28> PLT_RST# 6 LPC_RESET#
0.1U_0402_16V4Z 2 SPI_HOLD#_0 7 HOLD 1 2 7 +V3S
<25,35,37>
LPC_AD0 8 LPC_AD0
SPI_CS0# 1 9
D <26> SPI_CS0# S <25,35,37>
LPC_AD1 LPC_AD1 D
47_0402_5% 10
<25,35,37>
LPC_AD2 LPC_AD2
SPI_CLK 1 2 R1290 SPI_CLK_0 6 11
C <25,35,37>
LPC_AD3 LPC_AD3
47_0402_5% R1291 B+ 12
SPI_SI VCC_3VA
1 2 R1294 SPI_SI_0 5 D Q 2 SPI_SO_L01 2 SPI_SO SPI_SO <26> <37> STB_LED# 13 PWR_LED#
15_0402_5% 14
<37> CAPS_LED# CAPS_LED#
<37> NUM_LED# 15 NUM_LED#
WIESO_G6179-100000_8P 16
20mils R1288 <37,41> VCC1_PWRGD VCC1_PWRGD
SPI_CLK_L 1 2 SPICLK 17
+3VM 1 2 SPI_HOLD#_0
3.3K_0402_5%
SPI0 (16M*1) R1794 0_0402_5%
SPI_CS0#
SPI_SI_L
2
1
1 SPICS0#
2SPISI
18
19
SPI_CLK
SPI_CS#
SPI_SI

1
SPI_SO_L 1 2SPISO 20
R1924 SPI_SI_L SPI_SI SPI_HOLD#_0 SPI_SO
2 1 SPI_SI <26> 21 SPI_HOLD#
0_0402_5% R170 0_0402_5% SPI_CS1# 22
CLRP3 SHORT PADS Reserved
23 Reserved
+3VM +3VM R1795 0_0402_5% R201 0_0402_5% 24

2
R202 0_0402_5% Reserved
1

1 20mils SPI_CLK_L 2 1 SPI_CLK SPI_CLK <26>

R1287 C993 U67

SPI_SO_L
3.3K_0402_5% 8 4 ACES_87216-2404_24P
0.1U_0402_16V4Z VCC VSS conn@
2 0907 Add 0 ohm for SPI
SPI_WP# 3
2

SPI_WP# W
SPI_HOLD#_0 7 HOLD
1

0629 Change Pin3 to Pin23, change Pin24 to GND

@R1724
@ R1724 SPI_CS1# 1
<26> SPI_CS1# S
0_0402_5% @ 47_0402_5%
SPI_CLK_L 1 2 R1296 SPI_CLK_1 6
@ 47_0402_5% C @ R1297
2

SPI_SI_L 1 2 R1295 SPI_SI_1 5 SPI_SO_L11

2 2
D Q 15_0402_5%
@ SST25LF080A_SO8-200mil

C C
SPI1 (16M*1) 0821 SPI1 no install
0906 SPI1 install

+3VS

Q75
47K

3
DTA114YKA_SC59
Mini-PCIE Card LED
TPM1.2 10K 2 WW_LED# <31>
+3VS+3VALW

0.1U_0402_16V4Z
1 1 1 1
+3VS BLUE
C1053 C1054 C1055 C1052

1
Base I/O Address 47K

3
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0 = 02Eh +3VS
2 2 2 2 * 1 = 04Eh
0.1U_0402_16V4Z
24
19
10

U69 10K 2 WL_LED# <31>

R1377
VSB
VDD
VDD
VDD

Q88
4.7K_0402_5% DTA114YKA_SC59
LPC_AD0 26 28 LPC_PD# Q79 WL_BLUE_LED# <31,38>
<25,35,37> LPC_AD0 LPC_PD# <26>
2

LPC_AD1 LAD0 LPCPD# +3VS RHU002N06_SOT323

<25,35,37> LPC_AD1 23 9

1
LAD1 TESTB1/BADD

1
LPC_AD2 R1379 2 0_0402_5% D
<25,35,37> LPC_AD2 20 LAD2 TEST1 8 1
1

LPC_AD3 17 R1378 2
<25,35,37> LPC_AD3 LAD3 47K <34> BT_LED

3
B TPM_XTALO @ 4.7K_0402_5% G B
XTALO 14
13 TPM_XTALI 1 2 S
TPM_32K_CLK <37>

3
XTALI

2
TPM R101 @ 0_0402_5%
CLK_PCI_TCG 21 SLB 9635 TT 1.1 PAD 10K 2 R505
<15> CLK_PCI_TCG WP_LED# <31>
2

LPC_FRAME# LCLK T41 100K_0402_5%

<25,35,37> LPC_FRAME# 22 LFRAME# GPIO2 2
PLT_RST_B# 16 6
<28,31,35> PLT_RST_B# LRESET# GPIO
SIRQ 27 T42 18P_0402_50V8J
<26,31,35,37> SIRQ

1
PM_CLKRUN# SERIRQ PAD TPM_XTALI C1057 1 Q89 @
<26,31,35,37> PM_CLKRUN# 15 CLKRUN# 2
+3VS 1 2 7 1 DTA114YKA_SC59

1
PP NC
1

R1380 3 32.768KHZ_12.5P_1TJS125BJ2A251
NC

1
@ 4.7K_0402_5% R1381 D
12 1 NC 2
GND
GND
GND
GND

NC IN
1

WL_LED 2 Q78
R1409 4 3 G RHU002N06_SOT323
SLB9635TT_TSSOP28 OUT NC
S
4
11
18
25

3
2
0_0402_5% Y8
TPM_XTALO C1056 1 2 R504
2

10M_0402_5% 100K_0402_5%
18P_0402_50V8J

1
Finger printer +3V_FP

+3VS
1
C206
1

0.1U_0402_16V4Z
2 R1941
JP38 SI2301BDS_SOT23
0_0402_5% 1 10K_0402_5%
A R1334 1 +3VALW A
<26> USB20_N1 2 1 USB20_N1_R 2 Q145 @
2

2
<26> USB20_P1
R1335 2 1USB20_P1_R 3 3
S

0_0402_5%
D

4 4 3 1 +3V_FP
3

ACES_85205-0400
G

conn@
2

D54
S4_STATE <34>
@ PACDN042_SOT23~D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TCG/BIOS ROM/PS2/LED/SW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 36 of 57
5 4 3 2 1
 5 4 3 2 1

2/22 change 0_0402_5% +3VL

2 1 PWR_GD
1070@ +3VL 1021@ R1642 RP1
+3VL 2 1 PWR1 R1646 CRACK_BGA 1 2 AB1A_CLK 1 8
CRACK_GPIO28 <11,27>
0_0603_5% R1477 1 2 1 +3VS 0_0402_5% R1726 AB1A_DATA 2 7
C39 1 1070@ 0_0402_5% AB1B_CLK 3 6
+3VS 2 1 T32 T33 AB1B_DATA 4 5
0_0603_5% R1478 0.1U_0402_16V4Z 0.1U_0402_16V4Z C75 PAD PAD
1021@ 2 1070@ 4.7K_1206_8P4R_5%
1 1 1 1 1 2
C37 C51 C36 C34
C52 PM_SLP_M#
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z PM_SLP_M# <26,40,47,48,52>
2 2 2 2 2 GPIO29 <26>
1 2 EAPD <32,33>
+3VL R38 0_0402_5%
GPIO30 R141 1 2 0_0402_5%
D PWR1 1
AMT ADP_PRES <26> BIOS debug port D
RP58
1 8 KSI0
PCI_SERR# <24,31>
1070@ +3VL Place under KB area

127
128

106

119

100
126
KSI3 10U_0805_10V4Z C1289

94
95
96
97

39
58
84

14

49

15

93
98
99
2 7
KSI2 U47 2 +3VL
3 6

1
4 5 KSI1 KSO[0..13]

CAP
NC
NC
NC
NC
NC
NC

VCC1
VCC1
VCC1
VCC1
VCC1

VCC1

VCC2

GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
<38> KSO[0..13]
R575 JP43
10K_1206_8P4R_5% KSO0 21 124 KBC_PWR_ON
KSO0 OUT0 KBC_PWR_ON <46> 1
KSO1 20 125 GREEN_BATLED# 10K_0402_5% VCC1_PWRGD
RP59 KSO2 KSO1 OUT1/IRQ8# GREEN_BATLED# <25,31> 2
19

2
KSI7 KSO3 KSO2 BATSELB_A# D7 EC_GPIO9 3
1 8 18 KSO3 OUT7/SMI# 123 BATSELB_A# <45> 4
2 7 KSI6 KSO4 17 122 KBRST# 1 2 CRACK_BGA
KSI5 KSO5 KSO4 OUT8/KBRST A_SD KB_RST# <25> 5
3 6 16 KSO5 OUT9/PWM2 121 A_SD <33> 6

Keyboard/Mouse Interface
4 5 KSI4 KSO6 13 120 FAN_PWM CH751H-40_SC76

General Purpose I/O Interface

KSO7 KSO6 OUT10/PWM0 CHGCTRL FAN_PWM <4> @ ACES_85201-0602
12 KSO7 OUT11/PWM1 118 CHGCTRL <44,45>
10K_1206_8P4R_5% KSO8 10
KSO9 KSO8 THM_MBAY#
9 KSO9 GPIO01 107 THM_MBAY# <43>
KSO10 8 79 ON/OFFBTN_KBC# ON/OFFBTN_KBC# <38>
KSO11 KSO10 GPIO02 LOW_BAT#
7 KSO11 GPIO03 80 LOW_BAT# <26>
Pin3 250 : KSO12/OUT8/KBRST KSO12 6 81 KSO14 +3VL
KSO12/GPIO00/KBRST GPIO04/KSO14 KSO14 <38>
KSO13 5 83 KSO15 KSO15 <38>
+5VS KSO13/GPIO18 GPIO05/KSO15 THM_MAIN# 1 R600
<38> KSI[0..7] RSMRST_EC <26> 2
85 RSMRST_EC 210K_0402_1%
R578 KSI0 GPIO07/PWM3 CRACK_BGA 4.7K_0402_5% R20 1 ADP_PS1
29 KSI0 GPIO08/RXD 86 2 1 2
1 2 TP_CLK KSI1 28 87 EC_GPIO9 4.7K_0402_5% R18 1 2 +3VL R538 @ 100K_0402_5%
KSI2 KSI1 GPIO09/TXD EC_GPIO27 1 R33
27 KSI2 2
10K_0402_5% KSI3 26 88 AB2A_DATA R156 1 2 0_0402_5% Cap_DAT <38> 100K_0402_5%
R580 KSI4 KSI3 GPIO11/AB2A_DATA AB2A_CLK R155
25 KSI4 GPIO12/AB2A_CLK 89 1 2 0_0402_5% Cap_CLK <38>
1 2 TP_DATA KSI5 24 KSI5 GPIO13/AB2B_DATA 90 AB2B_DATA R140 1 2 0_0402_5% ME_EC_DATA1 <26>

SMSC_1070_TQFP-128P
KSI6 23 91 AB2B_CLK R154 1 2 0_0402_5% ME_EC_CLK1 <26>
10K_0402_5% KSI7 KSI6 GPIO14/AB2B_CLK BATCON
22 KSI7 GPIO15/FAN_TACH1 92 BATCON <45> R282 C92
101 THM_MAIN# D6 CH751H-40_SC76
C RP60 GPIO16/FAN_TACH2 THM_MAIN# <43> C
102 A20M 1 2 CLK_14M_KBC 1 2 1 2
KBD_CLK TP_CLK GPIO17/A20M R581 1 GATEA20 <25>
1 8 <38> TP_CLK 35 IMCLK 2 +3VL
2 7 KBD_DATA TP_DATA 36 103 NUM_LED# 10K_0402_5%
<38> TP_DATA IMDAT GPIO20/PS2CLK NUM_LED# <36> 10_0402_5% 10P_0402_25V8K
3 6 PS2_CLK KBD_CLK 38 105 SLP_S3#
<39> KBD_CLK KCLK GPIO21/PS2DAT SLP_S3# <26,29,32,33,39,40,47,48,49,50,51,52> @ @
4 5 PS2_DATA KBD_DATA 40 4 T37 PAD
<39> KBD_DATA KDAT GPIO24/KSO16
PS2_CLK 41 74 EC_GPIO27 2 1 Pin1 250 -- TEST Pin ( NC !! )
<39> PS2_CLK EMCLK GPIO27 ADP_PRES <29,44,45,46,50> Pin57 250 -- MODE
10K_1206_8P4R_5% PS2_DATA 42
<39> PS2_DATA EMDAT D10 CH751H-40_SC76
R25
111 AB1A_DATA AB1A_DATA <43> FWP# 1 2 PM_POK
AB1A_DATA AB1A_CLK
AB1A_CLK 112 AB1A_CLK <43>
Access Bus Interface 10K_0402_5%
+3VS PM_CLKRUN# 55 109 AB1B_DATA
<26,31,35,36> PM_CLKRUN# CLKRUN# AB1B_DATA AB1B_DATA <43>
SIRQ 57 110 AB1B_CLK
<26,31,35,36> SIRQ SER_IRQ Power Mgmt/SIRQ AB1B_CLK AB1B_CLK <43>
CLK_PCI_EC 54
<15> CLK_PCI_EC PCI_CLK
RUNSCI_EC# 76 73 Cap_INT
<26> RUNSCI_EC# EC_SCI# PGM Strap/GPIO25 Cap_INT <38>
108 EA#
R1289 LPC_AD3 EA Strap#/GPIO26/KSO17 CLK_14M_KBC
<25,35,36> LPC_AD3 51 LAD[3] CLOCKI 59 CLK_14M_KBC <15>
1 2RUNSCI_EC# LPC_AD2 50 75 32K_CLK

Miscellaneous
<25,35,36> LPC_AD2 LAD[2] 32KHZ_OUT/GPIO22
LPC_AD1 48 60 PM_POK
<25,35,36> LPC_AD1 LAD[1] RESET_OUT#/GPIO06 PM_POK <49>
10K_0402_5% LPC_AD0 46 LPC 78 PWR_GD
<25,35,36> LPC_AD0 LAD[0] PWRGD PWR_GD <21,26,31,40,41,49,50>
77 VCC1_PWRGD
LPC_FRAME# 52
Bus VCC1_PWRGD
61
VCC1_PWRGD <36,41>
<25,35,36> LPC_FRAME# LFRAME# 24MHZ_OUT/GPIO19/WINDMON Pin50 250 -- 24MHz_Out ADP_PS0 <50>
<26,35> NPCI_RST# 53 LRESET#
45 69 TEST 1 2 +3VL
<50> ADP_PS1 LPCPD#/GPIO23 TEST PIN Pin52 250 -- XOSEL R977 300_0402_5% JP31
Pin91 250 -- nDMS_LED
CRY1 VCC1_PWRGD 1
70 XTAL1 DMS_LED#/GPIO10 116 ADP_ID <50> 2
1 2 CRY2 71 113 AMBER_BATLED# +3VL R58 1 2 100K_0402_5% NUM_LED#
XTAL2 BAT_LED# AMBER_BATLED# <31> 3
CLK_PCI_EC 115 STB_LED# R59 1 2 100K_0402_5% STB_LED#
PWR_LED#/8051TX STB_LED# <36> 4
R74 120K_0402_5% 114 CAPS_LED# R60 1 2 100K_0402_5% CAPS_LED#
FDD_LED#/8051RX CAPS_LED# <36> 5
1

B @ 2M_0402_5% R75 B
68 VCC0 6
AGND

R86 2 1 R62 250@

VSS
VSS
VSS
VSS
VSS
VSS
VSS
@R1925
@ R1925 0_0402_5%
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC
NC
@ 10_0402_5% 1 2 Remove from daughter board @ ACES_85201-0602
+RTCVCC
KBC1070_VTQFP128
2

1
2
3
30
31
32
33
34
43
44

72

11
37
47
56
104
82
117

62
63
64
65
66
67
1

0_0402_5%
2
C80 Y2 1 2
For KBC debugging used.
IN

OUT

+3VL
1 1 @ R1926
@ 10P_0402_50V8J 18P_0402_50V8J 18P_0402_50V8J 1 2
1 C350 C349 0_0402_5% 2 1
R1942 C1317
NC

NC

2 2
1U_0603_10V4Z 0.1U_0402_16V4Z
2

C661 1 2

32.768KHZ_12.5P_1TJS125BJ2A251

AGND FILTER U87

11/20 for solve PM_PWROK glitch on power up

C58 R29 STB_LED# 1 6 LED_STB# <31,38,39>

FWP# A1 Y1 +3VALW
1 2 1 2

0.1U_0402_16V4Z 100K_0402_5% 2 5 +3VL U89

GND VCC

5
0_0402_5%
<21,26,31,40,41,49,50> PWR_GD 1 R1810

P
IN1
3 4 4
A2 Y2
<49> PGOOD_PU19 2
O PM_PWROK <26>
IN2

G
A NC7WZ07P6X_NL_SC70-6 VGATE <7,26> A

3
+3VL SN74AHC1G08DCKR_SC70
R28
FWP# 2 1
32K_CLK R91 1 2 0_0402_5% @ 1K_0402_5%
ADP_EN <50>
R97 1 2 @ 0_0402_5% TPM_32K_CLK <36>
TEST
R78 Security Classification Compal Secret Data Compal Electronics, Inc.
2 1 Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title
@ 1K_0402_5%
R27 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LPC47N1021
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
EA# 2 1 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
1K_0402_5% MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 37 of 57
5 4 3 2 1
 SWITCH BOARD. 0622 change 220P_0402_50V4Z
2
220P_0402_50V4Z
1
C749

C750
LED_STB#
INT_KBD CONN.
2 1 ON/OFF#
@ R21 0_0402_5%
Cap_RST# 1 2 KSO[0..15]
Cap_RST#_SB <26> <37> KSO[0..15]
KSI[0..7]
<37> KSI[0..7]
Cap_INT 2007,0125 change JP6
30 30 60 A30

1
0901 Change Cap_RST#_SB to SB GPIO28 1 29 29 59 A29
R30 28 A28
10K_0402_5% C1 28 58
+3VALW 27 27 57 A27
10P_0402_50V8K @JP20
@ JP20 26 A26
2 LID_SW# 26 56
@ 9 9 1 LID_SW# <17,26> 25 A25

2
1 KSO15 25 55 KSO15
10 10 2 2 24 24 54 A24
11 11 3 LED_STB# KSO10 23 A23 KSO10
+3VL +3VS 3 LED_STB# <31,37,39> 23 53
12 12 4 ON/OFF# KSO11 22 A22 KSO11
4 KSO14 22 52 KSO14
13 13 5 5 21 21 51 A21
14 14 6 ON/OFF# LID_SW# KSO13 20 A20 KSO13
JP18 6 KSO12 20 50 KSO12
15 15 7 7 19 19 49 A19
16 16 8 KSO3 18 A18 KSO3
1 2 8 18 48

2
Cap_RST# KSO6 17 A17 KSO6
3 4 Cap_CLK <37> 17 47
<37> Cap_DAT Aces_85203-08421-11 KSO8 16 A16 KSO8
5 6 Cap_INT <37> 16 46
WL_BLUE_LED# <31,36> @ D81 KSO7 15 A15 KSO7
7 8 KSO4 15 45 KSO4
9 10 14 14 44 A14
KSO2 13 A13 KSO2
ACES_85203-1002 PJDLC05_SOT23~D KSI0 13 43 KSI0
12 A12

1
KSO1 12 42 KSO1
conn@ 0829 Change to WL_BLUE_LED# 11 11 41 A11
KSO5 10 A10 KSO5
KSI3 10 40 KSI3
9 9 39 A9
KSI2 8 A8 KSI2
KSO0 8 38 KSO0
7 A7
WL,Vol up,Vol down,Mute,Present button On/off ,information button KSI5 6
7
6
37
36 A6 KSI5
KSI4 5 A5 KSI4
KSO9 5 35 KSO9
4 4 34 A4
KSI6 3 A3 KSI6
KSI7 3 33 KSI7
2 2 32 A2
+3VS KSI1 1 A1 KSI1
1 31

conn@
0.1U_0402_16V4Z 1 FOX_GB1SV301-160K-7F

MDC 1.5 Conn. 11/06 follow UMA SI-2 design change

2
C5
CP1 CP6
KSO9 4 5 KSO2 4 5
JP32 +3VS KSI6 3 6 KSO4 3 6
KSI7 2 7 KSO7 2 7
1 2 KSI1 1 8 KSO8 1 8
HDA_SDOUT_MDC GND1 RES0
<25> HDA_SDOUT_MDC 3 IAC_SDATA_OUT RES1 4
5 6 100P_1206_8P4C_50V8 100P_1206_8P4C_50V8
R1313 HDA_SYNC_MDC GND2 3.3V
<25> HDA_SYNC_MDC 7 IAC_SYNC GND3 8
<25> HDA_SDIN1 2 1HDA_SDIN1_MDC 9 IAC_SDATA_IN GND4 10 CP3 CP5
33_0402_5% 11 12 HDA_BITCLK_MDC HDA_BITCLK_MDC <25> KSI2 4 5 KSO6 4 5
IAC_RESET# IAC_BITCLK KSO0 KSO3
3 6 3 6
HDA_RST#_MDC_R KSI5 2 7 KSO12 2 7
KSI4 1 8 KSO13 1 8

13
14
15
16
17
18
19
20
<25,32> HDA_RST#_MDC 1 2 100P_1206_8P4C_50V8 100P_1206_8P4C_50V8
13 TYCO_1-179396-2~D
14
15
16
17
18
19
20
R1753 0_0402_5% CP7 CP2
KSI3 4 5 KSO14 4 5
0620 RESERVE FOR MDC Connector for MDC Rev1.5 KSO5 3 6 KSO11 3 6
KSO1 2 7 KSO10 2 7
conn@ KSI0 KSO15
1 8 1 8

100P_1206_8P4C_50V8 100P_1206_8P4C_50V8

Power button +3VL

TrackPoint CONN. T/P BOARD.
+5VS
JP14 +5VS JP17
1

+5VS
R536 1 2 SP_CLK TP_DATA 1
3 4 <37> TP_DATA 2
1

SP_DATA 1 <37> TP_CLK TP_CLK 1

5 6 3

2
R22 100K_0402_5% +5VS C321 C319
7 8 4
2

100K_0402_5% U5F ON/OFFBTN_KBC# ACES_87153-0801L D67 0.1U_0402_16V4Z SP_DATA 5 0.1U_0402_16V4Z

14

ON/OFFBTN_KBC# <37> 2 6 2
SN74LVC14APWLE_TSSOP14
2

7
1

R26 D SP_CLK
P

+3VALW conn@ 8
ON/OFF# 13 TP_DATA
<39> ON/OFF# O 12 1 2 2

1
I G R8 @ PACDN042_SOT23~D TP_CLK ACES_87212-0800
G

1 100K_0402_5% 1 S 1 2
3

2
C23 C11 100K_0402_5% conn@
7

1U_0603_10V4Z 1U_0603_10V4Z 1 2 ON/OFFBTN# ON/OFFBTN# <26> D58

2 2 Q70 PJDLC05_SOT23~D
RHU002N06_SOT323 D42
CH751H-40_SOD323

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MDC/KBD/ON_OFF/LID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 38 of 57
 A B C D E

+5VALW

1
DOCK CONN. 184PIN R529

100K_0402_5%
JP29

2
C746 10P_0402_50V8J
RED 1 2 L10 SLP_S5#_5R DOCK_MOD_RING conn@
C747 10P_0402_50V8J KC FBM-L18-453215-900LMA90T_1812 DOCK_MOD_TIP 2
1

1
GREEN D
1 2 VIN 2 1 DOCKVIN
C748 10P_0402_50V8J 1 2 Q65
1 1 <40> SLP_S5 1
BLUE 1 2 C72 C73 G E-T_3800-02_2P
S RHU002N06_SOT323

3
1000P_0402_50V7K 1000P_0402_50V7K
2 2 SWAP

JP30B conn@
C1630 22P_0402_50V8J JP30A conn@
DOCK_RED 1 2 <35> LPTACK# LPTACK# 46 128
C1631 22P_0402_50V8J LPTBUSY 46 128
172 G1 P1 173 DOCKVIN <35> LPTBUSY 47 47 129 129
DOCK_GRN 1 2 <35> LPTPE LPTPE 48 130
C1632 22P_0402_50V8J LPTSLCT 48 130
<35> LPTSLCT 49 49 131 131
DOCK_BLU 1 2 <35> LPD7 LPD7 50 132
ON/OFF# DETECT LPD6 50 132
<38> ON/OFF# 1 1 83 83 <35> LPD6 51 51 133 133
2 84 <35> LPD5 LPD5 52 134 KBD_DATA
2 84 52 134 KBD_DATA <37>
MDO2+ 3 85 MDO3+ MDO3+ <30> <35> LPD4 LPD4 53 135 KBD_CLK
<30> MDO2+ 3 85 53 135 KBD_CLK <37>
MDO2- 4 86 MDO3- MDO3- <30> <35> LPD3 LPD3 54 136 CPPE#
<30> MDO2- 4 86 54 136 CPPE# <15>
5 87 <35> LPD2 LPD2 55 137 PS2_DATA
5 87 55 137 PS2_DATA <37>
MDO0+ 6 88 MDO1+ MDO1+ <30> <35> LPD1 LPD1 56 138 PS2_CLK
<30> MDO0+ 6 88 56 138 PS2_CLK <37>
MDO0- 7 89 MDO1- MDO1- <30> <35> LPD0 LPD0 57 139 DOCK_HPS#
<30> MDO0- 7 89 57 139 DOCK_HPS# <33>
8 90 <35> LPTSLCTIN# LPTSLCTIN# 58 140
LED_ACT_LAN#_DOCK 8 90 PWR_LED LPTINIT# 58 140 DLINE_IN_L
9 9 91 91 <35> LPTINIT# 59 59 141 141 DLINE_IN_L <32>
LED_LINK_LAN#_DOCK 10 92 1 2 SLP_S5#_5R 60 142 DLINE_IN_R
10 92 60 142 DLINE_IN_R <32>
11 93 R515 1K_0402_5% 61 143
11 93 DVI_CLK 61 143 DLINE_OUT_L
<16> D_VSYNC 12 12 94 94 DVI_CLK <19> 62 62 144 144 DLINE_OUT_L <33>
<16> D_HSYNC 13 95 DVI_DAT DVI_DAT <19> 63 145 DLINE_OUT_R
13 95 63 145 DLINE_OUT_R <33>
<16> D_DDCDATA D_DDCDATA 14 96 64 146
D_DDCCLK 14 96 64 146
<16> D_DDCCLK 15 15 97 97 65 65 147 147
HLC0603CSCCR11JT_0603 <19> DVI_DETECT DVI_DETECT 16 98 DVI_TX2- 66 148
0314 change 16 98 DVI_TX2- <19> 66 148
R1404 17 99 67 149 PCIE_TXP5 PCIE_TXP5 <26>
DOCK_RED 17 99 DVI_TX2+ 67 149
<19> RED 1 2 18 18 100 100 DVI_TX2+ <19> 68 68 150 150
1 2 DOCK_GRN 19 101 69 151 PCIE_TXN5 PCIE_TXN5 <26>
2 <19> GREEN 19 101 69 151 2
1 2 DOCK_BLU 20 102 70 152
<19> BLUE 20 102 70 152
R1428 21 103 DVI_TX1- 71 153
21 103 DVI_TX1- <19> 71 153
R1429 <16,19> COMP 22 104 <26> USB20_N7 72 154 PCIE_RXP5_DOCK 1 R1346 2PCIE_RXP5
22 104 72 154 PCIE_RXP5 <26>
HLC0603CSCCR11JT_0603 <16,19> CRMA 23 105 DVI_TX1+ 73 155 0_0402_5%
23 105 DVI_TX1+ <19> 73 155
HLC0603CSCCR11JT_0603 <16,19> LUMA 24 106 <26> USB20_P7 74 156 PCIE_RXN5_DOCK 1 R1347 2PCIE_RXN5
24 106 74 156 PCIE_RXN5 <26>
25 107 75 157 0_0402_5%
25 107 DVI_CLK- 75 157
26 26 108 108 DVI_CLK- <19> <26> USB20_N9 76 76 158 158
27 109 77 159 CLK_PCIE_DOCK
<32> LINE_IN_SENSE 27 109 77 159 CLK_PCIE_DOCK <15>
28 110 DVI_CLK+ <26> USB20_P9 78 160
28 110 DVI_CLK+ <19> 78 160
29 111 79 161 CLK_PCIE_DOCK#
<50> ACOCP_EN# 29 111 79 161 CLK_PCIE_DOCK# <15>
30 112 <35> SER_SHD SER_SHD 80 162
30 112 DVI_TX0- EXPCRD_RST# 80 162 PREP#
31 31 113 113 DVI_TX0- <19> <35> EXPCRD_RST# 81 81 163 163 PREP# <26,30,32>
32 114 DETECT 82 164 VA_ON#
32 114 DVI_TX0+ 82 164
33 33 115 115 DVI_TX0+ <19>

1
DCD#1 34 116 176 178 1
<35> DCD#1 34 116 GND GND
RI#1 35 117 DOCK_ADP_SIGNAL 169 180 R66 C59
<35> RI#1 35 117 GND GND
DTR#1 36 118 DOCK_ID 175 182
<35> DTR#1 36 118 DOCK_ID <26> GND GND
CTS#1 37 119 179 174 1K_0402_5% 0.1U_0402_16V4Z
<35> CTS#1 37 119 +3VS GND GND 2
RTS#1 38 120 181 171
<35> RTS#1

2
DSR#1 38 120 GND GND
<35> DSR#1 39 39 121 121 R1387 177 GND GND 170
TXD1 40 122 +5VS
<35> TXD1 40 122 C678
RXD1 41 123 DOCK_ID 1 2
<35> RXD1 41 123

+
42 42 124 124 165 G2 P2 167 1 2
LPTSTB# 43 125 @ 10K_0402_5%
<35> LPTSTB# 43 125 ADP_SIGNAL
LPTAFD# 44 126 @ 22U_1206_10V4Z
<35> LPTAFD# 44 126
LPTERR# 45 127 DOCK_MOD_RING 166 168 DOCK_MOD_TIP
<35> LPTERR# 45 127 R1401 RING TIP

2
DOCK_ADP_SIGNAL 1 2
JAE_SP03-14588-PCL03 JAE_SP03-14588-PCL03
1K_0402_1% D59
@ PACDN042_SOT23~D

3 3

1
Closed to JP30

+3VS
U52 +3VS +3VS
U51 U50
5 VCC
5 VCC 5 VCC
<19> BLUE 1 A
<16> L_BLUE L_BLUE 2 1 1
B <19> GREEN A <19> RED A
<16> L_GREEN L_GREEN 2 <16> L_RED L_RED 2
ISO_PREP# B B
<26> ISO_PREP# 4 OE ISO_PREP# 4 ISO_PREP# 4
OE OE
3 GND
3 GND 3 GND
FSA66P5X_SC70-5
FSA66P5X_SC70-5 FSA66P5X_SC70-5

R1937 +3VALW
+3VM_LAN LED_ACT_LAN#_DOCK_R 1 2 LED_ACT_LAN#_DOCK
0_0402_5%
1

4 R527 D 4
C1627
2 1 2 Q62 @ R526
10K_0402_5% G RHU002N06_SOT323 2 1
S 10K_0402_5%
3

LED_ACT_LAN# <29,30> 100P_0402_50V8J

2

R1938
PWR_LED
LED_LINK_LAN#_DOCK_R 1 2LED_LINK_LAN#_DOCK Security Classification Compal Secret Data Compal Electronics, Inc.
1

0_0402_5% D
1

D 100P_0402_50V8J <31,37,38> LED_STB# 2 Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title
2 Q63 @ C1628 G
G RHU002N06_SOT323 2 1 Q59 S Docking CONN.
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
S RHU002N06_SOT323 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
3

LED_LINK_LAN# <26,29,30> <26,29,32,33,37,40,47,48,49,50,51,52> SLP_S3# DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 39 of 57
A B C D E
 A B C D E

+1.25VM to +1.25VS Transfer +3VALW to +3VM Transfer +3VALW +3VM

U78
B+ 8 1
+1.25VM +1.25VS D S
7 D S 2
C1273 1 6 3
D S

1
U77 +3VALW 10U_0603_6.3V6M 5 4
D G 1 1
8 1 10U_0603_6.3V6M R1643 C1274 C1275
D S 100K_0402_5% SI4800DY_SO8
7 D S 2 1

1
2 10U_0603_6.3V6M
1 6 D S 3
C1270 + C254 R1647 2 2
5 4 1 1

2
D G C1271 C1272 330U_D2E_2.5VM_R15 100K_0402_5% PM_SLP_M
1 SI4800DY_SO8 1

1
2 10U_0603_6.3V6M 2 0.1U_0402_16V4Z

1
0_0402_5% 2 2 D R470
RUNON 1 2+1.25VS_ON LAN_WOL_EN# 2 Q108
R1918 1 G BSS138_SOT23 470_0402_5%

1
1SS355_SOD323 0.1U_0402_16V4Z D
S

2
1 2 C1616 <26,37,47,48,52> PM_SLP_M# 2 1
0.1U_0402_16V4Z G +3VALW C121
@ D75 2 @ 0904 Add S

3
BSS138_SOT23 0.01U_0402_25V7Z

1
Q116 2
R1940
2007,0125 change 100K_0402_5%
+3VALW to +3VS Transfer

1
D
<26> LAN_WOL_EN 2 Q110

2
+3VALW +3VS G
B+ S

3
1
U13 BSS138_SOT23
8 1 0.1U_0402_16V4Z @R630
@ R630
D S
1

7 2 100K_0402_5%
R139 D S
1 6 D S 3
C127 5 4 1 1

2
330K_0402_5% D G C132 C128
SI4800DY_SO8
2

2 10U_0603_6.3V6M
R17 0_0402_5% 2 2
RUNON 1 2 +3VS_ON
1
+1.8V to VDD_MEM18 Transfer
1

J34 1SS355_SOD323 10U_0603_6.3V6M

SHORT PADS R469

1 2 C1619
0.1U_0402_16V4Z
Discharge circuit-2 for V-M
1 2

470_0402_5% @D76
@ D76 2 @ +1.8V VDD_MEM18
2 D 2
1
2

SLP_S3 2 +1.25VM +1.05VM U85

G C120 +3VM 0.1U_0402_16V4Z
8 D S 1
Q18 S 0.01U_0402_25V7Z 0904 Add 7 2 1
3

D S

1
2
1 6 D S 3

1
R631 R632 C1602 5 4 + C1601
D G 1 1
RHU002N06_SOT323 R633 C1603 C1604 330U_D2E_2.5VM_R15
47_0603_5% 470_0402_5% SI4800DY_SO8
470_0402_5% 2 10U_0603_6.3V6M 2

1 2

1 2
2 2

1 2
D D RUNON
D 1 2+1.8VS_ON 10U_0603_6.3V6M
LAN_WOL_EN# 2 LAN_WOL_EN# 2 10K_0402_5% 1
G G LAN_WOL_EN# 2 R1919
Q111 S Q112 S G D77 C1617
+5VALW to +5VS Transfer
3

3
RHU002N06_SOT323 RHU002N06_SOT323 Q113 S 1 2 0.001U_0402_50V7M

3
RHU002N06_SOT323 2

+5VALW 1SS355_SOD323 11/20 for ATI power sequence to install

+5VS
U9
8 1 0.1U_0402_16V4Z
D S
7 D S 2
1 6 D S 3 1 1
C86 5 4 C71 C77
D G
SI4800DY_SO8 10U_0603_6.3V6M +3VL +3VL +5VALW VDD_MEM18
2 10U_0603_6.3V6M 2 2
1

1
0_0402_5% R1920
RUNON 1 2+5VS_ON R125 R129 R135 R1895
1 0904 Add
1 2 100K_0402_5% 100K_0402_5% 100K_0402_5% 470_0402_5%
3 C1618 3
2

1 2
@ D78 0.1U_0402_16V4Z SLP_S3 SLP_S4 SLP_S5
2 <39> SLP_S5 D
1SS355_SOD323 @
1

1
D D D
SLP_S3 2
SLP_S3# 2 2 SLP_S5#2 G
<26,29,32,33,37,39,47,48,49,50,51,52> SLP_S3# <26,48> SLP_S4# <26,48> SLP_S5#
G G G Q131 S

3
Q19 S Q23 S Q22 S RHU002N06_SOT323
3

3
RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323

Discharge circuit-1
+1.8V
C91

1
1 2 +0.9V +3VS
+VCC_CORE +VCCP
R1310
+1.5VS +2.5VS +5VS
0.1U_0402_16V4Z
1

470_0402_5%
R186 R134

2
1

1
C184
470_0402_5% 470_0402_5% R151 R130 R116
+VCCP 1 2 +1.5VS
1 2

470_0402_5% 470_0402_5% 470_0402_5% SLP_S4 1 2

D PWR_GD <21,26,31,37,41,49,50>
R107 0_0402_5%
1 2

1 2

1 2
0.1U_0402_16V4Z
1

1
SLP_S4 1 Q27 D D
2 2 D D D
R1311 0_0402_5% G SLP_S3 2 SLP_S5 1 2 2
C93
S G Q17 SLP_S3 2 SLP_S3 2 SLP_S3 2 @ R110 0_0402_5% G Q90
3

+1.5VS 1 2 +1.8V SLP_S5 1 2 S G Q47 G Q21 G Q16 S

3

3
4 @R1312
@ R1312 0_0402_5% S S S 4
3

3
0.1U_0402_16V4Z RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323
RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Circuits
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 40 of 57
A B C D E
PWR_OK circuit KBC PWR_OK circuit
1M_0402_5% R126 +3VS
CH751H-40_SC76 2 1
+1.25VS 1 2 D71

1
+3VL
10K_0402_5% R47
2 1 R285 +5VALW
<52> VCCP_POK
10K_0402_5% +3VL +3VL

1
232K_0402_1% 20K_0402_5% U91A
J38

2
2 1 R288 2 1 3 R24

P
+5VS +
O 1 1 2 PWR_GD <21,26,31,37,40,49,50>
150K_0402_1% R115 VREF_393 2 100K_0402_5% R1943

14

14
-

G
+3VS 2 1 R289 U5D U5C

2
LM393M_SO8 SHORT PADS 0_0402_5%

P
4
D69 10K_0402_5% 9 8 5 6 1 2
I O I O VCC1_PWRGD <36,37>
DDR_PGOOD 1 2 1 2 R1747

1
CH751H-40_SC76 1
@ 100K_0402_5% C26 R1939

7
VDD_MEM18 1 2 R5
0.1U_0402_16V4Z 100K_0402_5%
@ 130K_0402_5% 2

2
+2.5VS 1 2 R14 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14

1219 Add Schmitt Trigger to eliminate glitch and pull down resistor
1

1
R128 C32

49.9K_0402_1% 1000P_0402_50V7K
2
2

Energy Star for CPU 1114 Add

+3VALW R117

0_0402_5%
1

<48> 1.8PGOOD 2 1 DDR_PGOOD

E_STAR <17>
1M_0402_5%
R1910 @ R43 +3VALW
1

2
10K_0402_5% D
1 2
2 @ D80
1 2

1
G Q133 +3VALW CH751H-40_SC76 +3VALW
R284 C S RHU002N06_SOT323
3

+0.9V 2 1 2 Q134 20K_0402_5% @ R46

1
5

1
3.3K_0402_5% B @R1931
@ R1931 @U88
@ U88 10K_0402_5% U90 @
E MMBT3904_SOT23 2 1 1 100K_0402_5% SN74LVC1G14DCKR_SC70-5

NC
+VCC_CORE
3

2
IN+
O 4 1 2 1 2 2 A Y 4 VCC_IDL <26>
3 1 @R53
@ R53
IN-

G
@ R52
@ R1933 20K_0402_5%

3
1.24VREF 2 1 @ C1623
2

1
20K_0402_5% 1 LMV331IDCKRG4_SC70-5~D 0.1U_0402_16V4Z

@C1622
@ C1622
0.1U_0402_16V4Z 2 @R1934
@ R1934

2
100K_0402_5%
D70 +3VALW
R199
DDR_PGOOD 1 2 1M_0402_5%
1 2
1

CH751H-40_SC76
20K_0402_5% +5VALW R49
R1911 10K_0402_5%
R198
8

10K_0402_5% U91B
1 2 1 2 5
P

<52> M_PROK
2

+
O 7 M_PWROK <7,26>
+3VM 1 2 VREF_393 6 -
G

76.8K_0402_1% 10K_0402_5%
R1912 LM393M_SO8
R178
4

1 2
1

1 1.24VREF 1
C1613
R39 C33 H1 H2 H3 H4 H5 H6 H7 H8 H9
1000P_0402_50V7K 56.2K_0402_1% 1000P_0402_50V7K FM1 FM2 FM3 FM4 FM5 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEAHOLEA HOLEA
2 2
1 1 1 1 1
2

1
CF7 CF8 CF9 CF10 CF11 CF12 CF13 CF14
1 1 1 1 1 1 1 1

H18 H19 H20 H21 H22 H23 H24 H25

CF6 HOLED HOLED HOLED HOLED HOLED HOLED HOLED HOLED
H15 H16 H17 1
LAN_RST circuit HOLEC HOLEC HOLEC

1
1

11/20 Enable ACBS (power management for NIC)

+3VL +3VL H27 H28 H32 H33 H34 H35 H36 H37
Need be tune to H10 H11 H12 H13 H14 HOLED HOLED HOLED HOLED HOLED HOLED HOLED HOLED
HOLEB HOLEB HOLEB HOLEB HOLEB
1 10msec time delay 1
C991 C992

1
CH751H-40_SOD323
D60
1

0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
14

14

2 1

R1732 R1350
P

+3VM 2 1 1 I O 2 1 2 3 I O 4 LAN_RST# <26>

120K_0402_5% 100K_0402_1%
G

G
0.1U_0603_50V4Z

U5A 1 SN74LVC14APWLE_TSSOP14
U5B
7

Security Classification Compal Secret Data Compal Electronics, Inc.

C990

SN74LVC14APWLE_TSSOP14 2
Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
POK CKT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 41 of 57
 5 4 3 2 1

D D

+1.25VM G965
APL5912
AC VIN LDO +1.05VS +3VS LDO
Adapter VS (1.05V) (2.5V)
in Page46
Page37 Page41

+5VALWP
SWITCH
+1.25VM
ACOK APL5912
MAINPWON LDO +1.05VM
+2.5VS 1A
(1.05V)
+3VALWP 4A Page46
ENBL2 ENBL1
+5VS
B+ B+ PWR_GD
C MAX8734A B+ ISL6269 C

DC/DC DC/DC VDD_CORE

(3V/5V) (VDD_CORE) VCC SHDN#
+5VALWP 4A Page45
VMB VIN Page40 ISL6260 &ISL6208
VS +1.8VS DC/DC
APL5912
LDO PCIE_VDD (CPU_CORE)
+3VLP 0.1A
(PCIE_VDD)
Page43
Page45
BQ24703 MAX8743
Charger DC/DC +1.5VSP 4.2A
B+ (1.05V/1.5V) CPU_CORE
Page38
B
( 44A) B

SLP_S3# Page41
+1.25VM 8A +5VALWP
ENBL1/ENBL2
BATSELB_A
Battery
Selector
Circuit BATSELB_A# VCC
Battery A Battery B
Page39
6 Cell 8 Cell TPS51116
B+ DC/DC +1.8VP 7A
VMB (+1.8VP/+0.9VSP)

SWITCH SWITCH SWITCH Battery Battery +0.9VP 2A

VMB_A VMB_B SLP_S5# S3/S5 Page42
Connector Connector
A A Page37 B Page37
A

BATT
BATT_A Title
POWER BLOCK DIAGRAM
BATT_B
Size Document Number Rev

Date: Tuesday, August 21, 2007 Sheet 42 of 57

5 4 3 2 1
 A B C D

PCN1 ADP_SIGNAL
9 GND6 SINGAL 5 VIN
8 GND5
1 PL1 1

7 1 SMB3025500YA_2P
GND4 PWR1
6 ADPIN 1 2
GND3

100P_0402_50V8J
4 GND2 PWR2 2

1000P_0402_50V7K
3 GND1

1
PC1

100P_0402_50V8J
1

1
PC4
FOX_JPD113E-LB103-7F PC2 PR1
1000P_0402_50V7K

PC3
@15K_0402_5%

2
AB/I_A <44>
VMB_A PL2 BATT_A
PCN2
FBM-L18-453215-900LMA90T_1812
BATT+ 1 1 2

2 EC_SMD_A
SMD EC_SMC_A PR2
SMC 3
2
RES 4 2 1 2

1
5 1M_0402_1%
TS PC5 PC6
6 1000P_0402_50V7K 0.01U_0402_50V4Z

2
GND +3VL
TYCO_C-1746706_6P
1

1
PR3
1K_0402_5% PR10
210K_0402_1%
2
1

2
PR4 PR5
THM_MAIN# <37>
100_0402_5% 100_0402_5%
2

EC_SMD_A1 AB1A_DATA <37>

EC_SMC_A1 AB1A_CLK <37>
1

1
220P_0402_25V8K
PC144

PC143 PC145
220P_0402_25V8K 220P_0402_25V8K
2

3 3

VMB_B

PCN3 PL3 BATT_B

FBM-L18-453215-900LMA90T_1812
BATT+ 1 1 2

2 EC_SMD_B
SMD EC_SMC_B
SMC 3
1

4 AB/I_B 2 PR7 1
B/I TS_B 1K_0402_5% PC8 PC9
TS 5
1 2 1000P_0402_50V7K 0.01U_0402_50V4Z
+3VL
2

2
2

6 PR9
GND PR11 210K_0402_1%
SUYIN_20163S-06G1-K 1K_0402_5%
1
1

PR14 PR15
THM_MBAY# <37>
100_0402_5%
100_0402_5%
2

EC_SMD_B1
AB1B_DATA <37>
4 4

EC_SMC_B1
AB1B_CLK <37>

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 43 of 57
A B C D
 A B C D

1 1

VIN P2

BATT
P4 PQ2
PQ3 PQ4 AO4407_SO8
AO4407_SO8 AO4407_SO8 1 8
1 8 8 1 2 7
2 7 7 2 3 6
3 6 6 3 5
0.1U_0603_16V7K

PQ5 5 5

2
B+ P2
47K_0402_5%

DTA144EUA_SC70 PR17

4
1

3 1 PR398 0_0402_5%
4

4
1
PC12

PR16 @200K_0402_5% 1 2
2

47K

200K_0402_5%
PR20 PL4
47K

1
0.015_2512_1% FBM-L11-322513-151LMAT_1210
2

@150K_0402_5%
1 2 1 2
2

1
PR18
1

2
0_0402_5%
47P_0402_50V8J

PR399
ADP_PRES <29,37,45,46,50>
2

PR19
CHG_B+
<50> ACN
1
PC13

1
4.7U_0805_25V6K

4.7U_0805_25V6K

4.7U_0805_25V6K

4.7U_0805_25V6K
PR343
1

1 2
PR22 PR23
1

1
D 100_0402_1% 0_0402_5%
1

PC198
PC43

PC14

PC15
ACDRV# 2 2 1
2

220K_0402_5% 2 PQ131 G

4.7U_0805_25V6K
1U_0805_25V4Z
G PQ93 @RHU002N06_SOT323 S

1
S RHU002N06_SOT323 1 2
3

1
PC17
PR396
<50> BATCAL#

PC200
2 0_0402_5% PC16 PD5 2

2
2

ADP_PRES 1 2 1U_0603_10V6K RLZ16B_LL34

2
PR21 1 2
2

3
2
1
150K_0402_5% PR24 PU2
PR397 1K_0402_1% 8 25 ACDRV#
@0_0402_5% ACN ACDRV#
9 22
1

ACP VCC DH_CHG PQ7

PD7 26 ACDET PWM# 21 4
16 FDS4435_SO8
1

<50> SRSET AC_CHG SRP

2 1 ADP_EN# <50> 2 PR25 1 5 ENABLE SRN 15
1K_0402_1% 28 12
ACSEL BATP
1SS355_SOD323
ALARM 19 ALARM BATDRV# 24 BATT
1 2 2 SRSET
3 18 PR28
PL5

5
6
7
8
<37,45> CHGCTRL PR26 ACSET VS
+3VL 2 PR27 1 27 ACPRES VHSP 20 0.015_1206_1%
191K_0402_1% 100K_0402_5% 13 LX_CHG 1 2 1 2
BQ24703VREF IBAT CV=12.6V(6 CELLS LI-ION)

10U_1206_25V6M
137K_0402_1%
1U_0603_10V6K

4.7U_0805_25V6K
4 VREF BATSET 6
2

100K_0402_1%

10UH_PCMB104T-100MS_6A_20%
BATDEP 1 1 16.8V(8 CELL LI-ION)
1

1
PC18

PR29

7 COMP GND 17

1
PGND

3K_0402_1%

3K_0402_1%
PR30

PC19

PC20
10 23
NC1 NC4 CC=3A for 2.4AHr

1
11 14
2

2
NC2 NC3 2

PR31

PR32
CC=3.57A for 2.55AHr
1

4.7U_0805_10V4Z

BQ24703_QFN28 PD8
2

29
SKS30-04AT_TSMA

2
1

PC22 Icharger=3A

2
80.6K_0402_1%

PC21
1

1 2 CELLSEL# =0,Vcharger= 12.6V

2
1
1U_0603_10V6K
PC23

PR33

SE_CHG+
ACDET
SE_CHG-
0.1U_0402_16V7K CELLSEL# =1,Vcharger= 16.8V
2

P2
2

+3VL +3VL
PR34 BATT
150P_0402_50V8J

1 2 PR35
3
330K_0402_5% 150_0402_1% 3
1
100K_0603_1%

PC24

1
4.7U_0805_10V6K
1 2
1

1
10K_0402_1%

PR44
2

VL
PR36

PR37

PC25 5.62K_0603_0.1%
0.1U_0402_16V7K BATT
PC26
2

+3VL
2

1 2
AC detector PR39
2

2
8

2.15K_0402_1% PU3A PU4

High 11.689V 1

1
1 2 3 SN74LVC1G17DBVR_SOT23-5 PR380
P

+ PR42 100K_0603_0.1% +3VL

Low 9.879V O 1 2 I O 4 ADP_PRES <29,37,45,46,50>
1

12.4K_0603_1%

2 196K_0402_1%
- NC 1
G

PR384
PR40

1
LM393M_SO8 100K_0402_5%
4

2
+3VL
CELLSEL#

1
2

PR381 PR385
PR43 PR382 7.68K_0603_0.1% 330K_0402_5%

1
+3VL 25.5K_0402_1% D
4.7K_0402_5%
1

PR46 2

2
PR45 1 2 PR47 G
PR386
2

2
1

1
D

RHU002N06_SOT323
130K_0402_1% 1M_0402_5% 1 2 ALARM <45> <43> AB/I_A S

PQ112 3
100P_0402_50V8J

PC27 100K_0402_5% 2 1 2 2

1
10K_0402_1%

@0.1U_0402_16V7K G
2

2
8

1
D D

RHU002N06_SOT323
PU3B PQ8 RHU002N06_SOT323 330K_0402_5% <50> S I_A#

PQ111 3
BQ24703VREF
PC28

PR48

5 2 PR360 2
P

+ G PR383 G
7 AC_CHG <45> 2.8K_0603_0.1% CFET_B <45,50>
2

O
1
10K_0603_1%

RHU002N06_SOT323

6 S 200K_0402_1% S
3

3
-
1

@47K_0402_1%

PQ110
22P_0402_50V8J

PR49
2
PR51

LM393M_SO8 100_0402_5%
4
1
PR50

PC29

VL
2

PR54
2

4 4

1 2 CELLSEL#
1

PQ10 D D
33K_0402_1% AC_CHG ACDET 2 2 PQ11
G G RHU002N06_SOT323
PU5 S S
3

1.24VREF RHU002N06_SOT323
4 REF CATHODE 3

Airline detector NC 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title
High 17.521V 5 1
Low 16.871V ANODE NC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
APL1431LBBC_SOT23-5 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 44 of 57
A B C D
 A B C D

+3VL

@0.1U_0402_10V6K
1
PC30
1 1

BATT_A

2
5
PU6 PD9
BATT_B PQ12

5
+3VL PU7 1 2

P
INB RHU002N06_SOT323
1 4 1

P
<44> ALARM INB O PR55 PR56
O 4 2 INA 3

G
47K_0402_5%
BATT_IN

S
2 INA 1 2 1 3 1 2

2
PR57
74LVC1G02_04_SOT353 RB715F_SOT323 100_0402_5% 0_0402_5%

0.1U_0603_50V4Z
74LVC1G02_04_SOT353 PD10

3
PQ13
1SS355_SOD323

G
2
RHU002N06_SOT323 PR58
PC31

1
PC32
1.5M_0402_5%

1
S

D
BATSELB_A 1 2 3 1

1
2
1000P_0402_50V7K PQ14 PD11
2

D RHU002N06_SOT323 +3VL
22K_0402_5%

G
2
LATCH
PR59

2 RLZ6.2C_LL34
G +3VL

2
S
3
1

1
PU8

NC
2 A Y 4
PQ15

G
PC33
1

RHU002N06_SOT323 D SN74LVC1G14DCKR_SC70-5 BATT

3
BATSELB_A# 1 2 2 1
G D
2

22K_0402_5%

1000P_0402_50V7K S PQ16 2 ADP_PRES <29,37,44,46,50>

3

RHU002N06_SOT323 G
PR60

2
S 2
3

1
1

PMBT2222_SOT23
PR61
PQ17
470K_0402_5%

1
RHU002N06_SOT323 D
+3VL +3VL BATT_IN 2

1
C G

2
PQ18
2 S

3
B PR62

10K_0402_5%
E 470K_0402_5%

3
1
PQ19

PR63
PD12

1
RHU002N06_SOT323 D

1
CFET_A 1 2 2
G PR64

2
5

PU9 PU10 S 4.7K_0402_5%

PD13

3
1SS355_SOD323

5
P

NC

PR65

1
BATSELB_A# BATSELB_A PQ20 D
2 4 1 1 2

P
<37> BATSELB_A#

2
A Y IN1
O 4 1 2 2
G

2 G RHU002N06_SOT323 SX34-40_SMA
IN2

G
SN74LVC1G14DCKR_SC70-5 S
3

3
10K_0402_5%

4
3

1
+3VL D
220P_0402_50V7K

SN74AHC1G08DCKR_SC70 PQ23 5 5
BATT_IN 2 3 6 6 3 PR66 BATT_A
1

PC34

G 2 7 7 2 470K_0402_5%
S 1 8 8 1

3
RHU002N06_SOT323 BATT
2

2
0.047U_0402_16V7K

PQ21 PQ22
2

AO4407_SO8 AO4407_SO8
470K_0402_5%
1

+3VL
PC35

PR70

PQ24 PQ25
3
+3VL AO4407_SO8 AO4407_SO8 3

1
1 8 8 1
2

PU11 2 7 7 2 PR67
1

1
SN74LVC1G14DCKR_SC70-5 3 6 6 3 470K_0402_5%
P

NC

PMBT2222_SOT23
2 PR68
A Y 4 5 5
2
220K_0402_5%

470K_0402_5%

2
G

BATT_B

4
2

470K_0402_5%
PR69
3

PR72
PR71 PU12 C
CHGCTRL PC180 PR342 PD15
1

PQ26
10K_0402_1% 2
1

PQ27

1
10K_0402_5%
1 2 1 2 2 1 B 1 2
P
1

G RHU002N06_SOT323 IN1 E PR73

<44> AC_CHG 4

1
O

1
PR74
1000P_0402_50V7K 1K_0402_5% S BATSELB_A# 2 4.7K_0402_5%
PD16
3

IN2 SX34-40_SMA
G
470K_0402_5%

3 1
1

PQ94 1 2
3

2
PR344

RHU002N06_SOT323 SN74AHC1G08DCKR_SC70
G

CFET_B#
2

2
ADP_PRES 1SS355_SOD323 PQ29

1
PD14 RHU002N06_SOT323 D
PR75
2

1
1SS355_SOD323 PQ28 D
2
1 2 2 G
+3VL G RHU002N06_SOT323 S

3
10K_0402_5% S
3

<44,50> CFET_B PQ30

CFET_B

1
RHU002N06_SOT323 D
PQ31 BATT_IN 2
5

PD17 D G
CFET_A 2 PU13 BATT_IN 2 S
P

3
1 2 4 G RHU002N06_SOT323
CFET_B I O BATCON <37>
3 1 S
3

NC
G

4 4
1

100K_0402_5%

RB715F_SOT323 SN74LVC1G17DBVR_SOT23-5
3
PR77
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Battery selector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 45 of 57
A B C D
 A B C D E

+3.3V/+5V

B+
2

1 1
PL6
FBM-L11-322513-151LMAT_1210 PC36 PC37
0.1U_0603_50V4Z 0.1U_0603_50V4Z
1 2 BST5B BST3B 1 2
B++
1

B++

2
PD18
2200P_0402_50V7K

2200P_0402_50V7K
CHP202U_SC70

10U_1206_25V6M

4.7U_0805_25V6K
1 VL
1

8
7
6
5

5
6
7
8
1
PC38

PC39

PC41

PC42
PQ34 PQ35

D
D
D
D

D
D
D
D
2
AO4468_SO8 AO4468_SO8
2

2
2 PR79 B++

47_0402_5%
0_0402_5%

G
S
S
S

S
S
S
PR80
DH5 PC40

1
2
3
4

4
3
2
1
0.1U_0603_50V4Z

2
LX_5V

1
8
7
6
5

5
6
7
8
2
0.1U_0603_50V4Z
PQ126 PQ127
D
D
D
D

D
D
D
D
AO4468_SO8 VL PR82 AO4468_SO8
0_0402_5%
1

2VREF_1999
G

G
S
S
S

S
S
S
4.7U_0805_10V4Z

1
LX_5V <50>

499K_0402_1% 200K_0402_1%

499K_0402_1% 100K_0402_1%
1U_0805_25V4Z
1
2
3
4

4
3
2
1
1

1
PC44

PR83
PL7

PR84
4.7UH_SIQB745-4R7_4A_30% BST3A

1
PC45

PC46
2

2
2 PL8 2

2
4.7UH_SIQB745-4R7_4A_30%

2 1

2 2
18

20

13

17
BST5A 14

TON

VCC
LD05

V+

2
BST5

PR86

PR87
ILIM3 5
16 DL3
DH5
+5VALWP

1
15 LX5
DL5 19 PU14 11 LX3
DL5 ILIM5
21 OUT5 MAX8734EEI_QSOP28
9 FB5 BST3 28
@10.2K_0402_1%

1 26 DH3
N.C. DH3
2

B++ 24
DL3
150U_B2_6.3VM

PR88

1 6 SHDN# LX3 27
4 ON5 OUT3 22
1

1
47K_0402_5%
PC47

+ 2VREF_1999 1 2 3
PC197 PR89 ON3
7
1

FB3
PR90

22U_0805_6.3VAM 1 2 0_0402_5% 12 2 +3VALWP

2

2 0_0402_5% SKIP# PGOOD

2VREF_19998

@3.57K_0402_1%
PRO#
LDO3
PR91

GND
2

REF
2

2
0_0402_5%

PR93

150U_B2_6.3VM
PR92

PR94
1 2 1
1

@0_0402_5%

23

25

10

PC49
+

0.22U_0603_10V7K
PC48
0.1U_0603_50V4Z
1

2 1
1
MAINPWON

PC50
PGOOD

2
2

1
PR95 100K_0402_5%

0_0402_5%
PR96
0_0402_5%

4.7U_0805_10V4Z
VL PR242

+3VLP +3VALWP

1
1

1
3 3

2
PC51
PR97 +3VL

2
499K_0402_1%
2

+3VLP
1

+3VL
PR98 PJP1
100K_0402_5% 2 1
1

PAD-OPEN 2x2m
2

PC52
1

0.1U_0603_50V4Z D
2

PQ36 2
RHU002N06_SOT323 G
S RHU002N06_SOT323
3

D PQ37
2
G KBC_PWR_ON <37>
S
3

RHU002N06_SOT323
1

D PQ77
2
G ADP_PRES <29,37,44,45,50>
S
3

4 4

Security Classification Compal Secret Data

Issued Date 2005/03/01 Deciphered Date 2006/03/01 Title
3.3V / 5V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 46 of 57
A B C D E
 A B C D

PL9
MAX8743_B+ FBM-L11-322513-151LMAT_1210

10U_1206_25V6M
2 1 B+
1

1
2200P_0402_50V7K
+5VALW

PC53

PC54
8
7
6
5

2
PR99

2
PQ38 2 0_0402_5%

D
D
D
D
1
AO4468_SO8 1

1
G
S
S
S
1
2
3
4
1U_0805_25V4Z

2200P_0402_50V7K
PC56

1
PD19
PQ39

4.7U_0805_25V6K
PC55

8
7
6
5

1
4.7U_0805_10V4Z 1 8

2
D2 G2

1
PQ40 PR100 2 7

D/K
D/K
D/K
D/K

2
D2 D1/S2/K

PC57

PC58
AO4712_SO8 20_0603_5% 3 6
CHP202U_SC70 G1 D1/S2/K
+1.5VSP 4 5

2
S1/A D1/S2/K

S/A
S/A
S/A

2
G
BST_1.25V_2

1
2
3
4
SI4914_SO8

BST_1.5V_2
1 2 BST_1.5V_1
PC59

0.1U_0603_50V4Z
0.1U_0603_50V4Z PR101 VCC_MAX8743
PL10

V+ 1U_0805_25V4Z
0_0402_5% PL11 +1.25VMP

1
2 1 2 1 PR102 PC62 3.3UH_SIQB74-3R3RF_4.8A_30%

PC60

PC61
0_0402_5% 0.1U_0603_50V4Z
220U_B2_2.5VM

1 3.3UH_SIQB74-3R3RF_4.8A_30% 1 2 2 1 1 2

2
2.2U_0603_6.3V6K

BST_1.25V_1
1

220U_B2_2.5VM
PC63

PR104

22
1

9
PC64

PU15 0_0402_5%

2.49K_0402_1%

PC66
PR103 25 21 1 2 DH_1.25V_2 +

UVP
VCC
2

BST1 VDD

1
2 2.2_0402_5%
1

5.1K_0402_1%

PR105
DH_1.5V_2 1 2 DH_1.5V_1 26 19
DH1 BST2 2
PR106

18 DH_1.25V_1
LX_1.5V DH2 LX_1.25V
27 LX1 LX2 17
DL_1.5V 24 20 DL_1.25V

2
DL1 DL2
2
16 2
2

CS2
28 CS1
1 OUT1 OUT2 15
FB2 14
2 FB1 ON2 12
1

PD30 PGOOD 7

10K_0402_1%
PR107 5 2 1
TON

PR111
10K_0402_1% 1 2 11 PR108
ON1 0_0402_5%
ILIM2 13
3

SKIP
GND
OVP
2

REF
1SS355_SOD323 ILIM1

2
MAX8743EEI_QSOP28 PR113
PD31

23

10
20K_0402_1%
<26,29,32,33,37,39,40,48,49,50,51,52> SLP_S3# 1 2 2 1 2 1
PR123 2VREF
@0.001U_0402_50V7M

0_0402_5% 2 1 1SS355_SOD323

100K_0402_1%
1

1
VCC_MAX8743 2 1 PR114
1

PR118
PC71

@0_0402_5% 20K_0402_1%

1
PR117
PM_SLP_M# <26,37,40,48,52>

0.22U_0603_10V7K
PR116 100K_0402_1% 2 1
2

PC69
PR121

@0.001U_0402_50V7M
PR120 0_0402_5%

2
0_0402_5%

PC70
2
3 3

+3VALW

1
PJP11
PAD-OPEN 2x2m
+2.5VS

2
PU26

1
2 VIN VO 3
PC134
10U_0805_6.3V6M 1 4 PR244

2
EN ADJ 13.7K_0603_1%

1
5 7

2
GND GND PC135
PJP6 PJP3 10U_0805_6.3V6M
6 8

2
GND GND

1
+1.5VSP 1 2 +1.5VS +5VALWP 1 2 +5VALW PR243
(4A,160mils ,Via NO.=8) (4.5A,180mils ,Via NO.= 9) G965-18P1U_SO8
PAD-OPEN 3x3m 47K_0402_5% PR245
PAD-OPEN 4x4m
1 2 12K_0402_1%
PJP5 <26,29,32,33,37,39,40,48,49,50,51,52> SLP_S3#

2
PJP16 1 2
PAD-OPEN 4x4m +3VALWP +3VALW
(3A,120mils ,Via NO.= 6)

1
1 2 +VCCP (4A,160mils ,Via NO.= 8) PC170
+1.05V_VCCP PAD-OPEN 4x4m
0.1U_0402_16V7K
PJP2

2
PJP8 +1.25VMP 1 2 +1.25VM (8A,320mils ,Via NO.= 16)
4 +0.9VP 1 2 +0.9V (2A,80mils ,Via NO.= 4) PAD-OPEN 4x4m 4

PAD-OPEN 3x3m

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title
PJP15
+1.05VMP 2 1 +1.05VM (1A,40mils ,Via NO.= 2) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2.5VALW/1.5VS/1.25VMP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
PAD-OPEN 2x2m DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 47 of 57
A B C D
 5 4 3 2 1

D D

DDR_B+ PL12
FBM-L11-322513-151LMAT_1210
+1.8V 2 1 B+

2200P_0402_50V7K
1

1
1

0_1206_5%

PC72
PC73

5
6
7
8
10U_1206_25V6M

PR124

2
PQ45 2

D
D
D
D
AO4468_SO8
PR125 PC74

2
0_0402_5% 0.1U_0603_50V4Z

12
7

G
S
S
S
PU17 BST_1.8V_1
1 2 BST_1.8V_2 1 2
PR126

NC

NC

4
3
2
1
0_0402_5%

10U_0805_10V4Z
1

PC76
PC75 23 22 DH_1.8V_1
1 2 DH_1.8V_2 +1.8V
10U_0805_10V4Z VLDOIN VBST 2.2UH_IHLP-2525CZ-01_8A_+-20%
2

24 21 LX_1.8V 1 2
VTT DRVH
C
+0.9VP PL13 1
C

5
6
7
8
1 VTTGND LL 20
DL_1.8V + PC78

D
D
D
D
PQ46 330U_D2E_2.5VM_R15
1

2 19 AO4712_SO8
PC79 VTTSNS DRVL 2

G
S
S
S
22U_0805_6.3VAM
2

3 18

4
3
2
1
GND PGND

22P_0402_50V8J
PR127
0_0402_5%

0.001U_0402_50V7M

1
20K_0603_1%
1 2 4 MODE CS 16

1
<7,13,14> V_DDR_MCH_REF

PC80
0.033U_0402_16V7K

14.3K_0603_1%
1

PC83

PR129
PR128
PC81

5 14

2
VTTREF V5FILT

4.7U_0805_10V4Z
2

2
1

2
PC82
6 TPS51116RGE_QFN24 13 PR130
COMP PGOOD 3_0402_5%

2
2 1 +5VALWP
+5VALW 8 VDDQSNS S5 11
PR131

Thermal pad
2 1 @0_0402_5%
SLP_S5# <26,40>
9 VDDQSET CS_GND S3 10
PR132
B

V5IN
B
2 1 0_0402_5%
SLP_S4# <26,40>
PR133
17

25

15
2 1 @0_0402_5%
SLP_S3# <26,29,32,33,37,39,40,47,49,50,51,52>
PR134
2 1 @0_0402_5%
SLP_S4# <26,40>

PR387
2 1 0_0402_5%
PM_SLP_M# <26,37,40,47,52>
1 2 +3VALW

1
@0.001U_0402_50V7M
PR294

@0.001U_0402_50V7M
100K_0402_5%
10K_0603_0.1%
1

PC84

1
PR135

PC85
2

2
1 2 1.8PGOOD <41>

2
PR317
0_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8V/0.9VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA3262P_DIS__M64
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 48 of 57
5 4 3 2 1
 8 7 6 5 4 3 2 1

+CPU_B+ PL15
FBM-L18-453215-900LMA90T_1812
1 2 B+

47U_25V_M
2200P_0402_50V7K

4.7U_1206_25V6K
0.01U_0402_50V4Z
H 1 H

PC148
10U_1206_25V6M
+
1

1
PC100

PC103
PQ50

PC101

PC102
5
SI7840DP_SO8 2

2
2

+CPU_B+
PR148
+5VS 0_0402_5% 4
2 1

BST_CPU1_2
BST_CPU1_1
2

1U_0603_10V6K
PR149

3
2
1
1
PC104
10_0603_5%

PC105

0.01U_0402_25V7K

2
PU18 0.22U_0603_16V7K
G 5 1 1 2 PL16 G
VCC BOOT
6 8 DH_CPU1 .36UH_MPC1040LR36_ 24A_20%
FCCM UGATE

1
PC106
2 7 LX_CPU1 1 2 +VCC_CORE
PWM PHASE

2
@4.7_1206_5%
3 4

2
GND LGATE

8
7
6
5

8
7
6
5
PR150

IRF7832Z_SO8

IRF7832Z_SO8

1
ISL6208CRZ-T_QFN8 10_0402_1%

D
D
D
D

D
D
D
D
+5VS

PQ52

PQ53
PR151 PC107

PR347
10K_0402_1% 0.22U_0603_16V7K

1
+3VS

10_0603_5%
1 2 2 1

G
S
S
S

S
S
S

2 2

@680P_0603_50V7K
1
2
3
4

1
2
3
4

2
PR152
PR153
1 5.11K_0402_1% 2 PR154 1

1
2
1U_0603_10V6K

@0_0402_5%

1
1

F PR155 F

PC190
PC108

1.91K_0603_1% VSUM VO
2

DL_CPU1

1
+VCCP
PGOOD_PU19 <37> +CPU_B+

PC109 +5VS
1

2 1 NTC
PR370
19

20

18

39

40

2200P_0402_50V7K
0.01U_0402_16V7K ISL6260CRZ-T_QFN40 PR157

4.7U_1206_25V6K
0.01U_0402_50V4Z
68_0402_5%
0_0402_5% PQ54
VSS

3V3
VDD

VIN

PGOOD
PR158 2 1 SI7840DP_SO8 1
2

1
PC110
1U_0603_10V6K
0_0402_5%

BST_CPU2_2
BST_CPU2_1

PC111

PC112
2 1 4 PC113
<4> H_PROCHOT# VR_TT#

1
10U_1206_25V6M

PC114
4

2
PR159 1 PWM1 2
2 3 RBIAS PWM1 27
147K_0402_1% PH2

2
E E
2 PR160 1 2 1 NTC 5
4.22K_0603_1% PC115 NTC PC116

3
2
1
2 1 470KB_0402_5%_ERTJ0EV474J 6 23 ISEN1 PU20 0.22U_0603_16V7K
SOFT ISEN1 PL17
5 VCC BOOT 1 1 2
0.015U_0402_16V7K PU19
2 PR1611 28 6 8 DH_CPU2 .36UH_MPC1040LR36_ 24A_20%
<5> CPU_VID0 VID0 FCCM UGATE
<5> CPU_VID1 2 PR162 1 0_0402_5% 29 VID1
0_0402_5% 2 PR163 1 30 26 PWM2 2 7 LX_CPU2 1 2 +VCC_CORE
<5> CPU_VID2 VID2 PWM2 PWM PHASE
<5> CPU_VID3 2 PR164 1 0_0402_5% 31 VID3

2
@4.7_1206_5%
0_0402_5% 2 PR165 1 32 3 4
<5> CPU_VID4 VID4 GND LGATE

8
7
6
5

8
7
6
5
2 PR166 1 0_0402_5% PR167

IRF7832Z_SO8

IRF7832Z_SO8
<5> CPU_VID5 33 VID5

1
0_0402_5% 2 PR168 1 34 22 ISEN2 ISL6208CRZ-T_QFN8 10_0402_1%

D
D
D
D

D
D
D
D
<5> CPU_VID6 VID6 ISEN2

PQ56

PQ57
0_0402_5% PR170 PC117

PR349
2 PR169 1 37 10K_0402_1% 0.22U_0603_16V7K

1
<5,7,25> H_DPRSTP# 0_0402_5% DPRSTP#
1 2 2 1

G
S
S
S

S
S
S
2 PR171 1 36 41

2 2
<7,26> DPRSLPVR DPRSLPVR CS_GND

@680P_0603_50V7K
1
2
3
4

1
2
3
4

2
2 PR172 1 499_0402_1% 1
D
<5> H_PSI# 0_0402_5% PSI# PR173 D
<37> PM_POK 2 PR174 1 2 24 5.11K_0402_1% 2 PR175 1

1
0_0402_5% PGD_IN FCCM
<26> CLK_EN# 1 2 38 PR177 @0_0402_5%

1
PR328 PD44 CLK_EN#
2 1

PC191
9,32,33,37,39,40,47,48,50,51,52> SLP_S3# +5VS
1 2 @1SS355_SOD323 35 0_0402_5% VSUM VO
VR_ON
1

<21,26,31,37,40,41,50> PWR_GD @100_0402_5% 2 1

PR178 12 25 DL_CPU2
0_0402_5% PC185 VSEN PWM3
2

PR318 @0.1U_0402_16V7K 13
<5> VCCSENSE @27.4_0402_1% RTN
2 1 PC118 21
+VCC_CORE ISEN3
2 1 2 1 11 VDIFF
PR179 PC119
@10_0402_1% 1000P_0402_50V7K 2 1
10 FB
1000P_0402_50V7K PR181
OCSET 7 2 1
9 11.5K_0402_1%
C <5> VSSSENSE COMP C
PR182 PC120 17 VSUM
VSUM
1.96K_0402_1%

PR319 180_0603_1% 1800P_0402_50V7K PR183 8 VW

1
@1000P_0402_50V7K

@27.4_0402_1% 2 1 1 2 2 1
PR185
DROOP

2 1 2 PR184 1 0_0402_5%
1.2K_0402_1%
DFB

1
VO

0.22U_0603_16V7K

PC122
4.53K_0402_1%

2
2
PR186

PC123

1 2 2 PR187 1
14

15

16

51K_0603_1%
1

PC124 PC121
2

1 2 0.022U_0402_16V7K
0.1U_0402_16V7K

220P_0402_25V8K PC125 VO
10KB_0603_5%_ERTJ1VR103J

2 1

1000P_0402_50V7K
1
PC126

PR188
2 1
1

B B
@1K_0402_1%

6.98K_0402_1% PR190 PR191

2

PH3

6.34K_0603_1% 1K_0402_1%
PR189

2 1 2 1

PR179,PR180 are for test need when M/B is without CPU

2

R1269,R1270 are same funtion with PR179,PR180

Layout Note: Use27.4 Ohm(PR318,PR319) routing for Vssense and PC127
Vccsense 2 1

330P_0402_50V7K

A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA3262P_DIS__M64
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 49 of 57
8 7 6 5 4 3 2 1
 5 4 3 2 1

PQ72 +5VS
+5VS PD20 NDS0610_NL_SOT23-3
+3VS CH751H-40_SOD323

S
1 2 1 2 1 3

1
+5VS
PR259 PD21
PR193

1
PU22A 1M_0402_1% CH751H-40_SOD323

G
2
8

1U_0805_25V4Z
PR194 PR192 1 2

PC128
3 330K_0402_5% PR256 133K_0402_1%

P
D D

2
+ 100K_0402_5% PR257
1 0 2 1
P4

220K_0402_5%
2 10K_0402_5%

2
-
G

220K_0402_5%
PU22B PU21B PU21A 10K_0402_5%
PR197

2
2

0_0402_5%

0_0402_5%
LM358A_SO8 5 3

P
4

2
+ +

1
PR196

PR195
1 2 5 + O 7 O 1

PR251

PR252
6.81K_0402_1% 7 6 2
0 - -

G
1 2 1 2 6 PR208

2
PR199 PR200 - LM393M_SO8 LM393M_SO8 10_0402_5%
1

4
10K_0402_1% 100K_0603_0.5% PR201

2
1
2K_0402_5%
LM358A_SO8 1 2

2
PR202
0_0402_5% 1 2

80.6K_0402_1%
1U_0805_50V4Z

PR203
PQ70
1

PC130

0.01U_0402_16V7K
1 2 200K_0603_1% LX_5V <46>

MMBT3906_SOT23
DTA144EUA_SC70

PR205
2
PC129 VIN
2

1
PQ58
39.2K_0402_1%

PC131
0.027U_0603_16V7K

2
3
7.87K_0402_1%
E
3 1

2
B
2

2
PR206

PR260
PR207 PD28

47K
C
3.9K_0402_5% 1SS355_SOD323

47K
1
PU23

1 2

1 2

1
PD22
D @CH751H-40_SOD323
4 REF CATHODE 3

1
2 1 2 PR254
PR211

215_0603_1%
PR210
2 G PWR_GD <21,26,31,37,40,41,49> 150K_0402_5% PR253
NC

PQ73

1SS355_SOD323
0.1U_0402_16V7K

210K_0402_1%

RHU002N06_SOT323
S 1 2 OCP# <4,26>

3
1

2
PC132

5 1 0_0402_5%

2 2
ANODE NC

PD24
C C

2
2

1
APL1431LBBC_SOT23-5 D

470K_0402_5%
2 PQ60 PD27 ADP_SIGNAL

1
G 1SS355_SOD323 +3VS
RHU002N06_SOT323
1

PR215
S PR255 PD26

1
1
PR212

1
PR261 <39> ACOCP_EN# PQ71 D

RHU002N06_SOT323
0_0402_5% 1 2 1 2

1
B+ 1M_0402_1% 2
G
2

PQ61 1K_0402_5% 1SS355_SOD323

S

3
1

C MMBT3904_SOT323
2 CFET_B <44,45>
1

1
<29,37,44,45,46> ADP_PRES B D D D PQ74
RHU002N06_SOT323

<29,37,44,45,46> ADP_PRES I_A# <44> ADP_PRES <29,37,44,45,46>

PR217 E 2 2 2
3

PQ113

47.5K_0402_1% G G G
1 2 PQ92 S S S RHU002N06_SOT323
3

1
RHU002N06_SOT323
PR265
PQ62
47K_0402_5%
NDS0610_NL_SOT23-3
ADP_SIGNAL PD25

2
3900P_0402_50V7K
3.9K_0402_5%
S

3 1 2 1

1
1

PR214
VIN 1SS355_SOD323

PC147
G
2
1

VIN
1

PR223 +3VL 2

1
137K_0402_1% PR224 +3VS
B 226K_0402_1% B

1
PC146
2

2
8

PU25A 1U_0603_10V6K PC133

2

1
0.1U_0603_16V7K PR219 +5VS
3
P

PR216

2
+ PR221 1M_0402_5% PR218
O 1
2 10K_0402_5% 2 1 1 2 10K_0402_5%
-
1

PR236 LM393M_SO8 PR220

4

2
470K_0402_5%

8
100K_0402_1% 10K_0402_5% PU24A
+3VS
1 2 3

P
ADP_ID <37> ACN <44> + ADP_PS0 <37>
1
2

PR229 O
2 -

G
1M_0402_5% <26,29,32,33,37,39,40,47,48,49,51,52> SLP_S3# BATCAL# <44>
1 2 PR222 LM393M_SO8

4
<44> SRSET 71.5K_0402_1% +3VS

2
1

VIN PR238 D PR225

2
PR235 1M_0402_5% 2 PQ95 @100K_0402_5% PR226 +5VS

1
10K_0402_1% VIN G RHU002N06_SOT323 1M_0402_5%
1 2
1

1
+3VL S 1 2
3

PR258 PR228 PR227

2

29.4K_0402_1% PU25B 21K_0603_1% PR232 10K_0402_5%

1

8
5 PR230 21K_0603_1% PU24B
P

2
+ 47K_0402_5%
7 1 2 5

P
2

1 2
O PR231 PR233 +
6 - O 7
1

D 220K_0402_5% 100K_0402_5% C 6 ADP_PS1 <37>

2

G
47K_0402_5%

2 LM393M_SO8 1 2 2 PQ63 PR234

4

2
1

G B MMBT3904_SOT323 3.48K_0402_1% LM393M_SO8

ADP_EN <37>

4
1

D
0_0402_5%

PR237

S PQ65 E
3

A A
1
PR240

@RHU002N06_SOT323 2 PQ64

2
PR241 G RHU002N06_SOT323
1

220K_0402_5%

10K_0402_1% S
2

PD23
2

PR239
2

1 2 Security Classification Compal Secret Data Compal Electronics, Inc.

2

1SS355_SOD323 Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ADP_OCP
ADP_EN# <44> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64
2005.8.20 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 50 of 57
5 4 3 2 1
 5 4 3 2 1

B+_VGA

PL18
FBM-L11-322513-151LMAT_1210
B+ 2 1

1M_0402_5%
10U_1206_25V6M

4.7U_1206_25V6K
1

1
+5VALW

PC152

PC153

PR351
2

2
D D

2
1

2
PC159
PR350 1000P_0402_50V7K

5
6
7
8
0_0402_5% PD43
1 2 1SS355_SOD323-2 PQ78

D
D
D
D
<26,29,32,33,37,39,40,47,48,49,50,52> SLP_S3#

VGA_BOOT 1
AO4468_SO8

1
1 2 VGA_BOOT1 1 2 PC151

1
+5VALW PR393 PR346 0.1U_0402_16V7K

G
S
S
S
PC155 @100K_0402_5% 0_0402_5%
@0.1U_0402_16V7K

4
3
2
1
1

2
PR367 VGA_UG
+5VALW 1UH_IHLP-2525CZ-01_11A_+-20%

16

15

14

13
10_0402_5%
PU29
VGA_LX 1 2

EN/PSV
TON

NC

BST
2
2 VDD_CORE
VCCA

330U_D2E_2.5VM_R9
12 PL19 1
DH

@SX34_SMA
PR345 6 VSSA

5
6
7
8

1
+

PC157
470K_0402_5% PC169 11
LX

PD29
1U_0603_10V6K 17 PR353 PQ79

D/K
D/K
D/K
D/K
2
TPAD
7 10 1 2 AO4712_SO8
2
PGND ILIM 19.6K_0402_1% 2

S/A
S/A
S/A
4 9 1 2

2
PGD VDDP

G
VOUT
PC168
1U_0603_10V6K

NC

FB

DL

4
3
2
1
VGA_LG

8
C C

SC411MLTRT_MLPQ16_4x4

VGA_VCORE
+5VALW PR354
1 2

10K_0402_1%

1
2 1

PR390 PR392 PC154

100K_0402_5% 24.9K_0402_1% 33P_0402_50V8J

1
2

2
RHU002N06_SOT323

1
PQ121 D PR355
2 9.76K_0402_1%

2
G
3 S
1

D
PR391
1 2 2
<19> POW_SW G
10K_0402_5%
S PQ120
3

RHU002N06_SOT323
1

PC196
B 1U_0603_10V6K B
+5VALW
2

+3VS

1
For M64S +1.8V
PC160
POW_SW= "0": VDD_CORE=1.2V

1
1U_0603_10V6K

2
"1": VDD_CORE=1V PR356
10K_0402_1%

6
PU31

1
(For M62S 5

VCNTL
2
VIN PC161
7
POW_SW= "0": VDD_CORE=1.1V POK
9 10U_1206_6.3V6M

2
"1": VDD_CORE=0.95V VIN

PR355 change to 11K and PR392 change to 33.2K) VOUT 3

<26,29,32,33,37,39,40,47,48,49,50,52> SLP_S3# 1 2 8 EN VOUT 4 PCIE_1.2V

PR357

GND

1
0_0402_5% 2
FB PC162

1
PC171 APL5913-KAC-TRL_SO8 22U_0805_6.3VAM

2
1
@0.1U_0402_16V7K

1
2
PR358
49.9K_0402_1% PC164

2
47P_0402_50V8J

2
1
SET TO 1.2V FOR M62S,M71S (R342= 49.9K)
SET TO 1.1V FOR M72S (R342 = 39.2K)
PR359
A 100K_0402_1% A

2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VDD_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 51 of 57
5 4 3 2 1
 5 4 3 2 1

B+_VGA
+5VALW

10_0402_5%
1

1
PR142
PR368

4.7U_0805_25V6K

4.7U_0805_25V6K
D 1M_0402_5% D

1
2

PC89

PC199
2

2
1
PC95 PD42
PD45

1
1000P_0402_50V7K 1SS355_SOD323-2
1 2

2
1SS355_SOD323

BOOT
1 2 PR136
<26,29,32,33,37,39,40,47,48,49,50,51> SLP_S3# PR249 1 2 BOOT1 1 2 UG

1
47K_0402_5% 0_0402_5% PQ47
PC90 1 8
PC186 0.1U_0402_16V7K D2 G2

16

15

14

13
2 7

2
+5VALW 47P_0402_50V8J PU28 D2 D1/S2/K
3 G1 D1/S2/K 6
4 5

EN/PSV
TON

NC

BST
S1/A D1/S2/K
2 VCCA
12 +1.05V_VCCP
DH

1
6 SI4914_SO8
PR137 PC97 VSSA
LX 11
@10K_0402_5% 1U_0603_10V6K 17 PR141

2
TPAD LX6269
7 PGND ILIM 10 1 2 1 2
18.2K_0402_1% PL14
2

220U_B2_2.5VM
4 9 3.3UH_SIQB74-3R3RF_4.8A_30% 1
<41> VCCP_POK PGD VDDP

VOUT

PC142
+

NC

FB

DL
PC91
1U_0603_10V6K

2
2

C C
SC411MLTRT_MLPQ16_4x4
LG

PR144
1 2
11K_0402_1%

1 2

PC96
33P_0402_50V8J

1
PR147
10K_0402_1%

+5VALW

B +3VALW B

1
PC139 +1.25VM

1
1U_0603_10V6K

2
PR293
@10K_0402_1%

6
PU27

1
5

VCNTL
2
<41> M_PROK 1 2 7
VIN PC138
PR323 POK 10U_0805_6.3V6M
9

2
0_0402_5% VIN

VOUT 3

<26,37,40,47,48> PM_SLP_M# 1 2 8 EN VOUT 4 +1.05VMP

PR292

GND

1
0_0402_5% 2
FB PC141
APL5915KAI-TRL_SO8 22U_0805_6.3VAM

2
1

1
PR247
47K_0402_1%

2
PC140

2
27P_0402_50V8J

1
PR248
150K_0402_1%

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.25VMP/+1.05V_VCCP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 52 of 57
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) for Power Circuit

Request
Item Page# Title Date Owner Issue Description Solution Description Cut in
43 DCIN/
D BATTERY CONN D
1 2006/09/07 HP R.L. Change charger control from HW to FW All the related components DB1B
44 Charger
50 ADP_OCP
2 50 ADP_OCP 2006/10/12 HP R.L. Identify 65W adapter as "light" Change PR223 from 180K to 147K DB2

VDD_CORE 2006/10/12 HP R.L. Change VGA chipset from ATi M62S to M64S Change PR355 from 11K to 9.76K
3 51 /PCIE_VDD Change PR392 from 33.2K to 24.9K DB2

+1.25VMP/ Change PR249 from 0 to 47K

4 52 +1.05V_VCCP 2006/10/12 HW For HW's requirement, fine tune +1.05V_VCCP sequence Add PC186 as 47pF
Tony J DB2
Install PD45

VDD_CORE Change PR358 from 47K to 49.9K

5 51 /PCIE_VDD 2006/10/12 PWR Fine tune PCIE_VDD Change PR359 from 150K to 100K DB2
Francis H
VDD_CORE SI
2006/11/08 HW
6
51 /PCIE_VDD Fine tune the GPU "Power Play" sequence Add PC196 as 1uf
Tony J
8
51 VDD_CORE SI
/PCIE_VDD 2006/11/08 HW Fine tune the power sequence of PCIE_VDD Change PU31 pin5, 9 source from VDD_MEM18 to +1.8V
C
Tony J C
9 Base on "Energy STAR" spec, reduce S5 and S3
44 Charger 2006/11/08 PWR power consumption (AC mode) Uninstall PQ11 SI
Francis H
10 48 1.8V/0.9V 2006/11/08 HP Add PM_SLP_M# sequence Add PR387 SI

+1.25VMP/ Change PR243 to 47K,

11 52 +1.05V_VCCP 2006/11/20 HW For HW's requirement, fine tune +2.5VS sequence Change PC170 to 0.1uF SI
Tony J

+1.25VMP/ HW Fine tune the +2.5VS power level to 2.57V (typ) Change PR244 from 13K to 13.7K SI2
12 52 +1.05V_VCCP 2007/2/28
Tony J

13 50 ADP_OCP 2007/2/28 HP R.L. System identity Change PR223 from 147K to 137K SI2

14 44 Charger 2007/3/1 PWR Reserve circuit for testing Energy STAR Reserve PR397, PR398, PR399 and PQ131 PV
Francis H Add PR396 as 0 ohm.

VDD_CORE PWR Change PQ78 from IRF7413Z to AO4468

B 15 51 /PCIE_VDD 2007/3/1 Francis H MOSFET change for M64s (original design is for M72) Change PQ79 from IRF8113 to AO4712 PV B

Change PR353 from 6.81K to 19.6K

Change PR210 from 422 to 215

Change PC129 from .22u to .027u
16 50 ADP_OCP 2007/4/12 HP R.L. Fine tune system OCP setting for battery spec Change PR203 from 604K to 200K MV
Change PC131 from .027u to .01u

44 Charger 1. Change PC14 from 10u_1206 to 4.7u_0805

46 3.3V/5V Add PC198 as 4.7u_0805
47 1.5VS/1.25VM 2. Change PC89 from 10u_1206 to 4.7u_0805 MP
+1.25VMP/ Add PC199 as 4.7u_0805
48 1.8V/0.9V 2007/7/30 HP R.L. Change some MLCCs size from 1206 to 0805 3. Change PC15, PC19, PC42 and PC58 from 4.7u_1206
17 51 VDD_CORE to 4.7u_0805
/PCIE_VDD 4. Change PC79, PC141, PC162 and PC197
52 +1.25VMP/ from 22u_1206 to 22u_0805
+1.05V_VCCP 5. Change PC134, PC135 and PC138 from 10u_1206
to 10u_0805

18 44 Charger 2007/7/30 TI For TI's suggestion, add 4.7u at VCC pin Add PC200 as 4.7u_0805 MP
A A

Title
PIR
Size Document Number Rev

Date: Tuesday, August 21, 2007 Sheet 53 of 57

5 4 3 2 1
 5 4 3 2 1

Item Fixed Issue Reason for change PAGE Modify List M.B. Ver.

<2006.09.11> 1 Dseign issue (Lost VRAM RST pin) 20, 22 Add DRAM_RST# from VGA to VRAM 0.2

2
Dseign issue (LVDS channel error) 19 Swapped LVDS upper and lower channel 0.2

D D

Dseign issue (HSYNC & VSYNC error) 19 Swapped VSYNC & HSYNC each other 0.2
3

4
isolate ESD to CPU core via USB and 1394 conn's pin 34 Add R4, R73 and R56 0.2

5
Follow ATI design suggestion for VDDR4, VDDR5 21 change and reserve two jopens for +1.8VS and +3VS power rails 0.2

6
Follow ATI design suggestion for DPLL_VDDC 21 delete R1892 0.2

7
follow ATI power sequence 40 Add +1.25VS, +3VS, +5VS and VDD_MEM18 delay circuits. 0.2

<2006.10.14> 1 RGB signal EA failed and CRT display garbage 16, 19 Change CRT circuit from MAX9511 to RLC circuit. 0.3

RGB signal EA failed and CRT display garbage Change CRT circuit from MAX9511 to RLC circuit.
C C
39 0.3
2 Add Q/Switch circuit.

3 follow ATI power sequence 21 install R1898 aand C1605, uninstall R1897 0.3

4 Increase VDD_MEM18 via holes 23 VDD_MEM18 no power noise, remove 1206 size resister. 0.3

5 Cancel Kill switch function on Chimay 28 uninstall JP53, R1906, R1736 and Q136 0.3

6 change 1394 bus route on board 31 re-define JP13 pins' assignment 0.3

7 implement one 4MB SPI chip 36 add R1794, R1795, R1924 0.3

8 implement 30pins KBC connector 38 re-define KBC connector JP6 pins assignment 0.3

<2006.11.20> 1 HP request, support Penryn CPU 4 Add R23, R34 0.4

B B

2 For Intel ES2 Crestline thermtrip pin. 7 Add R2 0.4

3 For EMI request enable 27MHz_SSC 15 install R1687 0.4

For Intel ES2 NB 800/667M Hz issue 15 Add CLRP4, CLRP5 to select FSB speed. 0.4
4

5 For RTC Accuracy fail to change 25 Change C528, C516 to 15pf 0.4

6 For detect CPU and system power saving 26 Add some components 0.4

7 Solve auto-turn on 26 install R1590 pull up to +3valw, uninstall R1727 0.4

8 Enable ACBS (power management for NIC) 29 install Q102, uninstall R1612, Q104, Q105 0.4

Enable ACBS (power management for NIC) 30 Change R1639 value to 1.87k 0.4
9
A A

Security Classification Compal Secret Data

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title
HW PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 54 of 57
5 4 3 2 1
 5 4 3 2 1

Item Fixed Issue Reason for change PAGE Modify List M.B. Ver.

<2006.11.20> 10 Add Energy Star for CPU schematics reserve R1931, R1934, R1933, C1622, U88, U90, R43, 0.4
41
R46, R52, R53, C1623, D80

11 0.4
Enable ACBS (power management for NIC) 41 Change R1732 pin2 from +3VM_Lan to +3VM
D D

HP request 38 MDC power change to +3vs 0.4

12

13 Follow ATI power sequence

40 Install D77, C1617, change R1919 to 10K 0.4

<2007.01.25> For HP request 40 Add R1940 and pull up +3valw 0.5

1

2 For 3VL/VCC1_PWRGD glitch change 41 Add U5C and R1939 pull down 0.5

3 For KBC VCC2 connection to 3VS 37 install R1646, C75 0.5

4 For HP request 25 Add Q144 and R1935 instead of D75 0.5

For HP request to install BGA CRACK components 27

5 0.5
12

C
6 For solving Power wireset interfere Fan 38 change JP20 connector Footprint 0.5 C

7 For Intel Crestline thermtrip shutdowm 7 Reserve 0.1uf *1 for THERMTRIP# 0.5

8 For possible Leak during ACBS on PREP# signal 26 Change pull up to +3valw 0.5

For HP request to change Line-in BOM 32 R370, R369 change to 6.04k, R374, R375 change to 2.00k 0.5
9

10 For SIM connector supply chain 31 SIM connector footprint change 0.5

11 For LMV331 supply chain, change to LMV393 41 change U76 & U86 to U91 0.5

12
For EMI changes for VGA CRT 16 Install C310,C313,C314,R542,R543,R544 0.5
B B

13 For EMI changes for LED_LAN_DOCK 33 Add R1805,R1806 0.5

14 For HP request, change R1780.1 to UIM_PWR 31 change R1780.1 to UIM_PWR 0.5

15 For Intel NIC crystal design 29 Add R1936 30ohm value

0.5

16 For G-Sensor LED 26 HDD_HALTLED (R15) pull down 0.5

Remove pull ups for STP_PCI# and STP_CPU# 0.5

17 For Intel new design 26
uninstall R1581, R1580

0.5
18 For HP request 36 Add CLRP6 for SPI ROM
A A

19 For VGA wavy isse 17 Change C586 to 10uf_1206, add C1629 10uf_1206 0.5

Security Classification Compal Secret Data

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title
HW PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 55 of 57
5 4 3 2 1
 5 4 3 2 1

Item Fixed Issue Reason for change PAGE Modify List M.B. Ver.

<2007.02.14> Add FP power supply circuit for Vista reserve R1931, R1934, R1933, C1622, U88, U90, R43, 0.4
1 41
R46, R52, R53, C1623, D80

0.4
2 Enable ACBS (power management for NIC) 41 Change R1732 pin2 from +3VM_Lan to +3VM
D D

3 HP request 38 MDC power change to +3vs 0.4

Follow ATI power sequence

4 40 Install D77, C1617, change R1919 to 10K 0.4

5 For HP request 40 Add R1940 and pull up +3valw 0.5

6 For 3VL/VCC1_PWRGD glitch change 41 Add U5C and R1939 pull down 0.5

7 For KBC VCC2 connection to 3VS 37 install R1646, C75 0.5

8 For HP request 25 Add Q144 and R1935 instead of D75 0.5

For HP request to install BGA CRACK components 27

0.5
12

C
For solving Power wireset interfere Fan 38 change JP20 connector Footprint 0.5 C

For Intel Crestline thermtrip shutdowm 7 Reserve 0.1uf *1 for THERMTRIP# 0.5

For possible Leak during ACBS on PREP# signal 26 Change pull up to +3valw 0.5

For HP request to change Line-in BOM 32 R370, R369 change to 6.04k, R374, R375 change to 2.00k 0.5
9

10 For SIM connector supply chain 31 SIM connector footprint change 0.5

11 For LMV331 supply chain, change to LMV393 41 change U76 & U86 to U91 0.5

12
For EMI changes for VGA CRT 16 Install C310,C313,C314,R542,R543,R544 0.5
B B

13 For EMI changes for LED_LAN_DOCK 33 Add R1805,R1806 0.5

14 For HP request, change R1780.1 to UIM_PWR 31 change R1780.1 to UIM_PWR 0.5

15 For Intel NIC crystal design 29 Add R1936 30ohm value

0.5

16 For G-Sensor LED 26 HDD_HALTLED (R15) pull down 0.5

Remove pull ups for STP_PCI# and STP_CPU# 0.5

17 For Intel new design 26
uninstall R1581, R1580

0.5
18 For HP request 36 Add CLRP6 for SPI ROM
A A

19 For VGA wavy isse 17 Change C586 to 10uf_1206, add C1629 10uf_1206 0.5

Security Classification Compal Secret Data

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title
HW PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 56 of 57
5 4 3 2 1
 5 4 3 2 1

Item Fixed Issue Reason for change PAGE Modify List M.B. Ver.

<2007.08.02>
1 Solve VGA can not thermal shutdown and KB dissolve 4 Add R229 (non-install) and contact to THERM#_VGA 1A

2 prevent Cap crack to change Cap size 17 C1629 & C586 size change from 1206 to 0805 1A
D D

3 Solve VGA can not thermal shutdown and KB dissolve 23 Add R1906 (non-install) and R1896 install 1A
Add Q30 & Q31

4 Prevent GPIO33 leakage 25 Change Q144 to CHP202U_SC70 1A

C C

10

11

12

B B

13

14

15

16

17

18

A A

19

Security Classification Compal Secret Data

Issued Date 2006/09/25 Deciphered Date 2006/09/25 Title
HW PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA3262P_DIS__M64 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, August 21, 2007 Sheet 57 of 57
5 4 3 2 1