ECE 127 HOMEWORK 3

Problem 1: Designing an FSM

Consider the design of a Moore-style FSM with a 1-bit input (x), and a 1-bit output (y). The FSM accepts
inputs one bit at a time and outputs a 0 until it sees the sequence 0101 (with no other bit values in
between). After seeing the second 1 in the sequence it outputs a 1 and then starts over.
(a) Draw the state transition diagram. Label all nodes and arcs.
(b) Derive the next state logic and the output logic equations.

Problem 2: Implementing an FSM

Consider the state transition diagram shown below:

(a) Write the Verilog behavior description for the corresponding circuit.
(b) Draw the circuit diagram for one-hot encoded implementation. (You may assume that flip-flops have
both "set" and "reset" inputs, but you must label which one you would use for each flip-flop.)

Problem 3: Converting from Mealy to Moore Style

Convert the Mealy-style state transition diagram to a Moore-style.

Problem 4: Verilog Code for a Vending Machine

The State Diagram of the Vending Machine is given here. It has the following states:

State 1: Reset
State 2: Five
State 3: Ten
State 4: Fifteen
State 5: Twenty
State 6: Twenty Five
The next state is the RESET state again. The diagram is given below and is self-explanatory.
Whenever a coin is dropped, the system jumps to the next state. For example, if the coin dropped from
the RESET State is a NICKEL, then the system jumps to the FIVE State. Otherwise, the system stays in the
present state. When the system gets an extra amount, it goes back to the RESET State and the difference
is given back to the user. Write the Verilog behavior description of this vending machine system.