Experiment no.

:3
Aim : To design and simulate 4 bit parallel adder in Xilinx platform.

Tools required : Xilinx ise 14.7

Theory :

A Parallel Adder is a digital circuit capable of finding the arithmetic sum of two binary numbers that
is greater than one bit in length by operating on corresponding pairs of bits in parallel. It consists of full
adders connected in a chain where the output carry from each full adder is connected to the carry input
of the next higher order full adder in the chain. A n bit parallel adder requires n full adders to perform
the operation. So for the 4-bit number, 4 full adders are needed. Parallel adders normally incorporate
carry lookahead logic to ensure that carry propagation between subsequent stages of addition does not
limit addition speed.

Fig 3.1: 4-bit Parallel Adder using full adder circuit diagram.

Source Code :

module parallel_adder(a,b,cin,cout,s);
input [3:0]a,b;
input cin;
output cout;
output [3:0]s;
wire ca1,ca2,ca3;
FA f1(a[0],b[0],cin,ca1,s[0]);
FA f2(a[1],b[1],ca1,ca2,s[1]);
FA f3(a[2],b[2],ca2,ca3,s[2]);
FA f4(a[3],b[3],ca3,cout,s[3]);
endmodule
module FA(a,b,c,ca,sum);
input a,b,c;
output ca,sum;
wire w1,w2,w3;
and(w1,a,b);and(w2,b,c);and(w3,a,c);
xor(sum,a,b,c);
or(ca,w1,w2,w3);
endmodule

Test Bench :
module fa;
reg [3:0] a;
reg [3:0] b;
reg cin;
wire cout;
wire [3:0] s;
parallel_adder uut (
.a(a),
.b(b),
.cin(cin),
.cout(cout),
.s(s));
initial begin
a = 1;b = 2;cin = 1;#100;
a = 4;b = 6;cin = 0;#100;
a = 6;b = 8;cin = 0;#100;
a = 8;b = 10;cin = 0;#100;
a = 5;b = 9;cin = 1;#100;
a = 2;b = 8;cin = 1;#100;
end
endmodule

RTL Schematic :

Fig 3.2: RTL schematic of 4-bit parallel adder using full adder.

Output Waveform :

Fig 3.3: 4-bit parallel adder output waveform.

Results : Hence, the 4-bit parallel adder was simulated and implemented in Xilinx platform and also the
output waveform was observed.