9/21/2019 ATPG Run No SPF

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9/21/2019 ATPG Run No SPF

ATPG Run No SPF

set_messages -log mylog -replace Read Netlist, Library
# Read in the netlist library and
# Verilog library Build ATPG Model
read_netlist -library library/*.v
read_netlist design.v Add Clock, PI
# Build ATPG Model Constraints
run_build_model DESIGN_TOP
Run DRC
# Add Clocks and PI Constraints
add_clocks 0{clk}-shift \ Add Faults, Run ATPG
-timing{100 50 80 40}
add_clocks 1{rst}-timing{100 50 80 40}
Write Test Patterns
add_scan_enable 1 test_se
add_scan_chains c1 test_sis data_out
add_pi_constraints 1 test_mode

# Set up and run DRC

set_drc stil_procedures.spf
run_drc

# Add faults and run ATPG

add_faults -all
run_atpg -auto

# Write the patterns

write_patterns DESIGN.stil -format STIL \
-replace
write_patterns DESIGN.bin -replace

Copy Script

For more information, see Basic ATPG Flow

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