CAD for VLSI 1

Homework #1

1. Install and run iverilog and GTKWave for the input files listed below:
1. fibonacci.v and fibonacci_tb.v
2. halfadder.v . Write your own testbench.
3. fulladder.v . Write your own testbench. Write brief notes on how you think
simulation works in each of these cases. Note down problems that you face in installing and
using the tool. Write a 2 page report about your experiences in using the tools. Turn in a
neatly hand-written or a printed copy. Do not attach waveforms or Verilog source code.
fibonacci.v

//Fibonacci sequence is 0 1 1 2 3 5 8 ...... 233

//active low reset, otherwise count on positive trigger of clk
module fibonacci(output [7:0]fibseq, input rst, input clk);

wire [7:0] fibseq;

reg [7:0] Reg1;
reg [8:0] Reg2;

//bit pattern is printed in decimal for convenience

initial
begin
$monitor($time , " : FibSeq = %d ", fibseq);
end

always@(posedge clk or negedge rst)

begin
//on reset, initialize reg1 to 0
if(rst == 1'b0) begin
Reg1<=8'b00000000;
Reg2<=8'b00000001;
end
else if(clk==1'b1)
begin
//Reg1 and Reg2 will infer registers
Reg1 <= Reg2;
Reg2 <= Reg2 + Reg1;
if(Reg2[8] == 1)
$display("\t\tout of range ERROR");
end
end

//Copy Reg1 to output

assign fibseq = Reg1;
endmodule
fibonacci_tb.v

`include "fibonacci.v"
//Test Bench
module fibonacci_tb; // stimulus for Fibonacci generator
reg clk, rst;
wire[7:0] fibseq;

// Instantiating the Fibonacci Module of fibo.v

fibonacci u1(fibseq,rst,clk);

initial begin
#0 clk=1'b0;
rst=1'b1;
#12 rst=1'b0;
#10 rst=1'b1;
#150 $finish; //at time=172 stop simulation
end

// clk that toggles for every 5 units of time

always
#5 clk=~clk;

//monitor the outputs

initial
begin
$dumpfile("fibonacci.vcd");
$dumpvars;
$dumpon;
#172 $dumpoff;
end

endmodule
halfadder.v
module halfadder (sum, cout, a, b);
//port list does not differentiate inputs and outputs
//do so now

input a,b;
output sum,cout;

//concurrent signal assignment on sum

//uses a dataflow expression

assign sum = a ^ b;

//AND primitive is used here

//implies structure
and(cout, a, b);
endmodule
fulladder.v

module fulladder (output sum, output cout, input a, input b, input cin);
//port list differentiates inputs and outputs

//some tools expect the inputs and outputs to be declared as wires too

wire a,b,cin,sum,cout;

wire s1;

//sum is generated as (a xor b) xor cin

//s1 is a wire that stores a xor b

xor(s1,a,b);
xor(sum,s1,cin);

//a concurrent signal assignment statement takes care

//of the assignment on cout

assign cout = (a&cin) | (b&cin) | (a&b);

endmodule