DIGITAL SYSTEMS DESIGN Charles H. Roth, Jr.DIGITAL SYSTEMS DESIGN Usinc VHDL°® Charles H. Roth, Jr The University of Texas at Austin ews Publishing Company P An International Thomson Publishing Company Boston » Albany * Bonn » Cincinnati * London » Madrid » Melbourne Mexico City * New York « Paris * San Francisco * Tokyo » Toronto * WashingtonPWS Publishing Company 20 Park Plaza, Boston, MA 02116-4324 Copyright © 1998 by PWS Publishing Company, a division of Intemational Thomson Publishing Inc. All rights reserved. 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Polanco London WCIV 7AA 11560 Mexico C.F, Mexico England Intemational Thomson Publishing GmbH ‘Thomas Nelson Australia Konigswinterer Strasse 418 102 Dodds Street 53227 Bonn, Germany ‘South Melbourne, 3205 Victoria, Australia Imermational Thomson Publishing Asis 21 Henderson Road Nelson Canada +#05-10 Henderson Building 1120 Birchmount Road Singapore 0315 Scarborough, Ontario Canada MIK 5G4 International Thorsson Publishing Japan Hirakawacho Kyowa Building, 31 Printed and bound in the United Staies of America. 22-1 Hirakawacho Chiyoda-ku, Tokyo 102 98 99 00 01-10 9 8765432 Japan Library of Congress Cataloging-in-Publication Data Roth, Chatles H, Digital system design using VHDL /by Charles H. Roth Pom. ISBN 0-534-95099-X (alk. paper) 1, Electronic digital computers—Cirevits—Design and construc. tiog—Daua processing. 2. VHDL Hardware description language) 3. ‘System design—Data processing, I. Tile, TK7S884.R667 1997 621.392—de21 97-24246 cleCONTENTS PREFACE CHAPTER 1 CHAPTER 2 REVIEW OF LOGIC DESIGN FUNDAMENTALS 1.1 Combinational Logic 1.2 Boolean Algebra and Algebraic Simplification 1.3 Karnaugh Maps 1.4 Designing with NAND and NOR Gates 1.5 Hazards in Combinational Networks 1.6 Flip-flops and Latches 1.7 Mealy Sequential Network Design 1.8 Design of a Moore Sequential Network 1.9 Equivalent States and Reduction of State Tables 1.10 Sequential Network Timing 1.11 Setup and Hold Times 1.12 Synchronous Design 1.13 Tristate Logic and Busses INTRODUCTION TO VHDL 2.1. VHDL Description of Combinational Networks 2.2. Modeling Flip-flops using VHDL Processes 2.3 VHDL Models for a Multiplexerwv Contents CHAPTER 3 CHAPTER 4 CHAPTER 5 2.4 Compilation and Simulation of VHDL Code 2.5 Modeling a Sequential Machine 2.6 Variables, Signals, and Constants 2.7 Arrays 2.8 VHDL Operators 2.9 VHDL Functions 2,10 VHDL Procedures 2.11 Packages and Libraries 2.12 VHDL Model for a 74163 Counter DESIGNING WITH PROGRAMMABLE LOGIC DEVICES 3.1 Read-only Memories 3.2. Programmable Logic Arrays (PLAS) 3.3. Programmable Array Logic (PALs) 3.4 Other Sequential Programmable Logic Devices (PLDs) 3.5 Design of a Keypad Scanner DESIGN OF NETWORKS FOR ARITHMETIC OPERATIONS 4.1 Design of a Serial Adder with Accumulator 4.2. State Graphs for Control Networks 4.3 Design of a Binary Multiplier 4.4 Multiplication of Signed Binary Numbers 4.5 Design of a Binary Divider DIGITAL DESIGN WITH SM CHARTS. 5.1 State Machine Charts 5.2 Derivation of SM Charts 5.3 Realization of SM Charts 5.4 Implementation of the Dice Game 56 58 65 68 70 72 74 76 78 85 85 89 96 101 109 121 121 123 124 132 144, 161 161 167 178 180Contents v| CHAPTER 6 ‘CHAPTER 7 CHAPTER 8 5.5 Alternative Realizations for SM Charts Using Microprogramming 184 5.6 Linked State Machines 190 DESIGNING WITH PROGRAMMABLE GATE ARRAYS AND ‘COMPLEX PROGRAMMABLE LOGIC DEVICES 201 6.1. XILINX 3000 Series FPGAs 201 6.2. Designing with FPGAs 211 6.3 XILINX 4000 Series FPGAs 219 6.4 Using a One-Hot State Assignment 229 6.5 Altera Complex Programmable Logic Devices (CPLDs) 231 6.6 Altera FLEX 10K Series CPLDs 236 FLOATING-POINT ARITHMETIC 243 7.1. Representation of Floating-Point Numbers 243 7.2 Floating-Point Multiplication 244 7.3, Other Floating-Point Operations 259 ADDITIONAL TOPICS IN VHDL 265 8.1 Attributes 265 8.2. Transport and Inertial Delays 269 8.3 Operator Overloading 270 8.4 Multivalued Logic and Signal Resolution 272 8.5. IEEE-1164 Standard Logic 276 8.6 Generics 280 8.7 Generate Statements 282 8.8 Synthesis of VHDL Code 283 8.9 Synthesis Examples 289 8.10 Files and TEXTIO 295lw Conrents CHAPTER 9 VHDL MODELS FOR MEMORIES AND BUSSES 9.1 Static RAM Memory 9.2 A Simplified 486 Bus Model 9.3 Interfacing Memory to a Microprocessor Bus CHAPTER 10 HARDWARE TESTING AND DESIGN FOR TESTABILITY 10.1 Testing Combinational Logic 10.2 Testing Sequential Logic 10.3 Scan Testing 10.4 Boundary Scan 10.5 Built-In Self-Test CHAPTER 11 DESIGN EXAMPLES. 11.1 UART Design 11.2 Description of the MC68HCO5 Microcontroller 11.3 Design of Microcontroller CPU 11.4 Completion of the Microcontroller Design APPENDIX A VHDL LANGUAGE SUMMARY APPENDIX B BIT PACKAGE APPENDIX C TEXTIO PACKAGE APPENDIX D BEHAVIORAL VHDL CODE FOR M6805 CPU APPENDIX E M6805 CPU VHDL CODE FOR SYNTHESIS. APPENDIX F PROJECTS. "REFERENCES INDEX 303 303 316 325 339 339 344 347 351 361 373 373 387 394 411 419 425 435 437 443 453 459 463PREFACE This textbook is intended for a senior-level course in digital systetns design. The book covers both basic principles of digital system design and the use of 2 hardware description language, VHDL, in the design process. After basic principles have been covered, design is best taught by using examples. For this reason, many digital system design examples, ranging in complexity from 4 simple binary adder toa complete microcontroller, are included in the text. ‘Students using this textbook should have completed a course in the fundamentals of logic design, including both combinational and sequential networks. Although no previous knowledge of VHDL is assumed, students should have programming experience using @ modern higher-level {anguage such as Pascal or C. A course in assembly language programming and basic computer organization is also very helpful, especially for Chapters 9 and Il. Because students typically take their first course in logic design two years before this course, most students need a review of the basics. For this reason, Chapter 1 includes review of logic design fundamentals, Most students can review this material on their own, so it is unnecessary to devote much lecture time to this chapter. However, a good understanding of timing in sequential networks and the principles of synchronous desig is essential to the digital system design process. Chapter 2 introduces the basics of VHDL, and this hardware description language is used throughout the rest of the book. Additional features of VHDL are introduced on an as-needed basis, and more advanced features are covered in Chapter 8. From the start, we relate the constructs of VHDL to the corresponding hardware. Some textbooks teach VHDL. asa programming language and devote many pages to teaching the language syntax. Instead, our emphasis is on how co use VHDL in the digital design process. The language is very complex, so we dg not attempt to cover all its features. We emphasize the basic features that are necessary for digital design and omit some of the less-used features. VHDL is very useful in teaching top-down design. We can design a system at a high Jevel and express the algorithms in VDL. We can then simulate and debug the designs at this level before proceeding with the detailed logic design. However, no design is complete until it has actually been implemented in hardware and the hardware has been tested. For this reason, we recommend that the course include some lab exercises in which designs are implemented in hardware. We introduce simple programmable logic devices (PLDs) in Chapter 3 so that real hardware can be used early in the course if desired, The first part