Version 2.

4 (1) Standard Level

Comprehensive e
5 Days

OVERVIEW
Comprehensive e is a 5-day training course providing one-stop project preparation for engineers in the application
of e for verification. Including advanced material on best practice techniques, Comprehensive e provides all the
know-how needed for engineers to apply and exploit verification components confidently and effectively.
The course comprises 2 modules :

• Fundamentals of e based Verification (days 1-3) provides a good grounding in the e language and how to use
it for verification, including the use of coverage driven verification methodology. It combines tutorial
presentations with a progressive series of practical workshops based on a relevant sample verification problem.
• e for Advanced verification (days 4-5) builds on this language foundation and shows engineers how to
architect large, re-usable test environments using Verisity’s e Reuse Methodology (eRM) and eVC’s. It
includes an introduction to the special language features added to support eRM:
1. Packages for encapsulating and protecting verification IP
2. Sequences for structuring and coordinating complex stimulus
3. Ports to unify interaction between e and other languages including SystemC and HDLs

Because Doulos is an independent company, delegates can choose from a range of leading VHDL or Verilog
simulation tools for use during the workshops as well as full access and tuition in the use of the Verisity tools.
Workshops are based around carefully designed exercises to reinforce and challenge the extent of learning, and
comprise approximately 50% of class time.

WHO SHOULD ATTEND?

• Engineers who wish to become skilled in the practical use of e for verification of large programmable logic or
ASIC designs
• Engineers who are about to embark on their first e verification project or evaluation
• Engineers who have already acquired some practical experience in the use of e, but wish to consolidate and
extend their knowledge within a training environment

WHAT WILL YOU LEARN?

Fundamentals of e based Verification
• The essential syntax and semantics of the e language
• Best-practice techniques for linking your e verification code to an HDL simulation
• Design patterns and testbench architectures that are applicable to a wide range of verification problems
Continued…

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 Version 2.4 (1) Standard Level

WHAT WILL YOU LEARN…continued

• How to use e's functional coverage features to audit and improve the quality of verification
• Coverage driven verification methodology: using the design of coverage as a starting point for verification
planning
• How to write high quality e code that reflects best practice in the industry

e for Advanced Verification

• How to write, customise and use e verification components (eVCs) following Verisity's standard reuse
methodology, eRM
• Designing and managing sophisticated stimulus using the Sequence mechanism
• An overview of how to integrate C code, including SystemC, with your e verification environment
• An understanding of the command language for Specman Elite, and how to control the tool using scripts
• Techniques and tips for getting the best out of the e language and related tools

PRE-REQUISITES
• Delegates need some familiarity with digital hardware design, at least to the level covered in the Doulos course
Essential Digital Design Techniques. Familiarity with VHDL, Verilog or a software programming language,
such as that gained from attending the Doulos courses Comprehensive VHDL or Comprehensive Verilog,
is strongly recommended.
• Delegates attending only the module e for Advanced Verification must already have a working knowledge of
e. This module is suitable for delegates who have previously attended the Specman Elite Basic Training
from Verisity or the Doulos Fundamentals of e based Verification module.

COURSE MATERIALS
Doulos course materials are renowned for being the most comprehensive and user friendly available. Their style,
content and coverage is unique in the EDA training world and has made them sought after resources in their own
right. Course fees include:

• Fully indexed course notes creating a complete reference manual

• Workbook full of practical examples and solutions to help you apply your knowledge
• e Golden Reference Guide
• Tool tour guides (to support the tools and technologies of your choice)

Continued…

AmbLot Tél : +33(0)1 42 79 57 48 Email : info@amblot.com Site Web : www.amblot.com

 Version 2.4 (1) Standard Level

STRUCTURE AND CONTENT

Fundamentals of e based Verification (days 1-3)

Verification Methodology
Contrasting testbench automation with a traditional HDL verification methodology Š Benefits of using e in testbench
automation Š Designing an e test environment using coverage driven verification methodology

Getting Started with the e Language

Introducing e as a programming language Š Introducing e as a verification language Š Random stimulus generation
Š Data types, structs and lists Š Methods and procedural e code Š Extension of types, structs and methods Š
Random generation and constraints Š Generation order Š Constraining Lists Š Conditional inheritance using when

Interfacing to the HDL environment

Accessing HDL signals Š Computed signal names Š Units and linking to HDL hierarchy Š Using events to mark the
passage of simulated time Š Time Consuming Methods (TCMs) Š On-the-fly data generation Š Packing to map
structured data to HDL vectors

Checking the simulation results

Data checking Š Developing a scoreboard Š Temporal checking Š The temporal language Š Writing temporal
expressions Š Using events to capture complex temporal behavior Š Temporal and procedural assertions

Coverage
The need for functional coverage Š Coverage features in e Š What does functional coverage tell us? Š Using
coverage data to audit the quality of tests Š Coverage driven verification methodology: using coverage as the
starting point for verification planning

Advanced Verification using e (days 4-5)

eRM and eVCs
Techniques for creating re-usable verification IP Š Signal maps Š The eRM library and language extensions:
packages, sequences Š Structure of a typical eVC Š Naming conventions Š Configuring an eVC Š Writing a test
base

Sequences
Issues in the management of complex stimulus Š Using the Sequences mechanism to separate stimulus
generation from the driving of data into the DUT Š Using Virtual and Layered sequences to structure and co-
ordinate multiple streams of stimulus

Practical Implementation
Linking Specman to your HDL simulator Š Scripting Specman from the Unix/Linux command line Š The general C
interface Š Interfacing SystemC models to an e Test Environment

AmbLot Tél : +33(0)1 42 79 57 48 Email : info@amblot.com Site Web : www.amblot.com

 Version 2.4 (1) Standard Level

STRUCTURE AND CONTENT…Continued

Advanced e language topics
Non-determinism Š More on HDL signal interface – verilog and vhdl statements Š The Ports mechanism Š
Understanding aspect-orientation Š Programming productivity – keyed lists, references, type conversions,
polymorphism and other useful techniques

PROJECT SERVICES
Doulos has been a market leader in selling design know-how for over a decade, with project services playing a key
role delivering know-how directly into customer projects. With the unique mix of training and design experience,
Doulos aims to make your e project a success by offering a flexible range of services including test environment
design, eVC design, or 'Expert on-call' access to technical expertise at project critical times.

Specman Elite is a registered trademark and eRM a trademark of Verisity Design.

Verilog is a registered trademark of Cadence Design Systems Inc
SystemC is a trademark of the Open SystemC Initiative

AmbLot Tél : +33(0)1 42 79 57 48 Email : info@amblot.com Site Web : www.amblot.com