For low-power testing proposal.

1.2V IO for DDR2 It can be cancel for cost-down proposal

M11
U11
U12
T13
T16
T17
T18
T21

V11
V12
V13
U201-B
T11 H18

DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS DVDD12_EMI
R11 DVSS DVDD12_EMI H16
R2 DVSS DVDD12_EMI H15
G6 DVSS DVDD12_EMI G9 DVDD12_EMI
G7 DVSS DVDD12_EMI G11

C144
C142

C143

C151

C130
G14 DVSS DVDD12_EMI G13
G17 G15

4.7uF
DVSS DVDD12_EMI
G20 DVSS DVDD12_EMI G16
H10 G18

100nF
100nF
100nF

100nF
DVSS DVDD12_EMI
M20 DVSS DVDD12_EMI H8
N11 DVSS DVDD12_EMI E7
A19 DVSS DVDD12_EMI F7
A26 DVSS DVDD12_EMI F8
B4 DVSS DVDD12_EMI G8 check MSDC1/ 2 Bottom cap/ 1st cap group check MSDC1/ 2
B10 H11
E21
DVSS DVDD12_EMI
H13 IO power C115 close to pin E1 (150m il) IO power
DVSS DVDD12_EMI
F6
B12
DVSS
E1
C125 close to pin G26 (150m il)
DVSS DVDD28_MSDC1 VMC_PMU

VMC_PMU
B14 DVSS DVDD28_MSDC2 V1 VIO18_PMU
B17 DVSS DVDD28_BPI AD26 VIO18_PMU
B22 DVSS DVDD28_MD U25
B24 DVSS DVDD18_MSDC0 G26
C4 DVSS DVDD18_IO0 L26 VIO18_PMU
C8 DVSS DVDD18_IO1 Y26
C11 DVSS DVDD18_IO2 D1

C125

C115

C116

C117

C127

C128
C123

C122
C12 DVSS DVDD18_IO3 W1
C16 AG13

1.0uF
DVSS DVDD18_IO4
C17 DVSS

100nF

100nF
C18 R10

100nF

100nF

100nF

100nF

100nF
DVSS VCCK
C20 DVSS VCCK P9
C21 DVSS VCCK L11
C22 DVSS VCCK L12
C23 DVSS VCCK L13
C25 DVSS VCCK L14
D4 DVSS VCCK L15
D5 DVSS VCCK L16
VCCK
D7 DVSS VCCK L17
D9 DVSS VCCK M10

C104

C124

C131

C140

C152

C129

C136
D11 DVSS VCCK M18

1.0uF

1.0uF
D13 DVSS VCCK N10
D15 DVSS VCCK N18

100nF

100nF

100nF

10uF

10uF
D17 DVSS VCCK P18
D21 DVSS VCCK R9
D24 DVSS VCCK R18 Bottom cap 1st cap group
E5 DVSS VCCK T10
E8 DVSS VCCK U10
E10 DVSS VCCK V10
E18 DVSS VCCK_VPROC
F18 DVSS VCCK_VPROC N12 VPROC_PMU
P21 DVSS VCCK_VPROC N13
L10 DVSS VCCK_VPROC N14

C156

C157

C158

C148

C155

C132

C133

C134
VCCK_VPROC N15
AE5 N16

1.0uF

1.0uF
AVSS18_WBG VCCK_VPROC
V7 N17

C153

C154

C160

C161
AVSS18_WBG VCCK_VPROC

10uF
100nF
100nF

100nF
U7 P14

10uF

10uF
AVSS18_WBG VCCK_VPROC

1.0uF

1.0uF
W7 AVSS18_WBG VCCK_VPROC R15
Y7 AVSS18_WBG VCCK_VPROC P15

100nF

100nF
AB6 AVSS18_WBG VCCK_VPROC R14
AB8 AVSS18_WBG VCCK_VPROC R13
AC3 R12
AC5
AVSS18_WBG VCCK_VPROC
R16 Bottom cap 1st cap group
AVSS18_WBG VCCK_VPROC
AC7 AVSS18_WBG VCCK_VPROC R17
AD4 AVSS18_WBG VCCK_VPROC T14
AE3 AVSS18_WBG VCCK_VPROC T15
VCCK_VPROC U15
VCCK_VPROC U16
VCCK_VPROC V15
W20 V16
GND_VPROC_FB [3] To MT6323 GND_VPROC_FB pin
AVSS18_MD VCCK_VPROC HT1
U20 AVSS18_MD
V20
VPROC_FB [3] To MT6323 VPROC_FB pin
AVSS18_MD
V21 M15 HT2
AVSS18_MD DVSS
U21 AVSS18_MD DVSS N21 (1)VPROC_BB, GND pin of 1st cap group should be laid differential
W21 P10
Y20
AVSS18_MD DVSS
P11
pair with ground shielding rem ote sense to PMIC
AVSS18_MD DVSS
Y21 AVSS18_MD DVSS P12
AA21 AVSS18_MD DVSS P13 (2)R107 & R103 m ust be close to 1st cap group.
AB21 P16
U17
AVSS18_MD DVSS
P17
If you want to rem ove them ,
AVSS18_AP DVSS
U18 AVSS18_AP DVSS L18 please m ake sure the VPROC_FB/ GND_VPROC_FB m ust connect from 1st cap. group of VPROC
For low-power testing proposal. DVSS M14
A2 M13
It can be cancel for cost-down proposal R24
AVSS18_MEMPLL DVSS
M12
AVSS33_USB DVSS

VIO18_PMU
AE21 AVDD18_MD DVDD18_MIPITX L2 VIO18_PMU

AE19 AVDD18_AP

C111

C113
DVDD18_MIPIIO G1
VTCXO_PMU AE22 AVDD28_DAC For low-power testing proposal.
AE18 T24
A3
DVDD18_PLLGP AVDD33_USB
P26
VUSB_PMU It can be cancel for cost-down proposal

100nF
AVDD18_MEMPLL AVDD18_USB VIO18_PMU

100nF
VIO18_PMU

AC21 AVSS18_MD
AD22 H4
C112

VIO18_PMU AVSS18_MD DVSS18_MIPIIO

AG26 AVSS18_MD DVSS18_MIPIIO H5 For low-power testing proposal.
V17 J5

C120

C119
VTCXO_PMU

V18
AVSS18_AP DVSS18_MIPIIO
J7 It can be cancel for cost-down proposal
AVSS18_AP DVSS18_MIPIIO

1.0uF
C108

100nF
C109

C110

AA18 L4
VUSB_PMU

AVSS18_AP DVSS18_MIPITX
AB19 M7
VIO18_PMU

AVSS18_AP DVSS18_MIPITX

100nF
DVSS18_MIPITX M8
AF3 AVSS18_WBG DVSS18_MIPITX N3
100nF

100nF

100nF

AG1 AVSS18_WBG
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS

BBIC-MT6582E1_LPDDR2_105
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T12
M16
K21
M17
H12
J21
H20
H17
H14
V14

MT6582
HT3

C110 Close to MT6582

A2 should conne ct to C110.GND pin first,
than connect to GND by via

TITLE: LUA-U23 REV: V1.3

DOCUMENT NO.: 01_MT6582_POWER SIZED: A1

DEPARTMENT:
Hardware DEPT.
COMPANY:

DESIGNER: < DESIGNER> Last Saved Date: 2015/ 12/ 7 SHEET: 1 OF 13

 U201-D

For DDR3 ED29 C26 RDQ31 RCS0_B B7 ECS0_B [4]

U201-A ED24 C24 RDQ30 RCS1_B B6 ECS1_B [4]
ED31 A25 RDQ29
[11]TX_BBIP AF22 AB24 ED28 B25 RDQ28 RCKE B5
UL_I_P BPI_BUS0 AS M_VCTRL_A[11,12] DVDD12_EMI ECKE [4]
[11]TX_BBIN AF21 AB23 ED30 B26 RDQ27
UL_I_N BPI_BUS1
DVDD28_BPI AS M_VCTRL_B[11,12]
AG20 AD25 ED27 B23 RDQ26
[11]TX_BBQP UL_Q_P BPI_BUS2 AS M_VCTRL_C [11,12]
AF20 AC24 ED25 A23 RDQ25 RDQM0 D16
[11]TX_BBQN UL_Q_N BPI_BUS3 WG_GGE_PA_ENABLE [11,12] EDQM0 [4]
AC23 ED26 D25 RDQ24 RDQM1 D18 EDQM1 [4]
BPI_BUS4
AE25 ED20 A11 RDQ23 RDQM2 D10 EDQM2 [4]
BPI_BUS5
AD24 ED22 A14 RDQ22 RDQM3 D23

2
BPI_BUS6 EDQM3 [4]

2
AF16 ED23 A13 RDQ21
BPI_BUS7

8.2K
W_PA_B1_EN [12]

100nF
D12 F15

C205
AA17 ED21 RDQ20 RDQS0 EDQS0 [4]
BPI_BUS8 W_PA_B2_EN [12]
AD16 ED17 A10 RDQ19 RDQS1 F17 EDQS1 [4]
BPI_BUS9 W_PA_B5_EN
AG25 AC16 ED19 B13 F12

R209
[11]RX_BBIP DL_I_P BPI_BUS10 W_PA_B8_EN [12] RDQ18 RDQS2 EDQS2 [4]

1
AG24 AF15 ED18 C10 RDQ17 RDQS3 E20 EDQS3 [4]
[11]RX_BBIN DL_I_N BPI_BUS11

1
TD_PA_B40_EN
AG22 AC17 ED16 B11 RDQ16
[11]RX_BBQP DL_Q_P BPI_BUS12 SP3T_A
AG23 AB17 ED13 D22 RDQ15 RDQS0_B E15 EDQS0_B [4]
[11]RX_BBQN DL_Q_N BPI_BUS13 SP3T_B
AC15 ED11 B20 RDQ14 RDQS1_B E17 EDQS1_B [4]
BPI_BUS14 [2,4] EVREF
Y15 ED12 D20 RDQ13 RDQS2_B E12 EDQS2_B [4]
BPI_BUS15
A22 F20

2
ED15 RDQ12 RDQS3_B EDQS3_B [4]

2
DVDD18_IO4

8.2K
C19

2
ED10 RDQ11

1.0uF
C207
100nF
AG14 ED8 B19

C206
VM0 VM0 [12] RDQ10
AF14 ED9 A20 RDQ9 RCLK0_B F9 EDCLK_B [4]
VM1 VM1 [12]

R210
ED14 B21 RDQ8 RCLK0 E9

1
EDCLK [4]

1
AD14 ED4 B16

1
BSI_EN BSI-A_EN [11] RDQ7
AF25 Y14 ED5 A17 RDQ6
VBIAS BSI_CLK BSI-A_CK [11]
[11,12]
WG_GGE_PA_VRAMP AE24 AB14 ED7 B18 RDQ5
APC BSI_DATA0 BSI-A_DAT0 [11]
AA14 BSI-A_DAT1 [11]
ED6 A16 RDQ4 RA0 B8 EA0
BSI_DATA1
AE14 AC14 ED2 B15 RDQ3 RA1 B9 EA1
[11]DCOC_FLAG TXBPI BSI_DATA2 BSI-A_DAT2 [11]
ED3 C15 RDQ2 RA2 D8 EA2
ED1 D14 RDQ1 RA3 A8 EA3
ED0 C14 RDQ0 RA4 A7 EA4
RA5 C7 EA5
RA6 A5 EA6
BBIC-MT6582E1_LPDDR2_105
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[2,4] EVREF F16 VREF RA7 D6 EA7

MT6582
RA8 C6 EA8
RA9 A4 EA9

TP250
A1 TP_MEMPLL REXTDN B3

1
R221

BBIC-MT6582E1_LPDDR2_105
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MT6582 56_NF

2
SCL0 [2,6]
SDA0 [2,6]
SCL1 [2,7] U201-E
SDA1 [2,7]
SCL2 [2,9,10] [6] MIPI_TCP M3 TCP LCM_RST U3 LRSTB [6]
SDA2 [2,9,10] [6] MIPI_TCN M4 TCN DSI_TE Y3 LPTE [6]
[6] MIPI_TDP0 M1 TDP0 DISP_PWM AD9 PWM [6]
DTV_SPICS1 [6] MIPI_TDN0
M2 TDN0
DTV_SPIDI [6] MIPI_TDP1 P2 TDP1
DTV_SPIDO [6] MIPI_TDN1 N2 TDN1
DTV_SPICLK MIPI_TDP2 P1 TDP2
MIPI_TDN2 R1 TDN2
N5 TDP3
M5 TDN3
R205 0
EINT11_HP [5] K6 B2 CMMCLK
[7] MIPI_RCP RCP CMMCLK [7]
[7] MIPI_RCN K5 RCN CMPCLK B1 CMPCLK
[7] MIPI_RDP0 L3 RDP0
EINT14_CTP_RST [6] K3 E2

C201
[7] MIPI_RDN0 RDN0 CMDAT0 SW_FM
EINT_ACC [9] [7] MIPI_RDP1 K1 RDP1 CMDAT1 F2 S W_TV
EINT16_MC1INSI [7] MIPI_RDN1 K2 RDN1
EINT17_DTV J1
[7] MIPI_RDP2 RDP2_

NF
[7] MIPI_RDN2 J2 RDN2_
TP204 GPIO_CHG_EN [7] G2
URXD1 MIPI_RDP3 RDP3_
CHGFULL_EN [10] [7] H2 RDN3_
TP-0.8MM

TP203 UTXD1 KCOL0 [10] MIPI_RDN3

1K
TP202

R202 KROW0 F5
[7] MIPI_RCP_A RCP_A_
TP-0.8MM

1 R203 1K G5
KCOL1 [10] [7] MIPI_RCN_A RCN_A_
TP201

DTV_RST TP213 [7] MIPI_RDP0_A G4 RDP0_A

1 G3
KCOL2 [10] [2,3] SYSRST_B [7] MIPI_RDN0_A RDN0_A

AD10

AD13

AA13
AC11

AC10

AC13
J3

AE10

AB13

AE13
AF10
GPIO93_DRVVBUS [7] MIPI_RDP1_A RDP1_A

AA3

AD8

AA1
AA2

AD7

AG8
AC8
AC9
AB3

AE7

AB9

AE9
T23
R23

AF8

Y13
P23
P22
W2

U2
H3

Y2

V2
[6] UTXD0 U201-C
[7] MIPI_RDN1_A RDN1_A
MT6605 OSC_EN (SRCLKENAI) need to default low

SPI_CK
SPI_CS
SPI_MO
SPI_MI
UTXD0
URXD0

UTXD1
URXD1

UTXD2
URXD2

UTXD3
URXD3

SCL0
SDA0
SCL1
SDA1
SCL2
SDA2

EINT11

EINT14
EINT15
EINT16
EINT17
EINT18
EINT19
EINT20

KPCOL0
KPROW0

KPCOL1
KPROW1

KPCOL2
KPROW2
N1
for MT6605 TESTMODE boot-strap MIPI_VRT VRT
AF26

1
[11] CLK1_BB CLK26M BBIC-MT6582E1_LPDDR2_105
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R204
DVDD18_IO3 DVDD28_MD M25 SYSRST_B [2,3] MT6582
SYSRSTB
[3] RTC32K_CK
RTC32K_CK L25 RTC32K_CK
VGP2_PMU R213 0 1.5K
AF11 M24

C208
TESTMODE TESTMODE SRCLKENAI

NF
SRCLKENAI

2
R214 0 FSOURCE_P R5 N25
FSOURCE_P SRCLKENA SRCLKENA [3,11]
R215 NC R4 DVDD18_EFUSE
[3] WATCHDOG_B
N26 WATCHDOG PWRAP_SPI0_CSN J23 PMIC_SPI_CS [3]
H23 Close to MT6582
2

100nF_NC

TP209 PWRAP_SPI0_CK PMIC_SPI_SCK [3]

AF12 J24
C209

JTCK PWRAP_SPI0_MI
N137090735

VIO18_PMU PMIC_SPI_MISO [3]

AE12 JTDO PWRAP_SPI0_MO H22
TP210 PMIC_SPI_MOSI [3]
N137090736

PWRAP_INT H24 EINT_PMIC [3]

C208 are for ESD ehnhace proposal.
1

TP211 AG11
N137090737

JTDI
K26
TP212 AF13
AUD_CLK_MOSI
K25
AUD_CLK [3] It can be cancel for cost-down proposal
JTMS AUD_DAT_MISO AUD_DAT_MISO [3]
5.1K
N137090733

AUD_DAT_MOSI J25 [3]

4.7K

AUD_DAT_MOSI
1

+ / -1%
1
4.7K

USB_VRT P25 USB_VRT

GPIO12 AG10 GPIO12 [7]
R201 R26 AF9
[6] USB_DP USB_DP GPIO13 GPIO13 [7]
Close to MT6582 R25
R217

R218

[6] USB_DM USB_DM

90 Ohm SIM1_SCLK L21 SIM1_SCLK [3]
2
2

K23
differential SIM1_SIO
L23
SIM1_SIO [3]
SIM1_SRST SIM1_SRST [3]
SIM2_SCLK L20 SIM2_SCLK [3]
SIM2_SIO L24 SIM2_SIO [3]
[2,9,10] SCL2
N23 CHD_DP SIM2_SRST K24 SIM2_SRST [3]
< Parallel Cam ./ MIPI CSI Mux Table>
[2,9,10]SDA2 [3] CHD_DP
N24 CHD_DM
[3] CHD_DM
EINT0 W22 GPIO_0 [5] MIPI CSI IF Port Parallel Cam era IF Port
EINT1 V22 EINT1_A [9]
VIO18_PMU EINT2 AA24 EINT2_CTP [6]
V24 RDP2 CMDAT9
EINT3 EINT3_SD [8]
EINT4 W25 EINT4_SUB_CMPDN [7] RDN2 CMDAT8
EINT5 Y25 GPIO5_AUDIO_PA_EN
[ 5] RDP3 CMDAT5
EINT6 AA23 EINT6_SUB_CMRST [7]
DVDD28_MD RDN3 CMDAT4
EINT7 AA26 EINT7_NFC_VENB
V5 DVDD18_IO3 AA25
I2S_BCK EINT8 EINT8_NFC
4.7K
1

RCP_A CMDAT7
4.7K

U5 Y23
1

I2S_LRCK EINT9 EINT9_MAINCAM_RST [7]

W5 I2S_DATA_IN EINT10 Y22 EINT10_CMPDN [7] RCN_A CMDAT6
V23 RDP0_A CMVS YNC
PCM_CLK
R212
R211

PCM_RX V26 RDN0_A CMHS YNC

V25
2

PCM_SYNC
[3] BAT_ID_ADC AC19 U24 RDP1_A CMDAT3
AUX_IN0 PCM_TX
[6] LCD_ID_ADC AD19 AUX_IN1 RDN1_A CMDAT2
[2,7] SCL1
C202

C203

[2,7] SDA1 AF18 AUX_XP

CMDAT1 CMDAT1
AG17 AUX_XM CMDAT0 CMDAT0
AF17 DVDD28_MSDC2 DVDD28_MSDC1 DVDD18_MSDC0
100PF

AUX_YP
100PF

AG16 AUX_YM CMMCLK CMMCLK

CMPCLK CMPCLK
AG19
MSDC2_DAT3
MSDC2_DAT2
MSDC2_DAT1
MSDC2_DAT0

MSDC1_DAT3
MSDC1_DAT2
MSDC1_DAT1
MSDC1_DAT0

MSDC0_DAT7
MSDC0_DAT6
MSDC0_DAT5
MSDC0_DAT4
MSDC0_DAT3
MSDC0_DAT2
MSDC0_DAT1
MSDC0_DAT0

MSDC0_RSTB

REFP REFP
MSDC2_CMD

MSDC1_CMD

MSDC0_CMD
MSDC2_CLK

MSDC1_CLK

MSDC0_CLK

VIO18_PMU
AF19 AVSS_REFN
C204
0.1uF

BBIC-MT6582E1_LPDDR2_105
(S1+S2+S3+S4+S5+S6+S7+S8+S9)TRUED:PROJECTPROJECT!¤º³¡-p¹º-SP!MT6582PHONE20130205MT6582_MT6166_MT6627_MT6323_EMMC_LPDDR2_WTG_20130205-2.DSN

MT6582
T2
T1
T5
T6
R7
T3

D3
C2
D2
E4
C3
E3

F22
E23
F24
G24
E26
E25
G23
G22
D26
E24
G25
1

4.7K
1

4.7K

EMMC_RST [4]
EMMC_CMD
C213 Close to MT6582 [4]
NF
NF

NF

EMMC_CLK [4]
HT201

AF19 should connect to C213.2 first, EMMC_DAT0 [4]

R219

R220

EMMC_DAT1 [4]
2

R206
2

R207

R208

than connect to GND by via EMMC_DAT2 [4]

EMMC_DAT3 [4]
[2,6] EMMC_DAT4 [4]
SCL0
[2,6] EMMC_DAT5 [4]
SDA0
EMMC_DAT6 [4]
EMMC_DAT7 [4]

MC1CM [8]
MC1CK [8]
MC1DA0 [8]
MC1DA1 [8]
MC1DA2 [8]
MC1DA3 [8]

TITLE: LUA-U23 REV: V1.3

DOCUMENT NO.: 02_MT6582_BASEBAND SIZED: A1

DEPARTMENT:
Hardware DEPT.
COMPANY:

DESIGNER: < DESIGNER> Last Saved Date: 2015/ 12/ 7 SHEET: 2 OF 13

 Befo re yo u select BJT , please take po wer dissipatio n into co nsideratio n.
Refer to MT6 3 2 3 desig n no tice
U301

BGA145-5.8X5.8-0.4E0.25B(MT6323)

SPK_P K1 AU_SPKP
SPK_N L1 AU_SPKN
VBAT P1
Charg er C313 2.2uF
L2
VBAT_SPK

H1
GND_SPK AU_HSP AU_HSP [5]
AU_HSN G1 AU_HSN [5]

AU_HPL H4 AU_HPL [5,10]

MICBIAS0 F2 AU_MICBIAS0 AU_HPR J4 AU_HPR [5,10]
VBUS G2
MICBIAS1 AU_MICBIAS1

C312
1.0uF
[5] AU_VIN0_P E4 AU_VIN0_P ISINK0 E9
F4 AUDIO DRIVER C9
[5] AU_VIN0_N AU_VIN0_N ISINK1
ISINK2 E10
1. Close to Battery Connector. [5] AU_VIN1_P G3 AU_VIN1_P ISINK3 C10
G4 AU_VIN1_N
[5] AU_VIN1_N
(Rsense (R328) < 10m m )
R329 VA_PMU VA_PMU AU_VIN2_P D2 AU_VIN2_P
2. Main path should be 40m il. VCDT [3] D1
AU_VIN2_N AU_VIN2_N
(VBUS -> U303's E, -> U303's C -> R328 -> VBAT)

C242
330K VCDT rating : 1 .2 6 8 V J2
R324 AVDD28_ABB

1.0uF
3. Star connection from R328 to BAT Connector D3 Please use inducto r reco m m and by MTK
AVDD28_AUXADC VPROC_PMU
H2 GND_ABB Refer to MT6 3 2 3 desig n no tice VPROC_PMU [1,3]

C329
1uF
cap rating depends o n 39K

4.7uF_NF
Pho ne OVP spec.

C243
40m ils E2
[5] ACCDET ACCDET BUCK OUTPUT VPROC_SW

1.0uF

C333
VPROC C14
L301 0.68uh
[11]CLK4_AUDIO E1 CLK26M VPROC D14
10

R331 E14
9
8
7
1
4

VPROC
POWER-NFET+ PNP-MI5809

CHR_LDO [3]
C
C
C
C
D
D

3.3K B12 VPROC_FB [1]

CHARGER VPROC_FB
GND_VPROC_FB C12
GND_VPROC_FB [1]
U303

ISENSE/ BSTSNS 4 m il [3] BATSNS BATSNS P13 BATSNS

[3] ISENSE ISENSE P12 ISENSE VPA A14 L302
differential to Rsense BAT_ON K3 B14 VPA_SW 2.2uh
[3] BAT_ON BATON VPA VPA_PMU
[3] VCDT VCDT A12 VCDT
VPA for WCDMA

2
VDRV M13 VDRV VPA_FB D12
[3] VDRV

2.2uF
C334
G
B
E

S
2
3
6
5

CHR_LDO [3] CHR_LDO N13 CHRLDO ¿¿½üL305

1
VSYS_SW L303 0.68uh

C316
40m ils H14 VSYS_PMU

C302

C317
VSYS
Add Zenar Dio de

1.0uF
500mW

1.0uF
R316 CONTROL SIGNAL
40m ils ISENSE_R M2
Place o n the path [10] PWRKEY PWRKEY

100PF
HT303 4m il A1
ISENSE [3]
[3] VDRV

[2] WATCHDOG_B SYSRSTB

SR0805

fro m VBAT to IC 1K
[3] CHR_LDO

K4
0.2
R328

Rsense Differential BATSNS [3] [2] SYSRST_B RESETB ALDO OUTPUT

4m il (Battery co nnecto r A9 FSOURCE VA M3 VA_PMU
HT304 A7 VEMC_3V3_PMU VA_PMU
Clo se to PMIC [2] EINT_PMIC INT
o r test po int o r IO N12 EXT_PMIC_EN VCN28 N3 VCN_2V8_PMU
VTCXO L4 VTCXO_PMU
40m ils co nnecto r) N2
TP-1.0MM TP-1.0MM TP-1.0MM PMU_TESTMODE
VF : 4.85V~ 5.36V P3 VCAMA_PMU
TP305 TP-1.0MM
BATTERY TP302 TP303
TP-0.8MM TP306
AUXADC_REF
AUXADC_REF [3,11] [2] AUD_DAT_MOSI E7 AUD_MOSI
VCAMA
VCN33 M6 VCN_3V3_PMU
TP304 [2] AUD_CLK E8 AUD_CLK AVDD33_RTC C3 VRTC

0.1uF
Between IC and IO po rt

1.0uF
B6
CONNECTOR [2] AUD_DAT_MISO AUD_MISO
C355
C331 100nF

C354
A2

C353
[2,11] SRCLKENA SRCLKEN
R334

16.9K

J301 DLDO OUTPUT

TP301
1

FCHR_ENB [3] [3] FCHR_ENB M1 FCHR_ENB 1.0uF

1

1 J13 DVDD12_EMI
VM
2 Refer to MT6 3 2 3 desig n
1

[2] PMIC_SPI_SCK D9 SPI_CLK VRF18 H11 VRF18_PMU

3 40m ils B7 L12
40m ils [2] PMIC_SPI_CS SPI_CSN VIO18 VIO18_PMU
4 D8 M4 VIO28_PMU
R317
VBAT
VBAT [3,5,6,7,10,11,12]
no tice fo r Zener selectio n [2] PMIC_SPI_MOSI
B8
SPI_MOSI
SPI_MISO
VIO28
VCN18 J12 VCN18_PMU
5 VBAT [2] PMIC_SPI_MISO
BAT_ON [3] VCAMD K14 VCAMD_PMU
6 L13 VCAMD_IO_PMU
VBAT INPUT VCAM_IO
1K F13
80m il VBAT_VPROC
40m il F14 VBAT_VPROC
BAC3290401 G13 P7 VEMC_3V3_PMU
R335

30mil (4mil if VPA no use ) VBAT_VPROC VEMC_3V3

27K

VBAT A13 L6
VR302

VMC_PMU
VR301

VBAT_VPA VMC
C360

BATTCON-BA2C04311-R R334,R335 m ust to be close to VMCH P4 VMCH_PMU

NF

20mil VBAT H13 N6 VUSB_PMU

VBAT_VSYS VUSB
PMIC AUXADC_REF pin P8 VBAT_LDOS3 VSIM1 P9 VSIM1_PMU
20m il

811200000061
P6 VBAT_LDOS3 VSIM2 N9 VSIM2_PMU

22uF
C310
20m il VBAT P5 L8

D302
VBAT_LDOS2 VGP1 VGP1_PMU

C330
20m il VBAT P2

NF
VBAT_LDOS1
VIBR M7 VIBR_PMU
20m il J14 N8

2
VSYS_PMU AVDD22_BUCK VGP2 VGP2_PMU
M14 AVDD22_BUCK VGP3 L14 VGP3_PMU
VIO18_PMU [1,2,3,4,5,6,8,9,11] DVDD18_DIG_PMIC VCAM_AF N7 VCAM_AF_PMU

if batte ry NTC is 10kohm, R334=16.9K, R335=27K A8 DVDD18_DIG

TP-0.8MM

R361

20K

if batte ry NTC is 47kohm, R334=61.9K, R335=100K VIO18_PMU VIO18_PMU A5

TP307

DVDD18_IO
1 Refer to MT6 3 2 3 HW desig n no tice
[3,11] AUXADC_REF AUXADC_REF C2 AUXADC VREF
R360 AUXADC_VREF18
[11] AUXADC_TSX AUXADC_TSX B1 AUXADC_AUXIN_GPS VREF P14

C320
BAT_ID_ADC [2] B2 AVSS28_AUXADC
GND_AUXADC

C323

C322
1K [11] dedicate VSS ball, m ust return to cap then to m ain GND:
CLOS E Batconne ctor

1.0uF

100nF
1 . GND_ VREF(N1 4 ) = > C3 2 0
BC 1.1

100nF
A10 N14 HT305
Based o n yo ur system level desig n , if [2] CHD_DM CHG_DM GND_VREF
A11 CHG_DP
VR310

[2] CHD_DP

4.7uF

10uF
10uF
better EOS perfo rm ance is needed o n yo ur
system , please refer to EOS perfo rm ance
SIM LVS RTC_32K1V8 D5 RTC32K_CK [2] RTC

HT301
C322 m ust to be close RTC C4
enhance pro po sal RTC_32K2V8

C350

C303
C301
[2] SIM1_SCLK B5 SIM1_AP_SCLK XIN A3 32K_IN
to PMIC AUXADC_TSX pin [2] SIM1_SIO M11 SIMLS1_AP_SIO XOUT A4 32K_OUT
[2] SIM1_SRST E6 SIM1_AP_SRST

10uF
10uF
[2] SIM2_SCLK C5 SIM2_AP_SCLK GND_ISINK B10

1.0uF
K11 G11

R336
[2] SIM2_SIO SIMLS2_AP_SIO GND_VSYS

C308 1.0uF

1.0uF
D6 SIM2_AP_SRST GND_VPA E13

0
[2] SIM2_SRST

C304
Connect TSX/ XTAL GND GND_VPROC E11

C306

C307
C309
[8] SCLK1 M9 SIMLS1_SCLK GND_VPROC F11
to AUXADC_GND first [8] SIO1 N11 SIMLS1_SIO GND_VPROC F10
than connect to m ain GND [8] SRST1 M10 SIMLS1_SRST
GND_LDO K6 RTC 3 2 K : X3 0 1 + C3 2 4 + C3 1 9 = > m o unt, R3 3 3 = > NC
[8] SCLK2 K9 SIMLS2_SCLK GND_LDO K8
L11 3 2 K-less: X3 0 1 + C3 2 4 = > rem o ve, C3 1 9 + R3 3 3 = > 0 R
[8] SIO2 SIMLS2_SIO
[8] SRST2 K10 SIMLS2_SRST GND_LDO F5 Clo se to chip

HT302
GND_LDO F6
F7 R333 0
GND_LDO DCXO_32K [11]
GND_LDO F8

GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
GND_LDO
refer to system analo g LDO GND_LDO F9
GND_LDO G5
perfo rm ance im pro ve pro po sal GND_LDO G6

J10
J9
J8
J7
J6
H10
H9
H8
H7
H6
H5
G9
G8
G7
VIBR_PMU

Refer to MT6 3 2 3 desig n no tice

fo r Buck GND layo ut rule VRTC

MOT
L304
C311
1uF

[3] VIBR_PMU

R312
68nH

1K
2
L305
1
J302
C314

C315
NF

NF

68nH
Refer to GPS co -clo ck layo ut rule

47uF
C325

C326
22uF
Vibra
= = > for longer RTC tim e sustain after battery rem ove,
please refer to RTC design notice

TITLE: LUA-U23 REV: V1.3

DOCUMENT NO.: 03_MT6323_PMIC_AUDIO SIZED: A1

DEPARTMENT:
Hardware DEPT.
COMPANY:

DESIGNER: < DESIGNER> Last Saved Date: 2015/ 12/ 7 SHEET: 3 OF 13

 R401 0

VIO18_PMU DVDD18_EMI
VDD1 : Core 1
DVDD18_EMI

U401
EA0 Y2 CA0 VDD1 F3
EA1 Y3 F4

100nF
CA1 VDD1
EA2 W2 F9

2
CA2 VDD1
EA3 W3 G5

2.2uF
CA3 VDD1

C401
EA4 V3 CA4 VDD1 AA3

C402
EA5 L3 CA5 VDD1 AA5
EA6 K3 AB3

1
CA6 VDD1
EA7 J3 CA7 VDD1 AB4 GND GND
EA8 J2 AB9 DVDD12_EMI
CA8 VDD1
EA9 H2 CA9
VDD2 F5
ED0 W12 DQ0 VDD2 F8 VDD2 : Core 2
ED1 V11 DQ1 VDD2 J5
ED2 V13 DQ2 VDD2 K5
ED3 U11 DQ3 VDD2 L2
ED4 U13 DQ4 VDD2 L5
ED5 T11 DQ5 VDD2 M5
ED6 T13 DQ6 VDD2 N5
ED7 R12 DQ7 VDD2 P5
ED8 N12 DQ8 VDD2 P8

100nF

100nF

100nF

100nF
ED9 M13 P11

2
DQ9 VDD2

C405

C406

C407

C408
ED10 M11 R5

2.2uF

4.7uF
DQ10 VDD2

C403

C404
ED11 L13 DQ11 VDD2 T5
ED12 L11 DQ12 VDD2 U5
ED13 K11 V5

1
DQ13 VDD2
ED14 K13 DQ14 VDD2 W5
ED15 J12 DQ15 VDD2 AB5 GND GND GND GND GND GND
ED16 AB12 DQ16 VDD2 AB8
ED17 AB11 DQ17
ED18 AB10 DQ18 VDDQ G9
ED19 AA13 DQ19 VDDQ H8
ED20 AA12 DQ20 VDDQ H12
ED21 AA10 J11 1. VCC : Core Voltage 2.7v ~ 3.6v
DQ21 VDDQ
ED22 Y13 DQ22 VDDQ K10 2. VCCQ : IO Voltage 1.7v~ 1.95v (low voltage range)
ED23 Y11 DQ23 Power VDDQ K12
ED24 H11 DQ24 VDDQ L8
ED25 H13 DQ25 VDDQ L9
ED26 G10 DQ26 VDDQ M10
ED27 G12 DQ27 VDDQ M12
ED28 G13 DQ28 VDDQ N11
ED29 F10 DQ29 VDDQ R11
ED30 F11 DQ30 VDDQ T10
ED31 F12 DQ31 VDDQ T12
R402 240 VDDQ U8
1 2 G2 U9
ZQ0 VDDQ
1 2 G3 V10
ZQ1 VDDQ
240 VDDQ V12
R403
GND F13 VSSQ VDDQ W11
G11 VSSQ VDDQ Y8
H10 VSSQ VDDQ Y12
J8 VSSQ VDDQ AA9
J13 VSSQ
K8 VSSQ VDDCA K2
K9 VSSQ VDDCA N2
L10 VSSQ VDDCA U2
L12 VSSQ VDDCA V2
M8 R404 0
VSSQ
N13 VSSQ VCC B3
VEMC_3V3_PMU

4.7uF
P9 VSSQ VCC B12
R13 B13

2
VSSQ VCC

0.22uF
T8 VSSQ VCC C4

C410
U10 VSSQ VCC D8

C409
U12 VSSQ VCCQ A4
V8 B6

1
VSSQ VCCQ
V9 VSSQ VCCQ B9 GND GND
W8 C7 R405 0
VSSQ VCCQ
W13 VSSQ VCCQ C11
VIO18_PMU
Y10 VSSQ VCCI A11
AA11 VSSQ

100nF
B8

1uF

2
CLKM EMMC_CLK [2]

100nF
F2 C2

2.2uF
VSS RST

C413

C414
EMMC_RST [2]
G4 VSS CMD A6 EMMC_CMD [2]
G8 VSS eMMC

C411
H3 B4

1
VSS DAT7

C412
EMMC_DAT7 [2]
H5 VSS DAT6 A5 EMMC_DAT6 [2] GND GND
L4 VSS DAT5 A10 EMMC_DAT5 [2] GND
M3 VSS DAT4 C9 EMMC_DAT4 [2]
M4 VSS DAT3 B5 EMMC_DAT3 [2]
N4 VSS DAT2 C6 EMMC_DAT2 [2]
N8 VSS DAT1 B10 EMMC_DAT1 [2]
P4 VSS DAT0 A9 EMMC_DAT0 [2]
P12 VSS
R3 VSS
R4 VSS
R8 VSS
T4 VSS
Y4 VSS CS0# U3 ECS0_B [2]
Y5 VSS CS1# T3 ECS1_B [2]
AA2 VSS LP-DDR3
AA4 VSS CKE0 T2 ECKE [2,4]
AA8 VSS CKE1 R2 ECKE [2,4]

H4 VSSCA CLK P3 EDCLK [2]

J4 VSSCA CLK# N3 EDCLK_B [2]
K4 VSSCA
P2 VSSCA DQS0 T9 EDQS0 [2]
U4 VSSCA DQS0# R9 EDQS0_B [2]
V4 VSSCA DQS1 M9 EDQS1 [2]
W4 VSSCA DQS1# N9 EDQS1_B [2]
DQS2 Y9 EDQS2 [2]
A3 VSSM DQS2# W9 EDQS2_B [2]
A8 VSSM DQS3 H9 EDQS3 [2]
A12 VSSM DQS3# J9 EDQS3_B [2]
B2 VSSM
B7 VSSM DM0 R10 EDQM0 [2]
B11 VSSM DM1 N10 EDQM1 [2]
C3 VSSM DM2 W10 EDQM2 [2]
C5 VSSM DM3 J10 EDQM3 [2]
C8 VSSM
C10 VSSM VREFCA M2 EVREF [2]
C12 VSSM VREFDQ P13
C13 VSSM
D7 VSSM
AB14
4.7uF

100nF

DNU
A2 VSF DNU AB13
A13 VSF DNU AB2
GND
B1 VSF DNU AB1
B14 VSF DNU AA14
C416
C415

D2 VSF DNU AA1

D3 VSF DNU A14
D4 VSF DNU A1 GND GND
D5 VSF
D6 VSF
A7 RFU ODT P10

LPDDR3+EMMC-H9TQ18ABJTMCUR
TITLE: LUA-U23 REV: V1.3

DOCUMENT NO.: 04_MEMORY_EMMC_LPDDR3 SIZED: A1

DEPARTMENT:
Hardware DEPT.
COMPANY:

DESIGNER: < DESIGNER> Last Saved Date: 2015/ 12/ 7 SHEET: 4 OF 13

 Receiver
Earpho ne Audio clo se to IC
sam e po wer do m ain

clo se to co nnecto r 470K

R505 (1) CTIA: L-R-G-M
clo se to IC clo se to co nnecto r VIO18_PMU

C501
33PF
R506 47K
[2] EINT11_HP

C510

0.1uF
R501 0 TP-0.8MM TP-0.8MM TP-0.8MM TP-0.8MM TP-0.8MM
[3] AU_HSP Reserve bead+ C fo o tprint fo r FM
REC501 TP1 TP2 TP3 TP4 TP5
AUDIO-REC-MRFD1206A011A18
perfo rm ance tuning

NF

NF
100PF
1

C502
BEAD503 1800ohm
2

C506
[5] HP_MIC HP_MIC-1 [5]

C507

1
R502 0 BEAD501 1800ohm BEAD504 1800ohm
[3] AU_HSN C504 22uF R503
[5] HP_MP3L-OUT HP_MP3L-1 [5]
100 AUDIO-EAR-PH12-6B05F35D

ESD-TVS-ESD9NS5V
BEAD502 1800ohm BEAD505 1800ohm EAR_DET [5]
22uF R504

3
C505

C503
33PF
[5] HP_MP3R-OUT HP_MP3R-1 [5]
3

TVS501
100 [5] HP_MP3R-1

33PF

33PF
[5] HP_MP3L-1 4
FM_ANT-1 [5] 5
[5] EAR_DET C542 2
[5] FM_ANT-1 6

C509
C508
1
[5] HP_MIC-1

1
4.7PF

VR501
J501

2
R507 R508
470
470
R509 0 FM_ANT [13]

220ohm
TVS502

TVS503

TVS504

1NF

BEAD506
C511

1NF
C541
Handset Micro pho ne R510 0 FM_RX_N_6572 [13]

MICBIAS0

Sing le via to GND plane

1K
R521

Clo se to
Clo se to
MIC
BB
1.5K
R522

C522

[3] AU_VIN0_P
C524
100nF
NC/ 100PF

[6] AU_VIN0_P-1
C527

C523 [6] AU_VIN0_N-1

4.7uF
[3] AU_VIN0_N
NC/ 33PF
NC/ 33PF

100nF
1.5K
R523

C526
C525

Analo g Switch Earpho ne MICPHONE

R524

1K

VBAT

MICBIAS1

R516

300

R511
to g ether then sing le via to m ain GND C518

U502
1uF Clo se to BB Clo se to MIC GND o f C(4 .7 uF) and headset
6 C519 0.1uF
GND sho uld tie to g ether and sing le

1K
C512
3 COM1 1
[5] HP_MP3R-OUT V+ AU_VIN1_N1 C517 4.7uFvia to GND plane
[3] AU_VIN1_N GND
R514
5 NC1 NO1 2 AU_HPR [3,10]
100nF C515 R512
1K IN1 4 R520 1K
GPIO_0 [2] Clo se to EarJack

C514
9 COM2 33PF

C521
R519
[5] HP_MP3L-OUT 1.5K
R515 AU_HPL [3,5,10]
7 NC2 NO2 10

100PF
1K C516

R518
IN2 8

680pF
R517
close to codec

470
C513 33PF

680pF

C520
SWITCH-ANALOG-SGM5223YWQ10/ TR
[3] AU_VIN1_P HP_MIC [5]

close to codec 100nF

100K

470
VBAT

R513
to g ether then sing le

1K
via to m ain GND
K-Class Audio PA
GND

[3] ACCDET
600ohm
FB501

IN= 0, COM Connected to NC;

C533 4.7uF
IN= 1, COM Connected to NO;

C534
100nF
U501
A3

B3
2.2uF

VDD

VDD

D2
C1P
4.7uF
C531

Close to SPK
C1 D3
C1N PVDD

D1 C535
C2P
2.2uF

B4 BEAD507220ohm
B1
VOP SPK_P [6]
C2N
B2
C532

C528 33nF C2N BEAD508

R525 3K D4
A1 VON SPK_N [6]
C529 33nF INP 220ohm
R526 3K A2
[3,5,10] AU_HPL INN
NC/ 33PF
NC/ 33PF
1nF

1nF

NC/ 100PF

[2] GPIO5_AUDIO_PA_EN A4
GND
GND
GND

C538

C539

SHDN
C540
C537
C536
C2
C3
C4

C530 AUDIO-AMP-AW8736
220PF
R527

2 1
100K

TITLE: LUA-U23 REV: V1.3

DOCUMENT NO.: 05_AUDIO SIZED: A1

DEPARTMENT:
Hardware DEPT.
COMPANY:

DESIGNER: < DESIGNER> Last Saved Date: 2015/ 12/ 7 SHEET: 5 OF 13

 CTP Backlig ht LED Driver
ĬÈÏ 3*3· â×°
<=8LEDs£¬² ¼¾Ö¿Õ¼ä½ôÕÅʱ£¬¿É»»2520· â×°
TP-0.8MM
TP-0.8MM TP-0.8MM TP-0.8MM TP-0.8MM TP-0.8MM
TP11
TP6 TP7 TP8 TP9 TP10

VBAT
R1101 10K_NF

1
1

1
GND

VIO18_PMU VIO18_PMU FB1101 D1101

R1102 L1101 10uH
[2] EINT14_CTP_RST CTP_GPIO_CTP_RSTB [6]
R1103 0
[2] EINT2_CTP CTP_EINT_CTP [6] 600ohm
0 FB1102
[3,6] VGP1_PMU

C1106

10uF
VGP1_PMU [3,6]
LEDA [6]
R1104
[2] SDA0 CTP_SDA_1 [6] 1000ohm
0
50V C1112

C1111
R1105 GND
[2] SCL0 CTP_SCL_1 [6]

1uF
0 R1106 47PF

TVS1105
TVS1104
TVS1103
[2] PWM

TVS1102
J1101

TVS1101
0 GND GND
1 R1107
[6] CTP_GPIO_CTP_RSTB R1108
2
[6] CTP_EINT_CTP
3 LED-DRIVER-SGM3733 LEDK [6]
[3,6] VGP1_PMU
4 NF ILED= 20m A
C1105 [6] CTP_SCL_1 100K 4 3 R1109
5 SW GND
C1101 C1103 C1104
[6] CTP_SDA_1 47PF

0.1uF
C1102 5 2
GND 6 CTRL COMP
100nF_NF [6] LCD_CABC GND
100nF_NF 100nF_NF 6 1
VIN FB C1110
100nF_NF 10 + / -1%
ZIF-04-6298-006-000-883+
GND
U1101
GND
GND GND GND GND GND

0.22uF
C1108
VFB= 200m V

LCD_ SUB_ bo ard

EMI1101
J1102
1 4
[2] MIPI_TDN0 42 41
2 3
[2] MIPI_TDP0
1 40
LCD_CABC [6]
EMI1102
2 39
LRSTB [2]
1 4 3 38 33 R1110
[2] MIPI_TDN1 LPTE [2]
R1113 1K
4 37
LCD_ID_ADC [2]
2 3
MIPI_TDP1 5 36
[2]
EMI1103 6 35 0 R1111
VIO18_PMU
7 34 0 R1112
MIPI_TCN 1 4 VIO28_PMU
[2]
8 33

MIPI_TCP 2 3 9 32
[2] AU_VIN0_N-1 [5]
10 31
AU_VIN0_P-1 [5]
11 30
[2] USB_DM
12 29 0.1uF 0.1uF 100nF NF 100PF
[2] USB_DP LEDA [6]
13 28 LEDK [6] R1114
C1116 C1118
9 0 o hm differential 14 27 C1113 C1114 C1115
UTXD0 [2]
15 26 1K
16 25
17 24 SPK_N [5,6]
18 23
VBUS SPK_P [5,6]
19 22

TP-0.8MM 20 21
2

TP18
1

1.0uF
TVS1107

43 44
0.01uF

NF/ 811200000071

C1117
1
C1119

D1102

BTBS-BF040-I40B-C08-A
TP19 TP16 TP17
1

TP-0.8MM TP-0.8MMESD-TVS-ESD5342N
TVS507

TVS508

TP-0.8MM
3
2

TVS1106

GND

SPK_N [5,6]
SPK_N [5,6]

SPK_P [5,6]
SPK_P [5,6]
2 + TVS 1

1
TVS505
(S)LESD9D12T5G-SOD-923

TVS506
2 + TVS
(S)LESD9D12T5G-SOD-923

TITLE: LUA-U23 REV: V1.3

DOCUMENT NO.: 11_LCD_CTP_SUB SIZED: A1

DEPARTMENT:
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DESIGNER: < DESIGNER> Last Saved Date: 2015/ 12/ 7 SHEET: 6 OF 13

FRONT_ca me ra
FLAS H_LED
VCAMD_PMU VBAT
VGP3_PMU

EMI1201 U1201

LED-FLASH-A-SL680W1D-JP1-4T

LED-FLASH-A-SL680W1D-JP1-4T
VCAMD_IO_PMU VCAMA_PMU
LED-DRIVER-KTD267
1 4
[2] MIPI_RCN_A C1201 L2101 1.0uH
8 C1203
5 OUT
2 3 SW

2
[2] MIPI_RCP_A 22uF 9 1 2
6 OUT
SW
4 10uF
EMI1202 VIN

LED1201

LED1202
0 NF/ 0 0
[2] MIPI_RDN0_A 1 4 12
LED1
0

14
LED2
2 3 10
[2] MIPI_RDP0_A [2] GPIO13 ENF 1

1
R1205 J1201 RM
R1206 R1207 R1208 11
[2] GPIO12 ENM 2
24 1 RF
PWM

AGND
AGND
PGND

R1203
23 2

R1204
AVDD_SUB [7] EMI1203
22 3
1 4 21 4
[7] [2] MIPI_RDN1_A
500mA*2

3
13
7
DVDD_SUB 20 5

68K
19 6
DOVDD_SUB [7] 2 3 AVDD_SUB
[2] MIPI_RDP1_A 18 7
EINT6_SUB_CMRST [2]
17 8

13K
16 9 SDA1 [2,7]
SCL1 [2,7]
15 10
[2] EINT4_SUB_CMPDN 14 11
4.7uF
1.0uF

1.0uF

[2,7] CMMCLK DVDD_SUB

13 12 DOVDD_SUB
C1204

C1205

C1206

BTBS-BF040-I24B-C08-A

GND GND

MAIN_ca me ra

EMI1204
Hi-545 I2C: 0x40,0x41
1 4
MIPI_RDN1 [2]

2 3
J1202 MIPI_RDP1 [2]
33 34
1.0uF
C1209

EMI1205
1 30
HT20 2 29 1 4
AF_GND MIPI_RCN [2]
3 28
R1209 0 [2,7] SDA1
2 3
VCAM_AF_PMU 4 AF_VCC= 2.8V
27 MIPI_RCP [2]
R1212 0 5 26
VCAMD_IO_PMU DOVDD= 1.8V
6 25 EMI1206
[2,7] SCL1
HT21 7 24
AGND 1 4
MIPI_RDN0 [2]
8 23
[2] EINT10_CMPDN
0 R1210 9 22 2 3
VCAMA_PMU AVDD= 2.8V MIPI_RDP0 [2]
0 R1211 10 21
DVDD: 8M= 1.2V/ 13M= 1.0V
VCAMD_PMU
[2] EINT9_MAINCAM_RST 11 20 EMI1207
12 19
strobe 1 4
MIPI_RDN2 [2]
4.7uF

13 18
1uF
1uF

14 17 2 3
[2,7] CMMCLK MIPI_RDP2 [2]
15 16
C1210
C1212
C1211

EMI1208
C1207

31 32
NF

1 4
MIPI_RDN3 [2]
BTBS-BF040-I30B-C08-A
GND GND GND 2 3
MIPI_RDP3 [2]

GND

TITLE: LUA-U23 REV: V1.3

DOCUMENT NO.: 12_CAMERA SIZED: A1

DEPARTMENT:
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DESIGNER: < DESIGNER> Last Saved Date: 2015/ 12/ 7 SHEET: 7 OF 13

 SD CARD

TP-0.8MM TP-0.8MM TP-0.8MM TP-0.8MM TP-0.8MM

TP1310 TP1312 TP1314 TP1316 TP1317

VMCH_PMU

TP-0.8MM TP-0.8MM TP-0.8MM

TP1311 TP1313 TP1315
1

1
0

1
R1307

J1301

2 7
0 [8] MC1DA2_1 T_DAT2 SIM_GND
[2] MC1DA2 R1308
MC1DA2_1 [8] 5 9
[8] MC1DA3_1 T_CD/ DAT3 SIM_VPP
R1309 0
[2] MC1DA3 MC1DA3_1 [8] 6 16
[8] MC1CM_1 T_CMD SIM_I/ O SIO1_1 [8]
R1310 0
[2] MC1CM MC1CM_1 [8] 8 11
[8] VMCH_PMU_1 T_VDD SIM_VCC VSIM1_PMU [3,8]
VMCH_PMU_1 [8]
17 10
[8] MC1CK_1 T_CLK SIM_RST SRST1 [3,8]
[2] R1311 0
MC1CK MC1CK_1 [8]

T card

SIM card
19 15

R1312 0 20
T_VSS SIM_CLK
18
SCLK1_1 [8]
SIM2
[2] MC1DA0 MC1DA0_1 [8] [8] MC1DA0_1 T_DAT0 RSVD
R1313 0 23 14
[2] MC1DA1 MC1DA1_1 [8] [8] MC1DA1_1 T_DAT1 RSVD
24
SW
1
COMMON_GND 25
3 COMMON_GND
COMMON_GND 22
4 COMMON_GND
COMMON_GND 21
12 COMMON_GND
COMMON_GND 13
COMMON_GND
VR1310

VR1311

VR1312

VR1313

VR1314

VR1315

VR1316

SIM+ T-CAF00-16234-0100
4.7uF
C1303

TP-0.8MM
TP1304
TP-0.8MM
TP-0.8MM TP-0.8MM
TP1303
TP1302 TP1301

[8] EINT_SD_1

1
1
1

1
J1302
R1302 0
SIM-CAF99-08153-0106
SIO2 [3]

R1301 0 6 10
CLK IO
5
[3] SCLK2 CLK
[3] SRST2 4 11
SIM1 3
RST
RST
VPP
VR1304

VIO18_PMU 2 12
TP-0.8MM VSIM2_PMU VCC GND

GND
GND
GND
GND
TP1309 1

33PF
VCC
TP-0.8MM TP-0.8MM TP-0.8MM TP-0.8MM

13
14
15
16
TP1305 TP1306 TP1307 TP1308 VR1301 VR1302 VR1303

1.0uF
33PF

C1304
R1305

C1301
47K

C1305
1

1
R1306 1K 0 R1303
[2] EINT3_SD EINT_SD_1 [8] [8] SIO1_1 SIO1 [3]

0 R1304
VR1309 [8] SCLK1_1 SCLK1 [3]

[3,8] SRST1 SRST1 [3,8]

VSIM1_PMU VSIM1_PMU

33PF

33PF
VR1305 VR1306 VR1307 VR1308

1.0uF

C1306

C1307
C1302

TITLE: LUA-U23 REV: V1.3

DOCUMENT NO.: 13_TK_SIM SIZED: A1

DEPARTMENT:
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DESIGNER: < DESIGNER> Last Saved Date: 2015/ 12/ 7 SHEET: 8 OF 13

 G-senso r VIO18_PMU

ÓÅÑ¡ R1402
VIO28_PMU

NF

VIO18_PMU
[2,9,10] SCL2
for AC noise filter
U1402
U1401
24

GND
[2,9,10] SDA2 8 1 R1403
3 1 SDA VDD
VDDIO SDO 7 2
4 2 [2] EINT1_A INT SCL
VDDD SDX SDA2 [2,9,10] 6 3
1.0uF

7 12 LDR GND
VDDA SCK SCL2 [2,9,10] 5 4
9 10 LEDC LEDA
GND CSB
8 11

4.7uF
100nF
C1401

GND PS SENSOR-ALS+ PS+ IR-AP3426M

6
CAP0 5
INT EINT_ACC [2,9]

C1403
SENSOR-ACCELER-BMA220

C1402
i2c slave add: 0x1E
GND
GND GND

BMA222E VIO18_PMU
VIO18_PMU

8bit ÓÅÑ¡

47K_NF
R1401
BMA222EÓëBMA220µÄÍ âÎ §Æ÷¼þ¿ÉÒÔ² »ÓÃÐÞ¸ Ä [2,9] EINT_ACC

i2c slave add: 0x11

ALS+ PS+ IR

Gse nsor¹ ©»õ² »¶¨ ¾¡ Á¿Ë«la y,Ä¿Ç°ÉÌ Î ñÉÏ ½¨ ÒéÓÅÑ¡ BMA222E

**
**

TITLE: LUA-U23 REV: V1.3

DOCUMENT NO.: 14_SENSORS SIZED: A1

DEPARTMENT:
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 VBUS

3
Q1501

D
R1510 0 1
[2] CHGFULL_EN G
R1512

3
100K Q1502

KEY
FET-N-2SK3541T2L

D
R1511

2
1
G
100K

S
FET-N-2SK3541T2L
R1513

2
TP-0.8MM TP-0.8MM 100K
TP1501 TP1505

RGB VBAT

0
[3] PWRKEY D1501
R1508
G 2
LED_GREEN [10]

R1503
TP-0.8MM
TP1504 R1507 10
U1501 4 1
R LED_RED [10]
0.1uF
C1504

1 R1509 20
[2,9] SCL2 SCL B 3
TP-0.8MM 2 LED_BLUE [10]
TVS1501

2.2uF
C1503
TP-0.8MM [2,9] SDA2 SDA 10
TP1503
TP1502 R1501 NC/ 0

1
3 6 DIODE-LEDX3-RGB6
[3,5] AU_HPL GND LED3 LED_BLUE [10]

TVS1505
GND C1501 0.22uF 4 7
R1502 0 AUDIO-IN LED2 LED_GREEN [10] D1502
[3,5] AU_HPR 5 8 R1560
VBAT VBAT LED1 LED_RED [10] G 2
SIDEKEY1
J1501

1
R1506 10
R1561
1
[2] KCOL2 1K 1 LED-DRIVER-AW2028
1 4 1
R

C1505

2.2uF
C1502
I2C--65H = C51 R1562

NC
2 20
RF-ANT-P-JS-IT-18 B 3
R1504 1K 3
[2] KCOL1 10
4 SIDEKEY2
DIODE-LEDX3-RGB6
5 1

TVS1504
D1503
[2] R1505 1K 6 R1563
KCOL0 G 2
RF-ANT-P-JS-IT-18 10
R1564
4 1
ZIF-04-6298-006-000-883+ R
Volum e Up : KCOL1/ GND B 3
R1565 20

Volum e Down : KPCOL0/ GND 10

DIODE-LEDX3-RGB6
D1504
R1566
G 2
10
TVS1502

TVS1503

R1567
4 1
R
R1568 20
B 3
10
DIODE-LEDX3-RGB6

FIDUCIAL-MARK-1MM FIDUCIAL-MARK-1MM

FIDUCIAL-MARK-1MM FIDUCIAL-MARK-1MM

TP50 TP60 TP70 TP80

1
HOLE-VIA2.4/ 3.6MM
HOLE-VIA1.6/ 2.6MM
HOLE-VIA2.4/ 3.6MM
HOLE-VIA2.4/ 3.6MM
HOLE-VIA2.4/ 3.6MM
MARK5 MARK4 MARK3 MARK2 MARK1

MARK6
HOLE-1.5MM

1
1

1
P1 P3 P2 P4

Æ
Á±Î¿ò Æ
Á±Î¿ò Æ
Á±Î¿ò Æ
Á±Î¿ò

1 1 1 1
ICO-BOX ICO-BOX ICO-BOX ICO-BOX

TITLE: LUA-U23 REV: V1.3

DOCUMENT NO.: 15_KEY_LEDS SIZED: A1

DEPARTMENT:
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COMPANY:

DESIGNER: < DESIGNER> Last Saved Date: 2015/ 12/ 7 SHEET: 10 OF 13

 RF9810 control logic table
L604
Enable VctC VctB VctA 1 2
[12] TRXB2
LB_GMSK_TX H L H L
12pF

[12]
HB_GMSK_TX H L H H

C606

4.3nH
NF

L607
LB_EDGE_TX H L L L L638

TRXB8
2

1
HB_EDGE_TX H L L H [12] TRXB1
1 2

RX1 L H L L 12pF GND GND

2
C652
RX2 L L H L

2.7nH
NF

C608
RX3 L L H H

RF-DPX-SAYEY1G88CA0B0A
2

1
RX4 L L L H

6
SAYEY1G88CA0B0A
GND GND

ANT
NF
7 1 2
G 7

GND
G 5
G L612

1
4
G 2

C639

12pF
U602

TX
RX
RX
6
SAYEY1G95HA0F0A

3
1
8

2
7 7.5NH

ANT
1 2
G 7 W_PA_OUT_B2
[12]
G 5 C641
G 4
G

6
2

SAYEY836MCA0F0A
U616

TX
RX
RX

RF-DPX-SAYEY1G88CA0B0A

RF-DPX-SAYEY1G88CA0B0A
ANT
L603
1 2 G 7

3
1
8
G 5
NF G 4
G 2

U607
[12]
W_PA_OUT_B1

TX
RX
RX
C601
2.2NH

C603
2.7nH
L653

3
1
8
1
1 2

C602
2

NF

2
8.2nH

1
[12]
W_PA_OUT_B8

1
4.7PF

C616
L617 L602

2
4.7PF

C645
1 2 1 2

1
22NH

C609
NF NF 1 2

NF

2
L621 L634 L613

2
1 2 1 2

2
1.8nH

1.8nH
C617

C626
NF NF

1
NF
L614
1 2

[12]
L600

GGE_PA_LB_IN
[12] [12][12]
VBAT

GGE_PA_HB_IN

W_PA_B2_IN

W_PA_LB_IN
[3]
VBAT [3,5,6,7,10,11,12] LB_RX_P [11]

W_PA_B1_IN
12nH

L616

39nH
C600

NF
L615
L618

10
[12] 2G_LB Z600
BPI0~ 4 and 10~ 11 are 2G+ 3G m ode both 2.2NH L619 VRF18-1 [11]

GND
22PF 1 9 LB_RX_N [11]

C665
LBIN LBOUT
BPI5~ 9 and 12~ 14 are 3G m ode only

NF
2 8 12nH
(suggest BPI5~ 9 = 1.8V) GND LBOUT C669 470nF

2
3 7 VRF18-1

2
AS M_VCTRL_A
[2] [2,11,12] [2,11,12] [2]
ASM_VCTRL_A C667 GND HBOUT L623

1.8nH
L622

1.8nH
[2]M_VCTRL_B
AS [2,11,12] ASM_VCTRL_B [2] [2]
[2,11,12] 4 6
[12] 2G_HB HBIN HBOUT HB_RX_P [11]

GND
[2]M_VCTRL_C
AS ASM_VCTRL_C
[2,11,12] [2]
[2,11,12] 6.2NH PDET [12]

L660 1
3.3NH

L661 1
[2] [2,11,12]
WG_GGE_PA_ENABLE WG_GGE_PA_ENABLE
[2,11,12] 22PF

C668

5
NF

7.5NH
L625
NF
L624
L626

A10

A11

D11

C10
B11

B10
D3

A2

A3

A5

A6

A8

A9
C3

C2

C7

C8

C9
E3

B3

B4

B5

B6

B8
J2

J7

J8
HB_RX_N [11] U600
6.2NH

2GHB_TX

3GH1_TX

3GH2_TX

3GL5_TX

2GLB_TX

VTXHF
GND
GND
GND
GND
GND

3GB1_RXN

3GB5_RXN

3GB2_RXN

3GB8_RXN

GND
GND

GND
GND
GND
GND
GND
3GB1_RXP

3GB5_RXP

3GB2_RXP

3GB8_RXP

DET
F3 GND GND D9
G3 GND GND E9
H3 GND GND F9
J3 GND GND G9
C4 GND
FDD RX TXO GND H9
D4 GND GND J9

Two Applicatio n Circuit Co nditio ns, A1 B40_RXP DETGND D10

WG_GGE_PA_VRAMP WG_GGE_PA_VRAMP [2,11,12]
[2] [2,11,12] [2]
B1 B40_RXN TMEAS C11
1 .TSX Circuit : X6 0 0 = TSX, R6 5 3 = R6 5 6 = NC, R6 5 4 = 1 0 0 K+ -1 %, R6 5 5 = R6 5 7 = 0 o hm
[11] LB_RX_P LB_RX_P C1 LB_RXP V28 E10 VTCXO28-1 VTCXO28-1
2 .XTAL Circuit :X6 0 0 = Mo bile XTAL, R6 5 3 = R6 5 6 = 0 o hm , R6 5 4 = R6 5 5 = R6 5 7 = NC TDD RX
[11]
[11]LB_RX_N LB_RX_N D1 LB_RXN 3GTX_IP G10 TX_BBIP TX_BBIP [2,11]
[3] [3,11]DCXO_32K DCXO_32K [3,11]
[3] connect to m ain GND

470nF
C674
[11]HB_RX_P HB_RX_P E1 HB_RXP 3GTX_IN G11 TX_BBIN TX_BBIN [2,11]
[3] AUXADC_REF Route AUXADC_REF with 4m il trace width TX(I/ Q)
R633 0
VTCXO_PMU VTCXO28-1 [11] [11] HB_RX_N HB_RX_N F1 F10 TX_BBQP TX_BBQP [2,11]
C675 HB_RXN 3GTX_QP
[11] VRF18-1 X600

MT6166
VRF18_PMU R634 0 VRF18-1 [11] XTAL-26M-2520-EXS00A VRF18-1 F2 F11 TX_BBQN

1.0uF
0 VRXHF 3GTX_QN TX_BBQN [2,11]

C685

NF
R654

R656
470nF G2 L11 VRF18-1 [11]
RFVCO_MON TXVCO_MON
VIO18_PMU VIO18_PMU 4 3 BGA104-4.7X4.7-0.4E0.25B(MT6166)
[3] AUXADC_TSX Route AUXADC_TSX with 4m il trace width R657 J1 XTAL1 VTXLF J11 VRF18-1 C676 470nF

[2] BS I-A_EN [2,11] BSI-A_EN [2,11]

[2]
[2] BS I-A_CK BSI-A_CK [2,11]
[2] H2 XTAL2 TXBPI H10 DCOC_FLAG
[2,11] XO

NF
[2] BS I-A_DAT0 BSI-A_DAT0 [2,11]
[2] 1 2 DCOC_FLAG
[2,11]
[2,11] GND VTCXO28-1 K1 J10 RCAL
[2] BS I-A_DAT1 [2,11] BSI-A_DAT1 [2,11]
[2] VTCXO28 RCAL
Test pin
[2] BS I-A_DAT2 [2,11] BSI-A_DAT2 [2,11]
[2] Route AUXADC_GND with 24m il trace width R655 R600
[3] GND_AUXADC DCXO_32K_EN G1 32K_EN TST2 K11
under AUXADC_REF/ AUXADC_TSX trace 2K
[2] DCOC_FLAG
[2,11] DCOC_FLAG
[2,11] [2] SRCLKENA L1 L10 PDF¸ ñʽÔ- Àí Í ¼,R600Î ª 2K
EN_BB TST1

NF
S RCLKENA[2,3,11][2,3] BSI
0 [11] VTCXO28-1
[2,3] SRCLKENA [2,3,11] SRCLKENA[2,3,11][2,3] SRCLKENA K2 G8 BSI-A_DAT2 BSI-A_DAT2 [2,11]
Close to each other C677 CLK_SEL BSI_DATA2

R653
26M output
[2] CLK1_BB [2,11] CLK1_BB [2,11][2]
[10] SYSCLK_WCN [11,13] SYSCLK_WCN [11,13] [10] Connect TSX/ XTAL GND and nearby X600 CLK3_CMMB L2 XO3 BSI_DATA1 H8 BSI-A_DAT1 BSI-A_DAT1 [2,11]
CLK3_CMMB [11] CLK3_CMMB [11] 470nF
[3] CLK4_AUDIO[3,11] CLK4_AUDIO [3,11] [3] to GND_AUXADC first E4 GND GND B7
F4 J6

AVDD_VIO18
GND GND
than connect to m ain GND connect to m ain GND RX(I/ Q)

BSI_DATA0
G4 GND GND D8
[2] RX_BBQP[2,11] RX_BBQP [2,11] H4 E8

OUT32K

BSI_CLK
VXODIG
[2,3,11] SRCLKENA GND GND

XMODE

BSI_EN
RX_QN
RX_QP
VRXLF

RX_IN
[2] RX_BBQN[2,11] RX_BBQN [2,11]

RX_IP
GND
GND
GND
GND
GND
GND

GND
GND

GND
GND
GND
GND
XO4

XO2

XO1
[2] RX_BBIN[2,11] RX_BBIN [2,11] [2,3,11] SRCLKENA
[2] RX_BBIP[2,11] RX_BBIP [2,11] Ro ute AUXADC_ REF/ AUXADC_ TSX as differential trace with well GND shielding
[11] CLK3_CMMB

J4
C5
D5
E5
F5
D7

K4

K3

L4

K5

L5

K6

K7

L7

L8

K8

K10

K9

G6

H6

F8

E7
J5

C6
D6
E6
F6
[2] TX_BBQP[2,11] TX_BBQP [2,11]
and ro ute AUXADC_ GND with 2 4 m il trace width under
[2] TX_BBQN[2,11] TX_BBQN [2,11]

RX_BBQN
AUXADC_ TSX/ AUXADC_ REF trace to pro vide return current path.

RX_BBQP
RX_BBIN
RX_BBIP
[2] TX_BBIN[2,11] TX_BBIN [2,11] [3,11] CLK4_AUDIO CLK4_AUDIO BSI-A_DAT0 BSI-A_DAT0 [2,11]
[2] TX_BBIP[2,11] TX_BBIP [2,11] R616 0 SYSCLK_WCN
[11,13]SYSCLK_WCN
[11]VTCXO28-1 1 2 [2,11] CLK1_BB CLK1_BB BSI-A_CK BSI-A_CK [2,11]
DCXO_32K_EN [11] [3,11] DCXO_32K DCXO_32K

VRF18-1

RX_BBIN
RX_BBIP

RX_BBQN
RX_BBQP
BSI-A_EN BSI-A_EN [2,11]

VIO18_VGPIO
Logic
MODE XMODE VXODIG [11] XMODE
DCXO_
32K_EN
VRF18-1 [11]
VIO18_PMU
L630 0 C682
XMODE [11] C684
R618
DCXO + 32K XO 0 (GND) 1 (VIO1 8 ) 1 (VIO1 8 )
[11]VTCXO28-1 1
0
2
[1,2,3,4,5,6,8,9,11]

1.0uF
DCXO + 32K-Less 1 (VTXCO2 8 ) 1 (VTXCO2 8 ) 1 (VTXCO2 8 ) 470nF
[11] VXODIG Reserved LC filter

VXODIG [11]
R617 0
[11]VTCXO28-1 1 2
470nF
C670

TITLE: LUA-U23 REV: V1.3

DOCUMENT NO.: 07_RF_MT6166_TXVR_2G_B34_B39 SIZED: A1

DEPARTMENT:
Hardware DEPT.
COMPANY:

DESIGNER: < DESIGNER> Last Saved Date: 2015/ 12/ 7 SHEET: 11 OF 13

 R715
ASM_VCTRL_C
[2,11]
1K
R716
R701
[2,11]
WG_GGE_PA_ENABLE

1 2 1K
[2,11]WG_GGE_PA_VRAMP

22PF
C705
22PF
C706
10K

2
1

220PF
C704
24K
R717
SKY77590 control logic table

1
VctA VctB VctC TxEn

2
GND
GND
6
2G_HB [11] S KY77590 ¼æÈÝS KY77584Éè¼Æ BS2 BS1 m ode ebable
2

VBAT [11]
(TRX1)G_DCS L L H L
2G_LB
6 S KY77590 pin22 pin24¿É½ÓÆäËûTRX¶Ë¿Ú£¬¿ÕÔØʱÐèÒª 51Å· Ä· ½ÓµØ
(TRX2)W_Band8 L H H L

2
2
TRXB1 [11] (TRX3)W_Band1 H L H L

22PF
C703
100PF

22uF
C650
6

C707
S KY77584 pin22 pin24½ÓµØ (TRX4)W_Band5 H H H L

VR701
[11]

1
TRXB2

1
6
(TRX5)W_Band2 L H L L
GND GND

6
(TRX6) NA H L L L
¶àÓàµÄ¶Ë¿Ú£¬ÓÃ50Å· Ä· ½ÓµØ
EDGETX_L H L H H
EDGETX_H H H H H
R714
GMSKTX_L H L L H
[2,11]ASM_VCTRL_B TRXB8 [11] GMSKTX_H H H L H
1K
2 GND
R713

[2,11]ASM_VCTRL_A

15
16
17
18
19
20
21
22
1K 2 TDD_B40_TX

MODE
GND

TXEN
VRAMP
TRX1
TRX2
TRX3
TRX4

U801

R730
22PF

51
C702

22PF
C701
14
VCC 0723 50ohm term inated
23

GND
13 TRX5

RF_ANT
VBATT
24
12 TRX6
BS1

RF-PA-SKY77590
25 GND
C713 11 GND
BS2 C708
26 RF-SWITCH-818000291
2 1 10 ANT
[11] GGE_PA_LB_IN TX_LB_IN 2 1 1 2
27 IN OUT
9 GND
56PF TX_HB_IN
28 39PF
GND J700
1

1
R712

R705
GND

C764

C768
NF

NF

NF

NF
GND
GND
GND
GND
GND
GND
GND
GND
2

2
8
7
6
5
4
3
2
1
GND GND
GND GND

[11]
GGE_PA_HB_IN 18PF GND
2 1
EDGE TXM
C712 4
GND
3
1

GND
R711

R710

2
NF

NF

I/ O
1
2

GND
GND GND
J602

BPI0~ 6 are 2G+ 3G m ode both

BPI7~ 13 are 3G m ode only

[12] W_PA_VBAT
Ôö¼ÓR756 OÅ· Ä· µÄ¼æÈÝ£¬CMOS PA ¿ÉÓã¬È¥ÁôÊÔÏ î Ä¿Çé¿ö [12] W_PA_VBAT
[12] W_PA_VCC
[12] W_PA_VCC

2
2
2

0.1uF
[2,12] VM1

82PF
C719
0.1uF
[2,12] VM1

C720
C733
R622

0.1uF

0.1uF
82PF
C746

C736

C737
1 2
VPA_PMU W_PA_VCC [12] [2,12] VM0 [2,12]VM0

1
1
0

1
2

GND
GND GND
2.2uF
C735

GND GND
GND

10
4
3

1
10
1

4
3

VCC
VBAT
VMODE_0
VMODE_1
VCC
VBAT
VMODE_0
VMODE_1
GND C725
R719 C726
C728 C745 2 1
R720 W_PA_B1_IN [11] 2 9 1 2
2 1 2 9 2 1 RF_IN RF_OUT W_PA_OUT_B1 [11]
[11] W_PA_LB_IN RF_IN RF_OUT W_PA_OUT_B8 [11] 0
18PF

2
R723 12pF

2
0 2.4nH

2
18PF
GND 8 U713 6

22NH
CPL_IN CPL_OUT

C750
C748
8 U708 6

NF

C732
1
NF
1

CPL_IN CPL_OUT SKY77761

sky77768 51

C749

NF

NF
R727
NF
R728

R619 5

1
1

1
[2] W_PA_B1_EN VEN

GND
GND
1 2 [2] W_PA_B8_EN 5 VEN
VBAT

GND
GND
W_PA_VBAT [12]

1
GND GND GND
0 GND

2
2

7
11
7
11

1
GND GND
3G_PA_CPL_OUT [12] GND

0_NF
R752
1
VR600

0_NF
R758
GND

2
[12] 3G_B1_CPL_OUT

2
3G_B2_CPL_OUT [12]

b5/8 b1

[12]
W_PA_VBAT
[12]
W_PA_VCC
2
2

[2,12]
2 VM1
0.1uF
82PF
C730
0.1uF

C711
C721

[2,12]
VM0
1

GND
GND GND
² Î ¿¼Éè¼ÆÊÇ26Å· Ä· ² Î ¿¼Éè¼ÆÊÇ26Å· Ä·
near-IC
10
4
3

R733 R737
1 2 1 2
VCC
VBAT
VMODE_0
VMODE_1

[11] PDET 3G_PA_CPL_OUT [12] C724

24 24 R725 L720
2

W_PA_B2_IN [11] 2 1 1 2 [11]

2 RF_IN RF_OUT 9 W_PA_OUT_B2
6
R746

18PF 0 1.0nH
[12]
36

3G_B1_CPL_OUT 8 U706 6
² Î ¿¼Éè¼ÆÊÇ35Å· Ä· CPL_IN CPL_OUT
C722

C723
NF

NF
1

SKY77762
1

NF
R729

5
1

2
W_PA_B2_EN [2] VEN
GND
GND

GND GND GND

2

7
11

GND GND
R709

3G_B2_CPL_OUT[12]

TITLE: LUA-U23 REV: V1.3

b2
DOCUMENT NO.: 08_RF_MT6166_WCDMA SIZED: A1

DEPARTMENT:
Hardware DEPT.
COMPANY:

DESIGNER: < DESIGNER> Last Saved Date: 2015/ 12/ 7 SHEET: 12 OF 13

 NF

C1023
NF
U1006

XTAL-CRYSTAL-26M-7L26002009
R1013
3 4 U201-F
OUTPUT VCC VCN_2V8_PMU
NF WB_RSTB AF6 WB_RSTB AVDD18_WBG AE4 AVDD18_WBG
XIN_WBG AD6 XO_IN
2 1 C224
GND GND AF5

0.1uF
GPS_RXQN GPS_RX_QN

C1022
[13]XO_IN GPS_RXQP AG5 GPS_RX_QP

NF
FM_DATA Y10 F2W_DATA GPS_RXIN AG4 GPS_RX_IN
FM_CLK AA10 F2W_CLK GPS_RXIP AF4 GPS_RX_IP

82PF
C1021
0 WB_SCLK AG7 WB_SCLK WB_TXQN AF2 WB_TX_QN
R1001 SYSCLK_WCN [11][6] WB_SDATA AF7 WB_SDATA WB_TXQP AG2 WB_TX_QP
WB_SEN AE6 WB_SEN WB_TXIN AF1 WB_TX_IN
WB_TXIP AE1 WB_TX_IP

WB_CTRL0 Y6 WB_CRTL0 WB_RXQN AE2 WB_RX_QN

WB_CTRL1 AA6 WB_CRTL1 WB_RXQP AD2 WB_RX_QP
WB_CTRL2 AA5 WB_CRTL2 WB_RXIN AC2 WB_RX_IN
WB_CTRL3 AA4 WB_CRTL3 WB_RXIP AC1 WB_RX_IP
WB_CTRL4 AB5 ANT_SEL0 [13]
WB_CRTL4
WB_CTRL5 AB4 WB_CRTL5
AB25 ANT_SEL0 TP1022
ANT_SEL0
AC26 ANT_SEL1
ANT_SEL1

WIFI/ BT/ GPS Single ANT Ref. AC25

5 0 Ohm ANT_SEL2 TP1024
ANT_SEL2
TP1023

Debug usage
BBIC-MT6582E1_LPDDR2_105
(S1+S2+S3+S4+S5+S6+S7+S8+S9)TRUED:PROJECTPROJECT!¤º³¡-p¹º-SP!MT6582PHONE20130205MT6582_MT6166_MT6627_MT6323_EMMC_LPDDR2_WTG_20130205-2.DSN

MT6582

ANT0902
ANT0901
1
1

RF-ANT-P-JS-IT-18
RF-ANT-P-JS-IT-18

WB_CTRL3 [13]

NF
C1018
WB_CTRL2 [13]
[13] WB_CTRL4

GPS Í â¼Óswitch£¨ ÐÔÄÜÓÅ»¯ £© [13] WB_CTRL5

WB_CTRL1 [13]
Close to MT6572

NF
U1007
WB_CTRL0 [13]

L1002
6 GND WIFI 1
5 0 Ohm
5 0 Ohm C1050 [13] AVDD18_WB
WB_RX_IP [13] HT1004
R1006 0 R1030 0
5 0 Ohm 5 2 [13]AVDD18_WBG VCN18_PMU
5 0 Ohm ANT GND
15PF
5 0 Ohm WB_RX_IN [13]
C1042

4 3
NF

GND GPS
C1041

NF

C1026
18PF U1000
RF-SAW-DP1608-V1524CAT

30

29

28

27

26

25

24

23

22

21
WB_RX_IN
WB_RX_IP
W_LNA_EXT

AVDD18_WBT

WB_CTRL5

WB_CTRL4

WB_CTRL3

WB_CTRL2

WB_CTRL1

WB_CTRL0
GND

5 0 Ohm 31 WB_GPS_RF_IN WB_RX_QP 20 WB_RX_QP [13]

[13] AVDD18_WB
HT1002
VCN18_PMU
C1029

NF

5 0 Ohm 32 19
GPS_DPX_RFOUT WB_RX_QN WB_RX_QN [13]
[13]AVDD18_GPS HT1003
VCN18_PMU
Based o n yo ur system level desig n , if
better WiFi TX perfo rm ance is needed o n VCN_3V3_PMU 33 AVDD33_WBT WB_TX_IP 18 WB_TX_IP [13]
[3,13]
yo ur system , please refer to WiFi Star Conn

100nF
for WB/ GPS/ WBG 1V8

C1007
perfo rm ance enhance pro po sal 34 17
NC WB_TX_IN WB_TX_IN [13]
5 0 Ohm
C1008

4700PF

C1005

1.0uF
35 16

C1006
NC WB_TX_QP WB_TX_QP [13]

36 AVDD28_FM
¸ ÖÍ ø×öÆÁ±Î ´ ¦ Àí MQFN40-5X5-0.4E(MT6627) WB_TX_QN 15 WB_TX_QN [13]
100PF

VCN_2V8_PMU_FM
[13]

37 FM_LANT_N GPS_RX_IP 14 GPS_RX_IP [13]

FM [5] FM_RX_N_6572 [5]

[5] FM_ANT [5]

L1011
FM_RX_N_6572

FM_LANT_P
38 FM_LANT_P GPS_RX_IN 13 GPS_RX_IN [13]
82nH
L1012
100NH

5 0 Ohm 39 GPS_RFIN GPS_RX_QP 12 GPS_RX_QP [13]

refer to FM desense perfo rm ance

AVDD18_GPS 40 AVDD18_GPS GPS_RX_QN 11 GPS_RX_QN [13]
[13] enhance pro po sal
FB1010 600ohm
AVDD28_FSOURCE

VCN_2V8_PMU
GPS Í â¼ÓLNA£¨ ÐÔÄÜÓÅ»¯ £©
VCN_2V8_PMU_FM
41 DVSS
33PF
R1010

0.01uF
C1002
L1013

F2W_DATA
NF

F2W_CLK

U1002
FM_DBG
HRST_B

SDATA

XO_IN
SCLK

CEXT
SEN

U1004 1 6
GND RFOUT
R1032 0 MT6627 SMD QFN40
2 5
1

10
C1031 L1001 GND EN ANT_SEL0 [13]
1 4 2 1 1 2 3 4
IN OUT RFIN VDD
5.6NH 1.0uF Close to MT6627
GND

GND

GND

33PF
GPS-LNA-RDALN16 C1025
C1030
2

NF

[3,13]
VCN_3V3_PMU

100PF
WB_RSTB
100PF

C1020 100PF [13] XO_IN

1.0uF

C1028

4.7uF
[13]
R1002

C1004

C1003
C1011

0
C1012

NF
[13] FM_DATA

VCN_2V8_PMU [3,13]
[13] FM_CLK

Based o n yo ur system level desig n , if

better GPS perfo rm ance is needed o n
[13] WB_SCLK
yo ur system , please refer to GPS
perfo rm ance enhance pro po sal [13]WB_SDATA

[13] WB_SEN

TITLE: LUA-U23 REV: V1.3

DOCUMENT NO.: 10_WIFI_BT_GPS_FM_MT6627 SIZED: A1

DEPARTMENT:
Hardware DEPT.
COMPANY:

DESIGNER: < DESIGNER> Last Saved Date: 2015/ 12/ 7 SHEET: 13 OF 13