Mr.

Abhishek Bhardwaj
Contact No: +91-7702929834
E-Mail ID: abhishek.bhardwaj@wdc.com , abhijiet9128@gmail.com
Address: 6-A-1, Vijay Nagar, Bhagat Ki Kothi, Jodhpur, Rajasthan

CAREER OBJECTIVE:

Seeking a challenging career in VLSI design and Electronic Design Automation industry, where I can grow myself and share my
knowledge of current technology so as to serve better to society.

EDUCATIONAL QUALIFICATIONS:

Name of Name of Name of Year of Marks obtained

Examination/Degree School/College University/Board passing
M. Tech(VLSI & CE) IIIT HYDERABAD IIIT HYDERABAD 2017 7. 85 CGPA
B. Tech(ECE) JIET Jodhpur RTU 2013 74.62%
AISSE-2009 K.V.No.1, AFS, Jodhpur CBSE 2009 78.0%
AISSCE-2007 K.V.No.1, AFS, Jodhpur CBSE 2007 69.6%

PROFESSIONAL EXPERIENCE (2 Years and 6months + 6months internship @ WDC):

 Working as a Senior ASIC Design Engineer at Western Digital Corporation from 17 Aug 2017 to till date.
 Worked as a Graduate Intern at SanDisk (WDC) from 16 Jan 2017 to 21 July 2017.

PROJECT ROLE:

PROJECT WORK
st
1 Project  Description : UHS 256GB SD card controller, sys_clk @ 500Mhz
28nm Tech  Role :
(Internship)  Written PT procs to perform sanity checks on release database through PD automation.

 Written script to report high-speed interface timing for skew balancing between flash
interface module and NAND FLASH.

2nd Project  Description : SSD Flash Manager Controller V2, sys_clk @700MHz , #10.5M instance
16nm Tech  Role :
 Integrated project with automation tool to perform sanity checks on received database from
synthesis team.

 Given timing closure of encoder block with single clock @700MHz.

 Worked with DFT team for Scan mode constraints development for all blocks and top and
provided clock grouping scheme for multi clock blocks to reduce test pattern count.

 Performed tweaker based ECO for top design as per project requirement to achieve Sign off
timing.

3rd Project  Description: PCIe Gen3/Gen4 SD-Express Controller. sys_clk @250MHz

16nm Tech  Role :
 Performed Synthesis experiments on a block to improve area by 15.1%.

 Evaluated IO constraints for source synchronous interface DRR SDR data transfer mode of
host interface module with interface max frequency @200MHz.

 Updated interface timing report environment for skew reporting between host interface
module and external host.

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4th Project  Description : SSD Flash Manager Controller V1 (re-opened), sys_clk @800MHz, #9M instance
16nm Tech
 Role :
 Given timing closure for re-opened two blocks and top with better performance with respect to
earlier release.
 Awarded by WDC VP for reducing total design power via PT ECO.
 Suggested methods for reducing automation tool runtime for faster completion of timing
runs.

5th Project  Description : SSD Flash Manager High Performance, sys_clk@700MHz, #30M instances
16nm Tech  Role :
 Given timing closure and best possible skew on multiple corners for ONFI interface
between flash interface module and NAND Flash @1GHz.

 Worked as a DFT interface to resolve DFT modes timing issues.

 Converted 9T ddc to 7.5T ddc for power critical block and performed DC experiments for
synthesis power comparison between 9T and 7.5T.

PROFICIENCY:

LANGUAGES : TCL, PERL, CSHELL, C, C++.

TOOLS : Synposys PrimeTime, Synopsys Design Compiler, Synopsys formality.
OPERATING SYSTEM : Windows, Linux RHE.

GRADUATION TRAININGS AND INTERNSHIPS:

Training:
Completed form Indian Space Research Organisation Jodhpur – Regional Remote Sensing Centre JODHPUR in Remote
Sensing System, GPS-GIS System.

Internships:
M. Tech (2017): Sr. ASIC Design Engineer (Graduate Intern) at SanDisk Device Design Center, Bangalore. (4rth Sem
Internship)
M. Tech (2016): Embedded Engineer at PROGITY, T-HUB Hyderabad.
B. Tech (2012): Completed Embedded System Designing from APPIN Institute, Jodhpur.

ACHIEVEMENTS:

 Awarded by WDC VP for reducing total design power via PT ECO @WDC

 Secure AIR-1761 in GATE 2015 with GATE score 647.

 2nd Position in OPEN HOUSE with working project “Hand Gesture Based Display using MATLAB” and awarded Rs 700.

 2rd Position in “Documentary Making”, in Annual competition RESONANCE 2013.

 1ST Position in B. Tech III SEM mid-term examinations awarded Rs 500.

 2nd Position in “Article Writing”, in inter-department competition under JESA.

PERSONAL DETAIL:

Date of Birth: 28/09/1991

Father’s Name: Late Mr. Kamal Kumar Bhardwaj

Nationality: Indian

Hobbies : Singing, Sports, Gaming.

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