Abstract

This document describes the design, simulation, and analysis of a Continuous Conduction Mode (CCM)
DC/DC Converter per the project assignment in Professor Subhashish Bhattacharya’s ECE 534 Power
Electronics course at North Carolina State University. The converter implemented contains two stages: a
transformer isolated forward-converter and a buck converter. This document describes the operational
analysis, component selection, power and efficiency analysis, as well as designing a feedback controller
for both stages. Finally, results obtained from simulating the design are showcased.

Introduction
The design project in ECE 534 Power Electronics was to design a two-stage forward-buck converter
shown in the following figure:

Figure 1. Forward-Buck Converter

The specifications given were provided:

Vin(V) 80-240
Vout(V) 12
Iout(A) 2-20
Light Load Efficiency (%) 72
Rated Load Efficiency (%) 88
Vout (ripple) (%) (Peak-Peak) 1
∆Il (Peak-Peak) 10%
Pout (max) (W) 240
Operating Temperature 0 C to 40OC
O

Table 1. Overall Specifications

In designing the converter, a steady-state analysis was performed while considering the major non-ideal
component parasitics, such as MOSFET on-resistance. Real components were then chosen for the design
such that they can meet the overall specifications as well as any other derived requirements resulting from
the design. The devices were chosen to provide at least a 1.5 safety margin. With the selected

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components, a power analysis was performed to determine if the overall specifications were met. A
control system was then designed for each stage of the converter to provide resistance to disturbances.
Finally, the design is Simulated using MATLAB Simulink with an add-on known as PLECS to verify the
design. Each of these tasks are discussed in detail in the following sections.

Task 1: Steady-State Analysis and Design

The design of the converter was broken up into two parts: The buck converter and the forward-converter.
To properly design the converter, a steady-state analysis was performed on both stages. For the steady-
state analysis the following non-idealities parasitics were included in the circuit models: MOSFET on-
resistance, Diode forward voltage drops, and inductor resistances. More non-idealities are considered
during the power/efficiency analysis, but the majority of the steady-state analysis could be performed
without including non-ideal parasitics with the understanding that the errors associated with these would
be small and eliminated by adding a feedback controller to the final design. The following section
discusses the buck-converter analysis.

Task 1.a: Buck Converter Steady-State Analysis

The buck-converter was analyzed first. The input voltage to the buck converter stage would be the output
voltage of the forward-converter stage and will be referred to as Vin2. The duty ratio associated with the
Q5 MOSFET will be referred to as D2. The buck converter was split into two sub-circuits: one where the
Q5 MOSFET is turned on, and one where the Q5 MOSFET is turned off:

Figure 2. Buck Converter Sub-Circuits

For each sub-circuit, the equations for the inductor voltage, capacitor current, voltage source current,
diode blocking voltage, and diode current were derived:

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Performing averaging on each circuit equation allows us to solve for a duty ratio which achieves a
particular output voltage and the average inductor current:

Waveforms were then drawn for the inductor voltage and current:

With these waveforms, the value for ripple current is derived and solved for L2, giving us a design
constraint:

From the sub-circuit analysis, we can see that the output capacitor takes on the ripple current such that it
doesn’t get fed into the load:

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From this, the output capacitor ripple voltage is derived, as well as another design constraint:

The average currents through other devices were derived:

The average power for each device is determined:

Finally, we determine component maximums:

Task 1.b: Forward Converter Steady-State Analysis

The Forward-Converter stage has an input of Vg, the overall converter input voltage, and an output
voltage of Vin2, which is the input voltage to the buck-stage. D1 is the duty ratio for the forward-
converter stage. The load resistance for this stage will be the equivalent resistance of the buck-converter,
which will be derived later in this document. A novel feature of this converter is that transistors and
diodes share the load evenly as the controller turns only 2 MOSFETs on during a single Ts period. In the
next Ts period, the other two MOSFETs are turned on. The diodes behave in a similar manner, through
during the MOSFET off-stage, both diodes conduct. Similar to the Buck-Stage analysis, the Forward-
Converter is broken up into its sub-circuits. The first stage is shown:

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Then the second stage is shown:

Resulting in the following equations:

Averaging these equations, we can derive an equation for the duty ratio and average inductor current:

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Using the sub-circuits and equations, we can draw the waveforms for the inductor voltage, inductor
current, and capacitor C2 current:

Using these waveforms, the ripple current and voltages are derived, as well as design constraints:

The diode current and MOSFET currents are drawn using the sub-circuit diagram. The MOSFET current
is equal to the Vg source current, but only every other Ts period.

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Using the waveforms, the average inductor current and RMS MOSFET currents are derived, as well as
the RMS C2 current:

With these currents, the average conduction power can be derived for each component:

Additionally, the component maximums are determined by utilizing the sub-circuit models and equations:

Task 1.c: Design Choices

After the sub-circuit analysis was complete for both converters, it was time to make some design
decisions. It had yet to be determined what the transformer turns ratio would be, what the output voltage
of the forward-converter would be set to, and what the switching frequency would be. It became an
iterative process in which these values would be decided, all equations would be reanalyzed, and then the
values would be chosen again based on the previous results. The values finally stabilized as follows:

Parameter Final Decision

n 0.6
Vin2 37
fs 350 kHz

A partial reason for redesigning these values was to obtain better efficiency ratings, to ensure that
components would operate beneath their maximum operating specifications, and to reduce the values of
inductors and capacitors.

It was at this time that the inductor part numbers were selected. For L2, the RB6132-25-0M5 was
selected, as it had the following characteristics:

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 Component L2
Part Number RB6132-25-0M5
Inductance 470µH
Series Resistance 2.4mΩ
Maximum Current 25A

For L1, the RB8522-36-1M5 was chosen as it had the following characteristics:

Component L1
Part Number RB8522-36-1M5
Inductance 1.5mH
Series Resistance 3mΩ
Maximum Current 36A

For many of the components throughout the design, many of the specifications are well above what was
required. The reason for this is based solely on other specifications. For example, even though L1 only
needed about 15 amps, the combination of high inductance and low series resistance was valuable.

All equations thus far can now be calculated knowing the input voltage, the output load resistance, and
the value of Req (the buck converter’s equivalent resistance). Finding this equivalent resistance relies on
the following power calculations:

We can also calculate the total power consumed by the forward converter, the total power consumed by
the converter, and the efficiency:

The switching loss calculations are discussed in the next section.

Task 2: MOSFET and Diode Selection

In the description of Task 1, the equations for maximum block voltages for all types of MOSFETs and
Diodes were derived. Evaluating the design at various operating points requires knowledge of the value of

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Req (the buck converter’s equivalent resistance). Finding this value involves knowing the switching loss
of both the MOSFETs and Diodes. Unfortunately, the parameters like Eon and Eoff are not always given
to easily calculate the switching loss of the MOSFETs or the Diodes, and the switching plots are often not
given either. When this is the case, it is usually required to create a test circuit to obtain the switch
timings, but that is not a practical way to design. Instead, the following equations are used to approximate
the switching loss, with the understanding that it may very well be better or worse:

If these values were still not given, a best guess was assumed for the sake of this project. With these
approximations, the remaining formulas described in Task 1 can be calculated. Doing so for the 4
operating points (Vgmin,Rmin; Vgmax,Rmin; Vgmin,Rmax; Vgmax,Rmin), we can calculate all values
associated with the circuit. This process is an iterative one since many of the circuit values depend on
component selection. The final values for all components and all operating points are shown later in this
document

After settling on a design, it was found that the Q5 blocking voltage was around 39.35, Q1-Q4 max
blocking voltage was 240V, D1-D2 max blocking voltage was 798V, the D3 max blocking voltage was
36.9V, the RMS current through Q1-Q4 was 4.39A, the RMS current through Q5 was 11.727A, the
average current through D1-D2 was 3.44A, and the average current through D3 was 13.13A. These values
helped select the parts, and all parts were given a 1.5 safety margin. See Task 4 section for more info.

The part selected for Q1-Q4, and Q5 was:

Component Q1-Q4 Q5
Part Number STL36N55M5 IPP50CN10N G
Rds,on 90mΩ 50 mΩ
Max Blocking Voltage 550V 100V
Continuous Current Ids 22.5 20
Qgs 15nF 4nF
Qgd 27nF 6nF
Vth 5V 4V

These parts were chosen to ensure the 1.5 safety margin needed, and to meet the power efficiency
requirements.

The part selected for D1-D2 and D3 was:

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 Component D1-D2 D3
Part Number VS-10ETS12PBF SBRT20U50SLP-13
Forward Diode Voltage 1.1V 0.5V
Max Reverse Voltage 1200V 50V
Maximum Average Current 10A 20A
irr 250mA 200mA
trr 2.5µs 500ns
The power loss associated with the MOSFETs and Diodes will be discussed during the Task 4 section.

Task 3: Capacitor Selection

Evaluating the design at various operating points using the equations formed in Task 1 showed that the
maximum RMS current through C2 was 18.95mA, and the maximum RMS current through Cout was
17.1mA. These are current ratings that are well within the limits of most available capacitors, so the
capacitor selection was mainly restricted to meeting the maximum voltage specifications and ripple
current specifications. See Task 4 for more information.

The capacitor chosen for Cout was a B41890A5108M. This capacitor had the following specifications:

Component Cout
Part Number B41890A5108M
Capacitance 100µF
Equivalent Series Resistance 30mΩ
Voltage Rating 25V
The specifications Cout ensured that the voltage rating of 12V was met with at least a 1.5 safety margin.
The capacitor chosen for Cin was a B43501A3107M. This capacitor had the following specifications:

Component Cin
Part Number B43501A3107M
Capacitance 100µF
Equivalent Series Resistance 660mΩ
Voltage Rating 385V

The choice of this capacitor was chosen solely to meet the input voltage range with a 1.5 safety margin.
The capacitor C2 was chosen to meet the Vin2 rating of 37V with a safety margin of 1.5, as well as
satisfy the condition for ripple voltage:

Component C2
Part Number B43504E2277M
Capacitance 270µF
Equivalent Series Resistance 570mΩ
Voltage Rating 200V

Though the voltage rating is well above what is needed, C2 was chosen for its high capacitance with low
series resistance. The power loss associated with the capacitors is described in the Efficiency and power
loss section.

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Task 4: Efficiency Calculation and Power Loss Distribution
Using the minimum and maximum values for both Vg and R, and the parameters obtained from choosing
components, and the design decisions involved with selecting n, Vin2, and fs, we can calculate all the
values thus far to determine if the design will meet specifications. The following table shows the value of
D1, D2, and Req for all 4 operation point extremes:

Operating Point Vgmin, Rmax Vgmax,Rmax Vgmin,Rmin Vgmax,Rmin

D1 0.286483 0.095335 0.293471 0.096128
D2 0.334353 0.334353 0.343781 0.343781
Req 55.33071 55.33071 5.381335 5.381335

The following table summarizes the component maximum voltage and currents for each device and at all
4 operating points:

Component
Maximums Vgmin, Rmax Vgmax,Rmax Vgmin,Rmin Vgmax,Rmin
vd3block 36.901476 36.901476 36.00146 36.00146
vq5block 39.35 39.35 39.35 39.35
vq1block 80 240 80 240
vd1block 264.89796 798.231294 258.69105 792.024383
il1avg 0.668706 0.668706 6.875617 6.875617
il2avg 2 2 20 20
id1avg 0.334353 0.334353 3.437808 3.437808
id3avg 1.331294 1.331294 13.124384 13.124384
iq5rms 1.156507 1.156507 11.726569 11.726569
iq1rms 0.421917 0.243427 4.389645 2.5123
Vc2max 37.000034 37.000043 37.000034 37.000043
Vcoutmax 12.000011 12.000011 12.00001 12.00001
ic2rms_1 0.014949 0.018953 0.014809 0.018946
Icoutrms 0.017042 0.017042 0.016858 0.016858

Comparing the maximum values to the maximum values of the chosen parts, it can be seen that all
devices meet the 1.5 safety margin. Looking at the ripple currents and voltages:

Ripple Vgmin, Rmax Vgmax,Rmax Vgmin,Rmin Vgmax,Rmin

delvcout 0.000105 0.000105 0.000104 0.000104
delv2 0.000034 0.000043 0.000034 0.000043
delil2 0.029517 0.029517 0.029199 0.029199
delil1 0.025892 0.032828 0.025651 0.032815

It can be seen that all ripple requirements have been met, in excess. The power loss of each component:

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 Component Vgmin, Rmax Vgmax,Rmax Vgmin,Rmin Vgmax,Rmin
PD3_Conduction 0.665647 W 0.665647 W 6.562192 W 6.562192 W
PD3_Switch 0.02625 W 0.02625 W 0.02625 W 0.02625 W
PQ5_Conduction 0.066875 W 0.066875 W 6.875621 W 6.875621 W
PQ5_Switch 0.073373 W 0.073373 W 0.724112 W 0.724112 W
PL2 0.0096 W 0.0096 W 0.96 W 0.96 W
Pcout 0.000015 W 0.000015 W 0.000014 W 0.000014 W
PL1 0.001342 W 0.001342 W 0.141822 W 0.141822 W
Pq1cond 0.016021 W 0.005333 W 1.734208 W 0.568048 W
Pq1SW 0.010484 W 0.010589 W 0.104166 W 0.104274 W
Pq2cond 0.016021 W 0.005333 W 1.734208 W 0.568048 W
Pq2SW 0.010484 W 0.010589 W 0.104166 W 0.104274 W
Pq3cond 0.016021 W 0.005333 W 1.734208 W 0.568048 W
Pq3SW 0.010484 W 0.010589 W 0.104166 W 0.104274 W
Pq4cond 0.016021 W 0.005333 W 1.734208 W 0.568048 W
Pq4SW 0.010484 W 0.010589 W 0.104166 W 0.104274 W
Pc2 0.000127 W 0.000205 W 0.000125 W 0.000205 W
PD1cond 0.367789 W 0.367789 W 3.781589 W 3.781589 W
PD1SW 0.360938 W 0.360938 W 0.360938 W 0.360938 W
PD2cond 0.367789 W 0.367789 W 3.781589 W 3.781589 W
PD2SW 0.360938 W 0.360938 W 0.360938 W 0.360938 W

Calculating the system efficiency at each operating point:

Power Type Vgmin, Rmax Vgmax,Rmax Vgmin,Rmin Vgmax,Rmin

PTotalLoss (W) 2.406703 2.364449 30.928686 26.264558
Pout (W) 24 24 240 240
Ptotal (W) 26.406703 26.364449 270.928686 266.264558
Efficiency (%) 90.88601481 91.03167679 88.58419665 90.13591662

Calculations show that the rated load efficiency is close to, but higher than, the original 88% requirement.
The light load efficiency is much higher than the original 72% efficiency. One reason for this large
difference could be improper assumptions and approximations made during the MOSFET and diode
switching loss calculations.

Where we can see a pie-chart distribution of the power loss throughout the system:

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Task 5: Small-Signal Model Transfer Functions
In order to design an effective control system, the transfer functions of the two stages must be determined.
The method used is known as Averaged Switch Network, and it involves finding the small-signal AC
model considering ideal components. Using the ideal components is fine in this case, as the non-idealities
can be viewed as disturbances to the system in which a control system will remove. This is especially true
in the case where integral control is implemented, as the steady-state error will go to zero as time goes to
infinity.

Task 5.a: Forward Converter Small Signal AC Transfer Functions

Starting with the forward converter, the non-ideal parasitics are removed from the sub-circuit and average
circuit equations:

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We now perturb and linearize using the following substitutions:

Distributing these terms, removing any DC component, and removing any 2nd order component (two hat-
values multiplied together), we get capacitor, inductor, and voltage generator current equations. We use
these equations to build an equivalent circuit model using voltage and current equations:

This circuit is then used to solve for the following transfer functions:

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Similarly, another transfer function is obtained from the model (wz = infinity in the following equation):

These transfer functions will be used in the next section when designing the controller.

Task 5.b: Buck Converter Small Signal AC Transfer Functions

The entire process described in this section is repeated for the 2nd-stage Buck Converter. The details are
not shown as they are nearly identical to the Forward-Converter. In order to reduce the document size,
only the results are shown:

Task 6 Controller Design

The objective of designing a controller is to design a compensator transfer function to place in a feedback
loop. We choose the overall cutoff frequency of our system as 1/10*fs, or 35kHz. We also choose to
design the phase margin as 52 degrees. The loop gain, which is the gain around the feedback loop
(ignoring all summations), is:

H(s) is the sensor gain and Vm is the PWM generator amplitude, both of which are designed. To make it
easy, both H(s) and Vm are set to 1:

The uncompensated loop gain can be obtained by setting Gc(s) = 1:

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Task 6. a: Forward Converter Controller Design

Plotting the bode plot of this transfer function, we determine the cutoff frequency, fo, the Quality factor,
Q, the uncompensated gain, Tuo, and the gain at fc:

Using these values, the PID controller was designed in the following way:

When originally tested, it was discovered that the system overshoot was not meeting the 20% project
requirement. To compensate for this, the Zeros were pushed closer to the origin to dampen the response:

Using these new values, Gc(s) was calculated as:

Calculating T(s):

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The magnitude bode plot was drawn by hand by drawing the following zero/pole tree of T(s):

Resulting in the following Bode Plot of the forward converter’s loop gain, T(s):

We confirm that the 0dB cutoff occurs at our fc value, 35kHz. We note that it has a high bandwidth and
high gain until the cutoff. Hand plotting the zero/pole phase tree of T(s):

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Resulting in the following hand-drawn phase plot of the forward converter’s T(s):

Task 6. b: Buck Converter Controller Design

The design of the Buck Converter controller is very similar to the process described in section 6.a. Instead
of repeating the entire description, the results are shown instead. The main difference is that the Gvd
value used was obtained from the Buck-Converter small signal analysis. Once again, the final designed
controller contained too much overshoot for the specification, so the zeros were moved in the following
way to compensate:

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Which results in the following buck converter Gc(s):

Using this Gc function, we calculate T(s):

Once again drawing the zero/pole magnitude tree of T(s) by hand:

Which results in the following hand drawn magnitude bode plot of T(s) by hand:

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This time, we see that the zero compensation has led to our cutoff frequency being 100kHz. The design
was tested and seemed to work well. Hand drawing the zero/pole phase tree of T(s) by hand:

Resulting in the following hand-drawn phase plot of the Buck Converter’s T(s):

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Task 7: Simulation
The following Simulink/PLECS schematic was used to simulate the Forward Converter:

And the following Simulink/PLECS schematic was used to simulate the Buck Converter:

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Showcasing the control system, in which 3 of the 4 quadrants are seen in a single timespan. The Vout
value has a very high resistance to changes in the input voltage, Vg, and the Vin2 value has a very high
resistance to changes in R.

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Verifying the ripple voltage is difficult due to control feedback effects, but overall the specification is
met.

For an example of ripple current:

Conclusion
This project was a good exercise in real world design. There was a lot of consideration and compromise
throughout the entire design. The most successful parts were finding the conduction power consumption
and evaluating all of the equations. The least successful part was determining the power loss due to
switching devices, as many times the datasheet did not have the information I require to calculate this. A
difficult part was designing the controllers. It seemed to be a partial calculation and partial trial-and-error
until I got something that was reasonable.

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Parts Selection
L1 http://www.digikey.com/product-
search/en?vendor=0&keywords=RB8522-36-1M5

L2 http://www.digikey.com/product-detail/en/RB6132-25-0M5/817-1668-
ND/3125504

Cin http://www.digikey.com/product-
detail/en/B43501A3107M/B43501A3107M-ND/3496250

C2 http://www.digikey.com/product-
detail/en/B43504E2277M/B43504E2277M-ND/3497874

Cout http://www.digikey.com/product-detail/en/EEH-ZA1E101XP/P15436CT-
ND/3088146

Q1-Q4 http://www.digikey.com/product-detail/en/STL36N55M5/497-13601-1-
ND/3910869

Q5 http://www.digikey.com/product-
detail/en/IPP50CN10N%20G/IPP50CN10NGIN-ND/1282062

D1-D2 http://www.digikey.com/product-detail/en/VS-10ETS12PBF/VS-
10ETS12PBF-ND/2632112

D3 http://www.digikey.com/product-detail/en/SBRT20U50SLP-
13/SBRT20U50SLP-13DITR-ND/4570623

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