Work Shop On Chip Process Design and

Analytical Testing (24th to 29th October, 2016)

Date: 25th OCT, 2016.

2nd Day Activity
(Hands-On Session on Mentor Graphics IC Design Tools)
Trainer: Engr. Faraz Qayyum

Advanced Electronics Laboratories

 HAND OUTS (Day-2)
Hands on Introduction to Mentor Graphics IC Design Tools
Advanced Electronics Laboratories "Work Shop On Chip Process Design and Analytical Testing" (24th to 29th October, 2016)

Getting started:
Log onto your Linux machine using the given username & password. Before creating design, you must
create a folder hierarchy for storing all the design files. Right click computer icon on desktop and click
browse folder, open File System> workshop. Create a folder named inverter and two sub folder named
schematic & layout in it. To generate the schematic design of your circuit using Pyxis Schematic. Open
terminal window by right clicking on desktop, Invoke Pyxis Schematic by entering following commands:
- source set_env.sh
- adk_daic &
You will see the main interface of Pyxis Schematic tool.

Setting the Lab Environment:

Setting the lab environment means to set up the working
directory (Location) of your project. In the main interface of
Pyxis Schematic, sequentially follow the path:
- MGC > Location Map > Set Working Directory
Mention the desired location of your project (like: /workshop/inverter/schematic).

Creating Schematic for Inverter:

Open a new design sheet for schematic from:
- File > Open >Schematic.
Enter name of your file as inverter after the
working directory path set already. An editable
blank sheet will show up. Click ADK IC Library in
schematic edit palette to your right. Components
you need in creating an inverter are:
- nmos, pmos, VDD, GND, In & Out.
Refer to the schematic ahead to insert
components from ADK IC Library:

Useful Shortcuts:
Esc → Exit.
F2 → Deselect All.
F3 → Add Wire.
Shift+F7→ Port Name.

After the schematic is captured, you need to check

the schematic to make sure there are no errors on
it. At the main menu, click on File > Check

Instructor: Engr. Faraz Qayyum

faraz.qayyum@iiu.edu.pk 1
 HAND OUTS (Day-2)
Hands on Introduction to Mentor Graphics IC Design Tools
Advanced Electronics Laboratories "Work Shop On Chip Process Design and Analytical Testing" (24th to 29th October, 2016)
Schematic. Check to see if the process passed or failed. Notice that at the bottom of the window, it reads
“passed check”. Click “Prepare for Layout” button to your right once you have completed the schematic.
Prepare for Layout script will create the viewpoints needed for layout and verification. You only have to do
this once per design after finalizing your schematic.

Generating Symbol and Saving Schematic:

Generating Symbol for a block is sometimes helpful to distinguish between different design cells. You can
generate a symbol by clicking on Add > Generate Symbol from the main menu. The symbol generated will
be seen. To check the symbol, click on File > Check Symbol at the main menu. Check to make sure the
symbol passed check at the bottom of the window. Save the symbol by clicking File > Save Symbol > Default
& Register the component created.

Creating a testbench for Simulation:

Prior to simulation a testbench
needs to be created that sets the
environment used to create
stimulus to simulate a design cell.
What you need to do next is to
create a testbench graphically.
Click on Session at the palette on
the right and open a new schematic
sheet with name testbench. An
empty schematic window pops up.
The first thing you need to do is to
instantiate your inverter design in
the testbench. Click on Add >Add
Instance on the main menu bar. An
Add Instance window pops up.
Select the inverter which is the
inverter symbol that you have
designed earlier. After placing the inverter, click on ADK IC Library. Components you need to add to the test
bench are:
- VDD, DC, GND & PULSE.
Refer to the diagram shown to insert the components and to connect the wires.
To modify the DC source, click on the DC source and it will be highlighted. Then, right click and select Edit
Properties to modify DC Source parameters. An Edit Object window pops up. On the DC column, change
value to 3.3V.
Similarly, to modify the PULSE source select Edit Properties and modify it as shown in figure above. Update
net names (inputs, outputs) using shift+F7. After creating the testbench, you now need to check the
schematic of the testbench to make sure it is correct. To check schematic, click on File>Check Schematic
from the main menu. Once passed, save the schematic by clicking on File> Save Sheet>Default or the blue
diskette tab.

Instructor: Engr. Faraz Qayyum

faraz.qayyum@iiu.edu.pk 2
 HAND OUTS (Day-2)
Hands on Introduction to Mentor Graphics IC Design Tools
Advanced Electronics Laboratories "Work Shop On Chip Process Design and Analytical Testing" (24th to 29th October, 2016)
Simulation mode:
Click on the Simulation in right palette. The schematic of the design in simulation mode will pop up.
Setup Simulator Viewer:
While in simulation mode click Setup Simulator Viewer button to the left. A popup menu appears.
Select Eldo as simulator and check Start EZwave automatically.
Setup Library Path:
Select the next button that is Setup include Path and set the include path for model library inside
your design kit and select the specific model based on the technology of your choice. Key in (or
browse) the path:
- /usr/local/MGCinstalled/adk3_1/technology/ic/models/ tsmc035.mod.
Setup Analysis:
The most important part of the simulation is the selection of Analysis type. Click on Setup
Analyses on the left a Setup Simulation window pops up. Choose Transient and click Apply. Click
on Analysis Setup and select Transient from dropdown menu for detailed entry of parameters.
A Setup Transient Analysis window will appear. Change the Stop Time to 100ns and Time Step to be 1ns.
Probes for Viewing Waveforms:
Click Probes in the left menu. In the Setup Simulation Window input ports to view waveforms
after simulation. You can update ports in that menu by simply clicking on ports one by one
graphically. You can just click on Run Eldo. This option will automatically run the netlist option
and then simulate. If your simulation is successfully done, you’ll be able to View waves like shown below:

Instructor: Engr. Faraz Qayyum

faraz.qayyum@iiu.edu.pk 3
 HAND OUTS (Day-2)
Hands on Introduction to Mentor Graphics IC Design Tools
Advanced Electronics Laboratories "Work Shop On Chip Process Design and Analytical Testing" (24th to 29th October, 2016)

Layout Design of the Inverter:

To invoke Pyxis Layout necessary steps involve the following commands in the terminal window.
- source set_env.sh
- adk_ic &
In Pyxis Layout window set the working directory from:
- MGC > Location Map > Set Working Directory
Mention the desired location of your project (like:
/workshop/inverter/layout) as done previously for Pyxis
Schematic.
To open an editable worksheet in Pyxis Layout window
select File> New> Layout from top menu, in the New
Layout window from left menu select Connectivity>
Existing View Point. Now in Viewpoint field browse to the
directory where you saved schematic for your inverter
and select sdl. Also select the Logic Loading Options and
set the hierarchy to Flat. In the New Layout Window enter
desired cell name and provide the tsmc035 process file,
rules file and in Options attach the Library file and make
the Angle Mode to All. Finally, click ‘OK’ in the New Layout
window. The logic window also pop up automatically to
confirm the binding.
Follow the path to attach above mentioned library files:
- /usr/local/MGCinstalled/adk3_1/technology/ic/process/
To make all points you click snap to one lambda we can set
the Grid size. To do that go to top menu Setup>
Preferences. A pop up window appears select the tab
Display> Ruler/Grid and Provide the values as shown.
Port Names are invisible by default and can be turned on
from top menu Setup> Preferences and Display> Objects,
just tick the item “Port/Pin Names”.
Now we have set the working environment as per our
needs and we are set to create the layout design of our
device.
Schematic Driven Layout:
Schematic driven layout is the concept in IC Layout where
the EDA software links the schematic and layout
databases. It was one of the first big steps forward in
layout software from the days when editing tools were
simply handling drawn polygons. Schematic driven layout
allows for several features that make the layout designer’s job easier and faster. One of the most important

Instructor: Engr. Faraz Qayyum

faraz.qayyum@iiu.edu.pk 4
 HAND OUTS (Day-2)
Hands on Introduction to Mentor Graphics IC Design Tools
Advanced Electronics Laboratories "Work Shop On Chip Process Design and Analytical Testing" (24th to 29th October, 2016)
advantage is that the changes to the circuit schematic are easily translated to the layout. Others include
connections between components in the schematic are graphically displayed as overflows in the layout
ensuring work is correct by construction.

Manual and auto instantiation:

Now when the empty cell has been opened, click on the DLA
Layout button (on the right side ic palette) This will bring up the
DLA Layout palette which has got all the major functionalities
needed for doing your SDL design.
Now you have to place the devices into your cell. For this
purpose there are 2 options available.
• Automatically place the devices (called Auto instantiation).
• Manually place the devices one by one.
Click on Autolnst in the DLA Layout palette.
The tools will locate devices that are of the same type and have
connectivity such that diffusion regions may be shared. The cell
will be automatically generated based on the length and width
parameters specified for the instances. The location of the
placed cell will be according to that in the schematic. You may
have to spread out the transistors a little to make space for the
connections.
If you don’t like the locations of cells placed by auto-inst feature
you can go for manual instantiation by clicking the inst button
in the DLA Layout palette, this will let you place each instance
(cell) one by one at your desired location.

Routing and Port Placement:

Once you placed the transistors, Fly lines (in
yellow) will show you the connectivity points
you need to draw on your circuit. As you wire
the circuit together, these overflows will
disappear when you have made the correct
connections.
To wire up the metal together you can use
AutoR from the same DLA layout palette this
will automatically route the connection. For
auto routing select the overflow and click on
AutoR, this will open the AUTOROU OV popup
menu and you will be asked to mention the
probe extent (the area which you allow the
router to use on cell), once you provided that,

Instructor: Engr. Faraz Qayyum

faraz.qayyum@iiu.edu.pk 5
 HAND OUTS (Day-2)
Hands on Introduction to Mentor Graphics IC Design Tools
Advanced Electronics Laboratories "Work Shop On Chip Process Design and Analytical Testing" (24th to 29th October, 2016)
routing will be done automatically. Or you can use AddR within ADK Edit Palette. This will prompt you for a
starting and ending point of a route.
Make the starting point on the metal contact between the two PMOS
Transistors. Notice to the right of the pointer, it says M1. This shows
that you are on routing layer1 (or metal1). Once you have selected
the starting point for the route, a guide will appear showing you the
clearance where you can place the route without any problems.
Draw the metal path leaving a knee-bend as shown in the Figure by
simply clicking at each corner. This will allow room for adding ports
later. Finally click on the pin of the NMOS to complete the route.
One important thing to be discussed here is that you cannot connect
polysilicon using this method since you cannot place routes in poly
because the AddR is used for routing layers only and poly is not a
routing layer.
Now select Path button from ADK Edit Palette. You will be prompted
for a location. Before placing the path, click on the Options button
on the prompt bar. Choose the layer name in the dialog box, or click
on the poly layer in the layer palette at the top-right corner of the
window after you have specified the width. You need to change the
width to 2λ. Select the Keep Option Settings box and exit the dialog
box. Now you are ready to place a route on the poly layer. Wire up
the gate inputs with poly. When you have made a complete
connection, the overflow line will disappear. If you need to use
metal, then you can simply click on the metal layer in the layer
palette (or on the contact to place a contact). Remember to change
the width as needed. Finally make sure to wire all the overflows.
To place the ports, select the two inputs and the output in your
schematic window. Then make the layout window active, again, and
click on Port in the DLA Layout palette menu. You are prompted to
put these ports one by one. The net for the current port to be placed
is highlighted in the layout window. This makes it easier to see which
port is being placed. Place the ports near half way between the two
transistors. Note that the ports are not yet connected to the
transistors. It is preferred to put the I/O ports near the middle of the
cell, but not necessary. Align them next to each other allowing some
room for routing later. But you should put the VDD port above the
PMOS and GND port below the NMOS and then resize the ports.
Now the overflows to the ports will be visible so you should wire up
the ports in the same manner described above. Notice there are still
two overflow lines? You will place diffusion contacts to bias the wells.
There are two macros for these. nwc: will give you an n-well contact.

Instructor: Engr. Faraz Qayyum

faraz.qayyum@iiu.edu.pk 6
 HAND OUTS (Day-2)
Hands on Introduction to Mentor Graphics IC Design Tools
Advanced Electronics Laboratories "Work Shop On Chip Process Design and Analytical Testing" (24th to 29th October, 2016)
pwc: will give you a p-well contact. You should place an n-well
contact on the VDD rail so that the contact’s top edge is
coincident with the top edge of the VDD rail. The p-well contact
should be placed on the Ground rail so that its bottom edge is
coincident with the bottom edge of the rail.

Some Useful Shortcuts:

Following shortcuts can be used to do your work more quickly
after pressing the spacebar on your keyboard.
p → To add polysilicon.
m → To add metal line.
pc → To add poly contact to access polysilicon from
Metal1.
pp → To add place port via for connecting Metal1 &
Metal2 layers.

Design Rule Check:

After completing the Layout design DRC (Design Rule Check)
must be performed just to make sure that the Layout design is
free of any errors. This option will check your design for errors
keeping in view the rule provided initially for the design. To
perform DRC on the developed design, go to ADK Edit palette,
under verification select Drc>Check. Check your message area
for total no of results to identify the no. of errors found in your
design. Go to Drc>First to check the first error and the
suggested solution to remove it. When results count come
down to zero you are done with the design and you can save
the design file.

Instructor: Engr. Faraz Qayyum

faraz.qayyum@iiu.edu.pk 7