CT 111 Notes - Logic Circuits From References

Binary Adder
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Binary Adders are arithmetic circuits in the form of half-adders and full-adders used to add together
two binary digits
Another common and very useful combinational logic circuit which can be constructed
using just a few basic logic gates allowing it to add together two or more binary numbers is
the Binary Adder.
A basic Binary Adder circuit can be made from standard AND and Ex-OR gates allowing
us to “add” together two single bit binary numbers, A and B.
The addition of these two digits produces an output called the SUM of the addition and a
second output called the CARRY or Carry-out, ( COUT ) bit according to the rules for binary
addition. One of the main uses for the Binary Adder is in arithmetic and counting circuits.
Consider the simple addition of the two denary (base 10) numbers below.
From our math lessons at school, we learnt that each number column is added together
starting from the right hand side and that each digit has a weighted value depending upon
its position within the columns.
When each column is added together a carry is generated if the result is greater or equal
to 10, the base number. This carry is then added to the result of the addition of the next
column to the left and so on, simple school math’s addition, add the numbers and carry.
The adding of binary numbers is exactly the same idea as that for adding together decimal
numbers but this time a carry is only generated when the result in any column is greater or
equal to “2”, the base number of binary. In other words 1 + 1 creates a carry.
Binary Addition
Binary Addition follows these same basic rules as for the denary addition above except
in binary there are only two digits with the largest digit being “1”. So when adding binary
numbers, a carry out is generated when the “SUM” equals or is greater than two (1+1) and
this becomes a “CARRY” bit for any subsequent addition being passed over to the next
column for addition and so on. Consider the single bit addition below.
Binary Addition of Two Bits
When the two single bits, A and B are added together, the addition of “0 + 0”, “0 + 1” and
“1 + 0” results in either a “0” or a “1” until you get to the final column of “1 + 1” then the
sum is equal to “2”. But the number two does not exists in binary however, 2 in binary is
equal to 10, in other words a zero for the sum plus an extra carry bit.
Then the operation of a simple adder requires two data inputs producing two outputs, the
Sum (S) of the equation and a Carry (C) bit as shown.
Binary Adder Block Diagram
For the simple 1-bit addition problem above, the resulting carry bit could be ignored but
you may have noticed something else with regards to the addition of these two bits, the
sum of their binary addition resembles that of an Exclusive-OR Gate. If we label the two
bits as A and B then the resulting truth table is the sum of the two bits but without the final
carry.
2-input Exclusive-OR Gate

Symbol Truth Table
B A S
0 0 0
0 1 1
2-input Ex-OR Gate
1 0 1
1 1 0
We can see from the truth table above, that an Exclusive-OR gate only produces an
output “1” when either input is at logic “1”, but not both the same as for the binary addition
of the previous two bits. However in order to perform the addition of two numbers,
microprocessors and electronic calculators require the extra carry bit to correctly calculate
the equations so we need to rewrite the previous summation to include two-bits of output
data as shown below.
From the above equations we now know that an Exclusive-OR gate will only produce an
output “1” when “EITHER” input is at logic “1”, so we need an additional output to produce
the carry bit when “BOTH” inputs A and B are at logic “1”. One digital gate that fits the bill
perfectly producing an output “1” when both of its inputs A and B are “1” (HIGH) is the
standard AND Gate.
2-input AND Gate

Symbol Truth Table
B A C
0 0 0
0 1 0
2-input AND Gate
1 0 0
1 1 1
By combining the Exclusive-OR gate with the AND gate results in a simple digital binary
adder circuit known commonly as the “Half Adder” circuit.
A Half Adder Circuit

A half adder is a logical circuit that performs an addition operation on two binary digits.
The half adder produces a sum and a carry value which are both binary digits.
Half Adder Truth Table with Carry-Out

Symbol Truth Table
B A SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
From the truth table of the half adder we can see that the SUM (S) output is the result of
the Exclusive-OR gate and the Carry-out (Cout) is the result of the AND gate. Then the
Boolean expression for a half adder is as follows.
For the SUM bit:
SUM = A XOR B = A ⊕ B
For the CARRY bit:
CARRY = A AND B = A.B
One major disadvantage of the Half Adder circuit when used as a binary adder, is that
there is no provision for a “Carry-in” from the previous circuit when adding together
multiple data bits.
For example, suppose we want to add together two 8-bit bytes of data, any resulting carry
bit would need to be able to “ripple” or move across the bit patterns starting from the least
significant bit (LSB). The most complicated operation the half adder can do is “1 + 1” but
as the half adder has no carry input the resultant added value would be incorrect. One
simple way to overcome this problem is to use a Full Adder type binary adder circuit.
A Full Adder Circuit

The main difference between the Full Adder and the previous Half Adder is that a full
adder has three inputs. The same two single bit data inputs A and B as before plus an
additional Carry-in (C-in) input to receive the carry from a previous stage as shown below.
Full Adder Block Diagram
Then the full adder is a logical circuit that performs an addition operation on three binary
digits and just like the half adder, it also generates a carry out to the next addition column.
Then a Carry-in is a possible carry from a less significant digit, while a Carry-
out represents a carry to a more significant digit.
In many ways, the full adder can be thought of as two half adders connected together,
with the first half adder passing its carry to the second half adder as shown.
Full Adder Logic Diagram
As the full adder circuit above is basically two half adders connected together, the truth
table for the full adder includes an additional column to take into account the Carry-
in, CINinput as well as the summed output, S and the Carry-out, COUT bit.
Full Adder Truth Table with Carry
Symbol Truth Table
C-in B A Sum C-out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Then the Boolean expression for a full adder is as follows.
For the SUM (S) bit:
SUM = (A XOR B) XOR Cin = (A ⊕ B) ⊕ Cin

For the CARRY-OUT (Cout) bit:
CARRY-OUT = A AND B OR Cin(A XOR B) = A.B + Cin(A ⊕ B)
An n-bit Binary Adder

We have seen above that single 1-bit binary adders can be constructed from basic logic
gates. But what if we wanted to add together two n-bit numbers, then n number of 1-bit full
adders need to be connected or “cascaded” together to produce what is known as
a Ripple Carry Adder.
A “ripple carry adder” is simply “n“, 1-bit full adders cascaded together with each full adder
representing a single weighted column in a long binary addition. It is called a ripple carry
adder because the carry signals produce a “ripple” effect through the binary adder from
right to left, (LSB to MSB).
For example, suppose we want to “add” together two 4-bit numbers, the two outputs of the
first full adder will provide the first place digit sum (S) of the addition plus a carry-out bit
that acts as the carry-in digit of the next binary adder.
The second binary adder in the chain also produces a summed output (the 2nd bit) plus
another carry-out bit and we can keep adding more full adders to the combination to add
larger numbers, linking the carry bit output from the first full binary adder to the next full
adder, and so forth. An example of a 4-bit adder is given below.
A 4-bit Ripple Carry Adder
One main disadvantage of “cascading” together 1-bit binary adders to add large binary
numbers is that if inputs A and B change, the sum at its output will not be valid until any
carry-input has “rippled” through every full adder in the chain because the MSB (most
significant bit) of the sum has to wait for any changes from the carry input of the LSB (less
significant bit). Consequently, there will be a finite delay before the output of the adder
responds to any change in its inputs resulting in a accumulated delay.
When the size of the bits being added is not too large for example, 4 or 8 bits, or the
summing speed of the adder is not important, this delay may not be important. However,
when the size of the bits is larger for example 32 or 64 bits used in multi-bit adders, or
summation is required at a very high clock speed, this delay may become prohibitively
large with the addition processes not being completed correctly within one clock cycle.
This unwanted delay time is called Propagation delay. Also another problem called
“overflow” occurs when an n-bit adder adds two parallel numbers together whose sum is
greater than or equal to 2n
One solution is to generate the carry-input signals directly from the A and B inputs rather
than using the ripple arrangement above. This then produces another type of binary adder
circuit called a Carry Look Ahead Binary Adder where the speed of the parallel adder
can be greatly improved using carry-look ahead logic.
The advantage of carry look ahead adders is that the length of time a carry look ahead
adder needs in order to produce the correct SUM is independent of the number of data
bits used in the operation, unlike the cycle time a parallel ripple adder needs to complete
the SUM which is a function of the total number of bits in the addend.
4-bit full adder circuits with carry look ahead features are available as standard IC
packages in the form of the TTL 4-bit binary adder 74LS83 or the 74LS283 and the CMOS
4008 which can add together two 4-bit binary numbers and generate a SUM and
a CARRYoutput as shown.
74LS83 Logic Symbol

Summary of Binary Adders
We have seen in this tutorial about Binary Adders that adder circuits can be used to
“add” together two binary numbers producing a “carry-out”. In its most basic form, adders
can be made from connecting together an Exclusive-OR gate with an AND gate to
produce a Half Adder circuit. Two half adders can be combined to produce a Full Adder.
There are a number of 4-bit full-adder ICs available such as the 74LS283 and CD4008.
which will add two 4-bit binary number and provide an additional input carry bit, as well as
an output carry bit, so you can cascade them together to produce 8-bit, 12-bit, 16-bit,
adders but the carry propagation delay can be a major issue in large n-bit ripple adders.
Display Decoder
A Display Decoder is a combinational circuit which decodes and n-bit input value into a number of
output lines to drive a display
A Digital Decoder IC, is a device which converts one digital format into another and one
of the most commonly used devices for doing this is called the Binary Coded Decimal
(BCD) to 7-Segment Display Decoder.
7-segment LED (Light Emitting Diode) or LCD (Liquid Crystal Display) type displays,
provide a very convenient way of displaying information or digital data in the form of
numbers, letters or even alpha-numerical characters.
Typically 7-segment displays consist of seven individual coloured LED’s (called the
segments), within one single display package. In order to produce the required numbers
or HEX characters from 0 to 9 and A to F respectively, on the display the correct
combination of LED segments need to be illuminated and BCD to 7-segment Display
Decoders such as the 74LS47 do just that.
A standard 7-segment LED display generally has eight (8) input connections, one for each
LED segment and one that acts as a common terminal or connection for all the internal
display segments. Some single displays have also have an additional input pin to display
a decimal point in their lower right or left hand corner.
In electronics there are two important types of 7-segment LED digital display.
 1. The Common Cathode Display (CCD) – In the common cathode display, all the
cathode connections of the LED’s are joined together to logic “0” or ground. The
individual segments are illuminated by application of a “HIGH”, logic “1” signal to the
individual Anode terminals.
 2. The Common Anode Display (CAD) – In the common anode display, all the
anode connections of the LED’s are joined together to logic “1” and the individual
segments are illuminated by connecting the individual Cathode terminals to a “LOW”,
logic “0” signal.
Common Cathode and Common Anode Format
Electrical connection of the individual diodes for a common cathode display and a
common anode display and by illuminating each light emitting diode individually, they can
be made to display a variety of numbers or characters.
7-Segment Display Format
So in order to display the number “3” for example, segments a, b, c, d and g would need
to be illuminated. If we wanted to display a different number or letter then a different set of
segments would need to be illuminated. Then for a 7-segment display, we can produce a
truth table giving the segments that need to be illuminated in order to produce the required
character as shown below.
Truth Table for a 7-segment display
Individual Segments Individual Segments

Display Display
a b c d e f g a b c d e f g
× × × × × × 0 × × × × × × × 8
× × 1 × × × × × × 9
× × × × × 2 × × × × × × A
× × × × × 3 × × × × × b
× × × × 4 × × × × C
× × × × × 5 × × × × × d
× × × × × × 6 × × × × × E
× × × 7 × × × × F
7-Segment Display Elements for all Numbers.
It can be seen that to display any single digit number from 0 to 9 in binary or letters
from A to F in hexadecimal, we would require seven separate segment connections plus
one additional connection for the LED’s “common” connection. Also as the segments are
basically a standard light emitting diode, the driving circuit would need to produce up to
20mA of current to illuminate each individual segment and to display the number “8”, all
seven segments would need to be lit resulting a total current of nearly 140mA, (8 x 20mA).
Obviously, the use of so many connections and power consumption is impractical for
some electronic or microprocessor based circuits and so in order to reduce the number of
signal lines required to drive just one single display, display decoders such as the BCD to
7-Segment Display Decoder and Driver IC’s are used instead.
Binary Coded Decimal

Binary Coded Decimal (BCD or “8421” BCD) numbers are made up using just 4 data bits
(a nibble or half a byte) similar to the Hexadecimal numbers we saw in the binary tutorial,
but unlike hexadecimal numbers that range in full from 0 through to F, BCD numbers only
range from 0 to 9, with the binary number patterns of 1010 through to 1111 (A to F) being
invalid inputs for this type of display and so are not used as shown below.
Binary Pattern Binary Pattern

Decimal BCD Decimal BCD
8 4 2 1 8 4 2 1
0 0 0 0 0 0 8 1 0 0 0 8
1 0 0 0 1 1 9 1 0 0 1 9
2 0 0 1 0 2 10 1 0 1 0 Invalid
3 0 0 1 1 3 11 1 0 1 1 Invalid
4 0 1 0 0 4 12 1 1 0 0 Invalid
5 0 1 0 1 5 13 1 1 0 1 Invalid
6 0 1 1 0 6 14 1 1 1 0 Invalid
7 0 1 1 1 7 15 1 1 1 1 Invalid
BCD to 7-Segment Display Decoders

A binary coded decimal (BCD) to 7-segment display decoder such as the TTL 74LS47 or
74LS48, have 4 BCD inputs and 7 output lines, one for each LED segment. This allows a
smaller 4-bit binary number (half a byte) to be used to display all the denary numbers
from 0 to 9 and by adding two displays together, a full range of numbers from 00 to 99 can
be displayed with just a single byte of eight data bits.
BCD to 7-Segment Decoder
The use of packed BCD allows two BCD digits to be stored within a single byte (8-bits) of
data, allowing a single data byte to hold a BCD number in the range of 00 to 99.
An example of the 4-bit BCD input ( 0100 ) representing the number “4” is given below.
Display Decoder Example No1
In practice current limiting resistors of about 150Ω to 220Ω would be connected in series
between the decoder/driver chip and each LED display segment to limit the maximum
current flow. There are different display decoders and drivers available for the different
types of available displays, either LED or LCD. For example, the 74LS48 for common-
cathode LED types, the 74LS47 for common-anode LED types, or the CMOS CD4543 for
liquid crystal display (LCD) types.
Liquid crystal displays (LCD´s) have one major advantage over similar LED types in that
they consume much less power and nowadays, both LCD and LED displays are combined
together to form larger Dot-Matrix Alphanumeric type displays which can show letters and
characters as well as numbers in standard Red or Tri-colour outputs.
Binary Decoder
Binary Decoder is another combinational logic circuit constructed from individual logic gates and is
the exact opposite to that of an Encoder
The name “Decoder” means to translate or decode coded information from one format into
another, so a binary decoder transforms “n” binary input signals into an equivalent code
using 2n outputs.
Binary Decoders are another type of digital logic device that has inputs of 2-bit, 3-bit or 4-
bit codes depending upon the number of data input lines, so a decoder that has a set of
two or more bits will be defined as having an n-bit code, and therefore it will be possible to
represent 2n possible values. Thus, a decoder generally decodes a binary value into a
non-binary one by setting exactly one of its n outputs to logic “1”.
If a binary decoder receives n inputs (usually grouped as a single Binary or Boolean
number) it activates one and only one of its 2n outputs based on that input with all other
outputs deactivated.
So for example, an inverter ( NOT-gate ) can be classed as a 1-to-2 binary decoder as 1-

input and 2-outputs (21) is possible because with an input A it can produce two
outputs A and A (not-A) as shown.
Then we can say that a standard combinational logic decoder is an n-to-m decoder,
where m ≤ 2n, and whose output, Q is dependent only on its present input states. In other
words, a binary decoder looks at its current inputs, determines which binary code or binary
number is present at its inputs and selects the appropriate output that corresponds to that
binary input.
A Binary Decoder converts coded inputs into coded outputs, where the input and output
codes are different and decoders are available to “decode” either a Binary or BCD (8421
code) input pattern to typically a Decimal output code. Commonly available BCD-to-
Decimal decoders include the TTL 7442 or the CMOS 4028. Generally a decoders output
code normally has more bits than its input code and practical “binary decoder” circuits
include, 2-to-4, 3-to-8 and 4-to-16 line configurations.
An example of a 2-to-4 line decoder along with its truth table is given as:
A 2-to-4 Binary Decoders
This simple example above of a 2-to-4 line binary decoder consists of an array of
four AND gates. The 2 binary inputs labelled A and B are decoded into one of 4 outputs,
hence the description of 2-to-4 binary decoder. Each output represents one of the
miniterms of the 2 input variables, (each output = a miniterm).
The binary inputs A and B determine which output line from Q0 to Q3 is “HIGH” at logic
level “1” while the remaining outputs are held “LOW” at logic “0” so only one output can be
active (HIGH) at any one time. Therefore, whichever output line is “HIGH” identifies the
binary code present at the input, in other words it “de-codes” the binary input.
Some binary decoders have an additional input pin labelled “Enable” that controls the
outputs from the device. This extra input allows the decoders outputs to be turned “ON” or
“OFF” as required. These types of binary decoders are commonly used as “memory
address decoders” in microprocessor memory applications.
74LS138 Binary Decoder

We can say that a binary decoder is a demultiplexer with an additional data line that is
used to enable the decoder. An alternative way of looking at the decoder circuit is to
regard inputs A, B and C as address signals. Each combination of A, B or C defines a
unique memory address.
We have seen that a 2-to-4 line binary decoder (TTL 74155) can be used for decoding any
2-bit binary code to provide four outputs, one for each possible input combination.
However, sometimes it is required to have a Binary Decoder with a number of outputs
greater than is available, so by adding more inputs, the decoder can potentially provide
2n more outputs.
So for example, a decoder with 3 binary inputs ( n = 3 ), would produce a 3-to-8 line
decoder (TTL 74138) and 4 inputs ( n = 4 ) would produce a 4-to-16 line decoder (TTL
74154) and so on. But a decoder can also have less than 2n outputs such as the BCD to
seven-segment decoder (TTL 7447) which has 4 inputs and only 7 active outputs to drive
a display rather than the full 16 (24) outputs as you would expect.
Here a much larger 4 (3 data plus 1 enable) to 16 line binary decoder has been
implemented using two smaller 3-to-8 decoders.
A 4-to-16 Binary Decoder Configuration
Inputs A, B, C are used to select which output on either decoder will be at logic “1” (HIGH)
and input D is used with the enable input to select which encoder either the first or second
will output the “1”.
However, there is a limit to the number of inputs that can be used for one particular
decoder, because as n increases, the number of AND gates required to produce an output
also becomes larger resulting in the fan-out of the gates used to drive them becoming
large.
This type of active-“HIGH” decoder can be implemented using just Inverters, ( NOT
Gates ) and AND gates. It is convenient to use an AND gate as the basic decoding
element for the output because it produces a “HIGH” or logic “1” output only when all of its
inputs are logic “1”.
But some binary decoders are constructed using NAND gates instead of AND gates for
their decoded output, since NAND gates are cheaper to produce than AND’s as they
require fewer transistors to implement within their design.
The use of NAND gates as the decoding element, results in an active-“LOW” output while
the rest will be “HIGH”. As a NAND gate produces the AND operation with an inverted
output, the NAND decoder looks like this with its inverted truth table.
2-to-4 Line NAND Binary Decoder
Then for the NAND decoder, only one output can be LOW and equal to logic “0” at any
given time, with all the other outputs being HIGH at logic “1”.
Decoders are also available with an additional “Enable” input pin which allows the
decoded output to be turned “ON” or “OFF” by applying a logic “1” or logic “0” respectively
to it. So for example, when the enable input is at logic level “0”, (EN = 0) all outputs are
“OFF” at logic “0” (for AND gates) regardless of the state of the inputs A and B.
Generally to implement this enabling function the 2-input AND or NAND gates are
replaced with 3-input AND or NAND gates. The additional input pin represents the enable
function.
Memory Address Decoder

Binary Decoders are most often used in more complex digital systems to access a
particular memory location based on an “address” produced by a computing device. In
modern microprocessor systems the amount of memory required can be quite high and is
generally more than one single memory chip alone.
One method of overcoming this problem is to connect lots of individual memory chips
together and to read the data on a common “Data Bus”. In order to prevent the data being
“read” from each memory chip at the same time, each memory chip is selected individually
one at time and this process is known as Address Decoding.
In this type of application, the address represents the coded data input, and the outputs
are the particular memory element select signals. Each memory chip has an input
called Chip Select or CS which is used by the MPU (micro-processor unit) to select the
appropriate memory chip when required. Generally a logic “1” on the chip select (CS)
input selects the memory device while a logic “0” on the input de-selects it.
So by selecting or de-selecting each chip one at a time, allows us to select the correct
memory address device for a particular address location. The advantage of address
decoding is that when we specify a particular memory address, the corresponding
memory location exists ONLY in one of the chips.
For example, Lets assume we have a very simple microprocessor system with only 1Kb
(one thousand bytes) of RAM memory and 10 memory address lines available. The
memory consists of 128×8-bit (128×8 = 1024 bytes) devices and for 1Kb we would need 8
individual memory chips but in order to select the correct memory chip we would also
require a 3-to-8 line binary decoder as shown below.
Memory Address Decoding
The binary decoder requires only 3 address lines, (A0 to A2) to select each one of the 8
chips (the lower part of the address), while the remaining 8 address lines (A3 to A10) select
the correct memory location on that chip (the upper part of the address).
Having selected a memory location using the address bus, the information at the particular
internal memory location is sent to a common “Data Bus” for use by the microprocessor.
This is of course a simple example but the principals remain the same for all types of
memory chips or modules.
Binary Decoders are very useful devices for converting one digital format to another,
such as binary or BCD type data into decimal or octal etc and commonly available
decoder IC’s are the TTL 74LS138 3-to-8 line binary decoder or the 74ALS154 4-to-16
line decoder. They are also very useful for interfacing to 7-segment displays such as the
TTL 74LS47 which we will look at in the next tutorial.
Priority Encoder
Priority Encoders take all of their data inputs one at a time and converts them into an equivalent
binary code at its output
Unlike a multiplexer that selects one individual data input line and then sends that data to
a single output line or switch, Digital Encoder more commonly called a Binary
Encodertakes ALL its data inputs one at a time and then converts them into a single
encoded output. So we can say that a binary encoder, is a multi-input combinational logic
circuit that converts the logic level “1” data at its inputs into an equivalent binary code at its
output.
Generally, digital encoders produce outputs of 2-bit, 3-bit or 4-bit codes depending upon
the number of data input lines. An “n-bit” binary encoder has 2n input lines and n-bitoutput
lines with common types that include 4-to-2, 8-to-3 and 16-to-4 line configurations.
The output lines of a digital encoder generate the binary equivalent of the input line whose
value is equal to “1” and are available to encode either a decimal or hexadecimal input
pattern to typically a binary or “B.C.D” (binary coded decimal) output code.
4-to-2 Bit Binary Encoder
One of the main disadvantages of standard digital encoders is that they can generate the
wrong output code when there is more than one input present at logic level “1”. For
example, if we make inputs D1 and D2 HIGH at logic “1” both at the same time, the
resulting output is neither at “01” or at “10” but will be at “11” which is an output binary
number that is different to the actual input present. Also, an output code of all logic “0”s
can be generated when all of its inputs are at “0” OR when input D0 is equal to one.
One simple way to overcome this problem is to “Prioritise” the level of each input pin. So if
there is more than one input at logic level “1” at the same time, the actual output code
would only correspond to the input with the highest designated priority. Then this type of
digital encoder is known commonly as a Priority Encoder or P-encoder for short.
Priority Encoder
The Priority Encoder solves the problems mentioned above by allocating a priority level
to each input. The priority encoders output corresponds to the currently active input which
has the highest priority. So when an input with a higher priority is present, all other inputs
with a lower priority will be ignored.
The priority encoder comes in many different forms with an example of an 8-input priority
encoder along with its truth table shown below.
8-to-3 Bit Priority Encoder
Priority encoders are available in standard IC form and the TTL 74LS148 is an 8-to-3 bit
priority encoder which has eight active LOW (logic “0”) inputs and provides a 3-bit code of
the highest ranked input at its output.
Priority encoders output the highest order input first for example, if input lines “D2“, “D3”
and “D5” are applied simultaneously the output code would be for input “D5” (“101”) as
this has the highest order out of the 3 inputs. Once input “D5” had been removed the next
highest output code would be for input “D3” (“011”), and so on.
The truth table for a 8-to-3 bit priority encoder is given as:
Digital Inputs Binary Output
D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 X 0 0 1
0 0 0 0 0 1 X X 0 1 0
0 0 0 0 1 X X X 0 1 1
0 0 0 1 X X X X 1 0 0
0 0 1 X X X X X 1 0 1
0 1 X X X X X X 1 1 0
1 X X X X X X X 1 1 1
Where X equals “dont care”, that is logic “0” or a logic “1”.

From this truth table, the Boolean expression for the encoder above with data
inputs D0to D7 and outputs Q0, Q1, Q2 is given as:
Output Q0
Output Q1
Output Q2
Then the final Boolean expression for the priority encoder including the zero inputs is
defined as:
Priority Encoder Output Expression
In practice these zero inputs would be ignored allowing the implementation of the final
Boolean expression for the outputs of the 8-to-3 priority encoder. We can constructed a
simple encoder from the expression above using individual OR gates as follows.
Digital Encoder using Logic Gates

Digital Encoder Applications
Keyboard Encoder
Priority encoders can be used to reduce the number of wires needed in a particular
circuits or application that have multiple inputs. For example, assume that a
microcomputer needs to read the 104 keys of a standard QWERTY keyboard where only
one key would be pressed either “HIGH” or “LOW” at any one time.
One way would be to connect all 104 wires from the individual keys on the keyboard
directly to the computers input but this would be impractical for a small home PC. Another
alternative and better way would be to interface the keyboard to the PC using a priority
encoder.
The 104 individual buttons or keys could be encoded into a standard ASCII code of only 7-
bits (0 to 127 decimal) to represent each key or character of the keyboard and then input
as a much smaller 7-bit B.C.D code directly to the computer. Keypad encoders such as
the 74C923 20-key encoder are available to do just that.
Positional Encoders
Another more common application is in magnetic positional control as used on ships
navigation or for robotic arm positioning etc. Here for example, the angular or rotary
position of a compass is converted into a digital code by a 74LS148 8-to-3 line priority
encoder and input to the systems computer to provide navigational data and an example
of a simple 8 position to 3-bit output compass encoder is shown below. Magnets and reed
switches could be used at each compass point to indicate the needles angular position.
Priority Encoder Navigation

Binary Output
Compass Direction
Q0 Q1 Q2
North 0 0 0
North-East 0 0 1
East 0 1 0
South-East 0 1 1
South 1 0 0
South-West 1 0 1
West 1 1 0
North-West 1 1 1
Interrupt Requests
Other applications especially for Priority Encoders may include detecting interrupts in
microprocessor applications. Here the microprocessor uses interrupts to allow peripheral
devices such as the disk drive, scanner, mouse, or printer etc, to communicate with it, but
the microprocessor can only “talk” to one peripheral device at a time so needs some way
of knowing when a particular peripheral device wants to communicate with it.
The processor does this by using “Interrupt Requests” or “IRQ” signals to assign priority to
all the peripheral devices to ensure that the most important peripheral device is serviced
first. The order of importance of the devices will depend upon their connection to the
priority encoder.
IRQ Number Typical Use Description
IRQ 0 System timer Internal System Timer.
IRQ 1 Keyboard Keyboard Controller.
IRQ 3 COM2 & COM4 Second and Fourth Serial Port.
IRQ 4 COM1 & COM3 First and Third Serial Port.
IRQ 5 Sound Sound Card.
IRQ 6 Floppy disk Floppy Disk Controller.
IRQ 7 Parallel port Parallel Printer.
IRQ 12 Mouse PS/2 Mouse.
IRQ 14 Primary IDE Primary Hard Disk Controller.
IRQ 15 Secondary IDE Secondary Hard Disk Controller.

Because implementing such a system using priority encoders such as the standard
74LS148 priority encoder IC involves additional logic circuits, purpose built integrated
circuits such as the 8259 Programmable Priority Interrupt Controller is available.
Digital Encoder Summary

Then to summarise, the Digital Encoder is a combinational circuit that generates a
specific code at its outputs such as binary or BCD in response to one or more active
inputs. There are two main types of digital encoder. The Binary Encoder and the Priority
Encoder.
We have seen that the Binary Encoder converts one of 2n inputs into an n-bit output.
Then a binary encoder has fewer output bits than the input code. Binary encoders are
useful for compressing data and can be constructed from simple AND or OR gates.One of
the main disadvantages of a standard binary encoder is that it would produce an error at
its outputs if more than one input were active at the same time. To overcome this problem
priority encoders were developed.
The Priority Encoder is another type of combinational circuit similar to a binary encoder,
except that it generates an output code based on the highest prioritised input. Priority
encoders are used extensively in digital and computer systems as microprocessor
interrupt controllers where they detect the highest priority input.
In the next tutorial about combinational logic devices, we will look at complementary
function of the encoder called a Decoder which convert an n-bit input code to one of
its 2noutput lines.
The Demultiplexer
The demultiplexer is a combinational logic circuit designed to switch one common input line to one of
several seperate output line
The data distributor, known more commonly as a Demultiplexer or “Demux” for short, is
the exact opposite of the Multiplexer we saw in the previous tutorial.
The demultiplexer takes one single input data line and then switches it to any one of a
number of individual output lines one at a time. The demultiplexer converts a serial data
signal at the input to a parallel data at its output lines as shown below.
1-to-4 Channel De-multiplexer
Output Select
Data Output
Selected
a b
0 0 A
0 1 B
1 0 C
1 1 D
The Boolean expression for this 1-to-4 Demultiplexer above with outputs A to D and data
select lines a, b is given as:
The function of the Demultiplexer is to switch one common data input line to any one of
the 4 output data lines A to D in our example above. As with the multiplexer the individual
solid state switches are selected by the binary input address code on the output select
pins “a” and “b” as shown.
Demultiplexer Output Line Selection
As with the previous multiplexer circuit, adding more address line inputs it is possible to
switch more outputs giving a 1-to-2n data line outputs.
Some standard demultiplexer IC´s also have an additional “enable output” pin which
disables or prevents the input from being passed to the selected output. Also some have
latches built into their outputs to maintain the output logic level after the address inputs
have been changed.
However, in standard decoder type circuits the address input will determine which single
data output will have the same value as the data input with all other data outputs having
the value of logic “0”.
The implementation of the Boolean expression above using individual logic gates would
require the use of six individual gates consisting of AND and NOT gates as shown.
4 Channel Demultiplexer using Logic Gates
The symbol used in logic diagrams to identify a demultiplexer is as follows.
The Demultiplexer Symbol
Again, as with the previous multiplexer example, we can also use the demultiplexer to
digitally control the gain of an operational amplifier as shown.
Digitally Adjustable Amplifier Gain
The circuit above illustrates how to provide digitally controlled adjustable/variable op-amp
gain using a demultiplexer. The voltage gain of the inverting operational amplifier is
dependent upon the ratio between the input resistor, RIN and its feedback resistor, Rƒ as
determined in the Op-amp tutorials.
The digitally controlled analogue switches of the demultiplexer select an input resistor to
vary the value of Rin. The combination of these resistors will determine the overall voltage
gain of the amplifier, (Av). Then the voltage gain of the inverting operational amplifier can
be adjusted digitally simply by selecting the appropriate input resistor combination.
Standard Demultiplexer IC packages available are the TTL 74LS138 1 to 8-output
demultiplexer, the TTL 74LS139 Dual 1-to-4 output demultiplexer or the CMOS CD4514 1-
to-16 output demultiplexer.
Another type of demultiplexer is the 24-pin, 74LS154 which is a 4-bit to 16-line
demultiplexer/decoder. Here the individual output positions are selected using a 4-bit
binary coded input. Like multiplexers, demultiplexers can also be cascaded together to
form higher order demultiplexers.
Unlike multiplexers which convert data from a single data line to multiple lines and
demultiplexers which convert multiple lines to a single data line, there are devices
available which convert data to and from multiple lines and in the next tutorial about
combinational logic devices, we will look at Encoders which convert multiple input lines
into multiple output lines, converting the data from one form to another.
The Multiplexer
The multiplexer is a combinational logic circuit designed to switch one of several input lines to a
single common output line
Multiplexing is the generic term used to describe the operation of sending one or more
analogue or digital signals over a common transmission line at different times or speeds
and as such, the device we use to do just that is called a Multiplexer.
The multiplexer, shortened to “MUX” or “MPX”, is a combinational logic circuit designed to
switch one of several input lines through to a single common output line by the application
of a control signal. Multiplexers operate like very fast acting multiple position rotary
switches connecting or controlling multiple input lines called “channels” one at a time to
the output.
Multiplexers, or MUX’s, can be either digital circuits made from high speed logic gates
used to switch digital or binary data or they can be analogue types using transistors,
MOSFET’s or relays to switch one of the voltage or current inputs through to a single
output.
The most basic type of multiplexer device is that of a one-way rotary switch as shown.
Basic Multiplexing Switch
The rotary switch, also called a wafer switch as each layer of the switch is known as a
wafer, is a mechanical device whose input is selected by rotating a shaft. In other words,
the rotary switch is a manual switch that you can use to select individual data or signal
lines simply by turning its inputs “ON” or “OFF”. So how can we select each data input
automatically using a digital device.
In digital electronics, multiplexers are also known as data selectors because they can
“select” each input line, are constructed from individual Analogue Switches encased in a
single IC package as opposed to the “mechanical” type selectors such as normal
conventional switches and relays.
They are used as one method of reducing the number of logic gates required in a circuit
design or when a single data line or data bus is required to carry two or more different
digital signals. For example, a single 8-channel multiplexer.
Generally, the selection of each input line in a multiplexer is controlled by an additional set
of inputs called control lines and according to the binary condition of these control inputs,
either “HIGH” or “LOW” the appropriate data input is connected directly to the output.
Normally, a multiplexer has an even number of 2n data input lines and a number of
“control” inputs that correspond with the number of data inputs.
Note that multiplexers are different in operation to Encoders. Encoders are able to switch
an n-bit input pattern to multiple output lines that represent the binary coded (BCD) output
equivalent of the active input.
We can build a simple 2-line to 1-line (2-to-1) multiplexer from basic logic NAND gates as
shown.
2-input Multiplexer Design
The input A of this simple 2-1 line multiplexer circuit constructed from standard NAND
gates acts to control which input ( I0 or I1 ) gets passed to the output at Q.
From the truth table above, we can see that when the data select input, A is LOW at logic
0, input I1 passes its data through the NAND gate multiplexer circuit to the output, while
input I0 is blocked. When the data select A is HIGH at logic 1, the reverse happens and
now input I0 passes data to the output Q while input I1 is blocked.
So by the application of either a logic “0” or a logic “1” at A we can select the appropriate
input, I0 or I1 with the circuit acting a bit like a single pole double throw (SPDT) switch.
As we only have one control line, (A) then we can only switch 21 inputs and in this simple
example, the 2-input multiplexer connects one of two 1-bit sources to a common output,
producing a 2-to-1-line multiplexer. We can confirm this in the following Boolean
expression.
and for our 2-input multiplexer circuit above, this can be simplified too:
We can increase the number of data inputs to be selected further simply by following the
same procedure and larger multiplexer circuits can be implemented using smaller 2-to-1
multiplexers as their basic building blocks. So for a 4-input multiplexer we would therefore
require two data select lines as 4-inputs represents 22 data control lines give a circuit with
four inputs, I0, I1, I2, I3 and two data select lines A and B as shown.
4-to-1 Channel Multiplexer
The Boolean expression for this 4-to-1 Multiplexer above with inputs A to D and data
select lines a, b is given as:
In this example at any one instant in time only ONE of the four analogue switches is
closed, connecting only one of the input lines A to D to the single output at Q. As to which
switch is closed depends upon the addressing input code on lines “a” and “b“.
So for this example to select input B to the output at Q, the binary input address would
need to be “a” = logic “1” and “b” = logic “0”. Thus we can show the selection of the data
through the multiplexer as a function of the data select bits as shown.
Multiplexer Input Line Selection
Adding more control address lines, (n) will allow the multiplexer to control more inputs as it
can switch 2n inputs but each control line configuration will connect only ONE input to the
output.
Then the implementation of the Boolean expression above using individual logic gates
would require the use of seven individual gates consisting of AND, OR and NOT gates as
shown.
4 Channel Multiplexer using Logic Gates
The symbol used in logic diagrams to identify a multiplexer is as follows:
Multiplexer Symbol
Multiplexers are not limited to just switching a number of different input lines or channels
to one common single output. There are also types that can switch their inputs to multiple
outputs and have arrangements or 4-to-2, 8-to-3 or even 16-to-4 etc configurations and an
example of a simple Dual channel 4 input multiplexer (4-to-2) is given below:
4-to-2 Channel Multiplexer
Here in this example the 4 input channels are switched to 2 individual output lines but
larger arrangements are also possible. This simple 4-to-2 configuration could be used for
example, to switch audio signals for stereo pre-amplifiers or mixers.
Adjustable Amplifier Gain

As well as sending parallel data in a serial format down a single transmission line or
connection, another possible use of multi-channel multiplexers is in digital audio
applications as mixers or where the gain of an analogue amplifier can be controlled
digitally, for example.
Digitally Adjustable Amplifier Gain
Here, the voltage gain of the inverting operational amplifier is dependent upon the ratio
between the input resistor, RIN and its feedback resistor, Rƒ as determined in the Op-amp
tutorials.
A single 4-channel (Quad) SPST switch configured as a 4-to-1 channel multiplexer is
connected in series with the resistors to select any feedback resistor to vary the value
of Rƒ. The combination of these resistors will determine the overall voltage gain of the
amplifier, (Av). Then the voltage gain of the amplifier can be adjusted digitally by simply
selecting the appropriate resistor combination.
Digital multiplexers are sometimes also referred to as “Data Selectors” as they select the
data to be sent to the output line and are commonly used in communications or high
speed network switching circuits such as LAN´s and Ethernet applications.
Some multiplexer IC´s have a single inverting buffer (NOT Gate) connected to the output
to give a positive logic output (logic “1”, HIGH) on one terminal and a complimentary
negative logic output (logic “0”, LOW) on another different terminal.
It is possible to make simple multiplexer circuits from standard AND and OR gates as we
have seen above, but commonly multiplexers/data selectors are available as standard i.c.
packages such as the common TTL 74LS151 8-input to 1 line multiplexer or the TTL
74LS153 Dual 4-input to 1 line multiplexer. Multiplexer circuits with much higher number of
inputs can be obtained by cascading together two or more smaller devices.
Multiplexer Summary
Then we can see that Multiplexers are switching circuits that just switch or route signals
through themselves, and being a combinational circuit they are memoryless as there is no
signal feedback path. The multiplexer is a very useful electronic circuit that has uses in
many different applications such as signal routing, data communications and data bus
control applications.
When used with a demultiplexer, parallel data can be transmitted in serial form via a single
data link such as a fibre-optic cable or telephone line and converted back into parallel data
once again. The advantage is that only one serial data line is required instead of multiple
parallel data lines. Therefore, multiplexers are sometimes referred to as “data selectors”,
as they select the data to the line.
Multiplexers can also be used to switch either analogue, digital or video signals, with the
switching current in analogue power circuits limited to below 10mA to 20mA per channel in
order to reduce heat dissipation.
In the next tutorial about combinational logic devices, we will look at the reverse of
the Multiplexer called the Demultiplexer which takes a single input line and connects it to
multiple output lines.
Combinational Logic Circuits
Combinational Logic Circuits are memory-less digital logic circuits whose output at any instant in time
depends only on the combination of its inputs
Unlike Sequential Logic Circuits whose outputs are dependant on both their present inputs
and their previous output state giving them some form of Memory. The outputs
of Combinational Logic Circuits are only determined by the logical function of their
current input state, logic “0” or logic “1”, at any given instant in time.
The result is that combinational logic circuits have no feedback, and any changes to the
signals being applied to their inputs will immediately have an effect at the output. In other
words, in a Combinational Logic Circuit, the output is dependant at all times on the
combination of its inputs. Thus a combinational circuit is memoryless.
So if one of its inputs condition changes state, from 0-1 or 1-0, so too will the resulting
output as by default combinational logic circuits have “no memory”, “timing” or “feedback
loops” within their design.
Combinational Logic
Combinational Logic Circuits are made up from basic logic NAND, NOR or NOT gates
that are “combined” or connected together to produce more complicated switching circuits.
These logic gates are the building blocks of combinational logic circuits. An example of a
combinational circuit is a decoder, which converts the binary code data present at its input
into a number of different output lines, one at a time producing an equivalent decimal code
at its output.
Combinational logic circuits can be very simple or very complicated and any combinational
circuit can be implemented with only NAND and NOR gates as these are classed as
“universal” gates.
The three main ways of specifying the function of a combinational logic circuit are:
 1. Boolean Algebra – This forms the algebraic expression showing the operation of
the logic circuit for each input variable either True or False that results in a logic “1”
output.
 2. Truth Table – A truth table defines the function of a logic gate by providing a
concise list that shows all the output states in tabular form for each possible combination
of input variable that the gate could encounter.
 3. Logic Diagram – This is a graphical representation of a logic circuit that shows the
wiring and connections of each individual logic gate, represented by a specific graphical
symbol, that implements the logic circuit.
and all three of these logic circuit representations are shown below.
As combinational logic circuits are made up from individual logic gates only, they can also
be considered as “decision making circuits” and combinational logic is about combining
logic gates together to process two or more signals in order to produce at least one output
signal according to the logical function of each logic gate. Common combinational circuits
made up from individual logic gates that carry out a desired application
includeMultiplexers, De-multiplexers, Encoders, Decoders, Full and Half Adders etc.
Classification of Combinational Logic
One of the most common uses of combinational logic is in Multiplexer and De-multiplexer
type circuits. Here, multiple inputs or outputs are connected to a common signal line and
logic gates are used to decode an address to select a single data input or output switch.
A multiplexer consist of two separate components, a logic decoder and some solid state
switches, but before we can discuss multiplexers, decoders and de-multiplexers in more
detail we first need to understand how these devices use these “solid state switches” in
their design.
Solid State Switches
Standard TTL logic devices made up from Transistors can only pass signal currents in one
direction only making them “uni-directional” devices and poor imitations of conventional
electro-mechanical switches or relays. However, some CMOS switching devices made up
from FET’s act as near perfect “bi-directional” switches making them ideal for use as solid
state switches.
Solid state switches come in a variety of different types and ratings, and there are many
different applications for using solid state switches. They can basically be sub-divided into
3 different main groups for switching applications and in this combinational logic section
we will only look at the Analogue type of switch but the principal is the same for all types
including digital.
Solid State Switch Applications

 Analogue Switches – Used in Data Switching and Communications, Video and Audio
Signal Switching, Instrumentation and Process Control Circuits …etc.
 Digital Switches – High Speed Data Transmission, Switching and Signal Routing,
Ethernet, LAN’s, USB and Serial Transmissions …etc.
 Power Switches – Power Supplies and General “Standby Power” Switching Applications,
Switching of Larger Voltages and Currents …etc.
Analogue Bilateral Switches

Analogue or “Analog” switches are those types that are used to switch data or signal
currents when they are in their “ON” state and block them when they are in their “OFF”
state. The rapid switching between the “ON” and the “OFF” state is usually controlled by a
digital signal applied to the control gate of the switch. An ideal analogue switch has zero
resistance when “ON” (or closed), and infinite resistance when “OFF” (or open) and
switches with RON values of less than 1Ω are commonly available.
Solid State Analogue Switch
By connecting an N-channel MOSFET in parallel with a P-channel MOSFET allows

signals to pass in either direction making it a “Bi-directional” switch and as to whether the
N-channel or the P-channel device carries more signal current will depend upon the ratio
between the input to the output voltage. The two MOSFET’s are switched “ON” or “OFF”
by two internal non-inverting and inverting amplifiers.
Contact Types
Just like mechanical switches, analogue switches come in a variety of forms or contact
types, depending on the number of “poles” and “throws” they offer. Thus, terms such as
“SPST” (single-pole single throw) and “SPDT” (single-pole double-throw) also apply to
solid state analogue switches with “make-before-break” and “break-before-make”
configurations available.
Analogue Switch Types
Individual analogue switches can be grouped together into standard IC packages to form
devices with multiple switching configurations of SPST (single-pole single-throw) and
SPDT (single-pole double-throw) as well as multi channel multiplexers.
The most common and simplest analogue switch in a single IC package is the 74HC4066
which has 4 independent bi-directional “ON/OFF” Switches within a single package but the
most widely used variants of the CMOS analogue switch are those described as “Multi-
way Bilateral Switches” otherwise known as the “Multiplexer” and “De-multiplexer” IC´s
and these are discussed in the next tutorial.
Combinational Logic Summary

Then to summarise, Combinational Logic Circuits consist of inputs, two or more basic
logic gates and outputs. The logic gates are combined in such a way that the output state
depends entirely on the input states. Combinational logic circuits have “no memory”,
“timing” or “feedback loops”, there operation is instantaneous. A combinational logic circuit
performs an operation assigned logically by a Boolean expression or truth table.
Examples of common combinational logic circuits include: half adders, full adders,
multiplexers, demultiplexers, encoders and decoders all of which we will look at in the next
few tutorials.
Digital Comparator
The Digital Comparator is another very useful combinational logic circuit used to compare the value of
two binary digits
Digital or Binary Comparators are made up from standard AND, NOR and NOT gates that
compare the digital signals present at their input terminals and produce an output
depending upon the condition of those inputs.
For example, along with being able to add and subtract binary numbers we need to be
able to compare them and determine whether the value of input A is greater than, smaller
than or equal to the value at input B etc. The digital comparator accomplishes this using
several logic gates that operate on the principles of Boolean Algebra. There are two main
types of Digital Comparator available and these are.
 1. Identity Comparator – an Identity Comparator is a digital comparator with only one
output terminal for when A = B, either A = B = 1 (HIGH) or A = B = 0 (LOW)
 2. Magnitude Comparator – a Magnitude Comparator is a digital comparator which has
three output terminals, one each for equality, A = B greater than, A > B and less
than A < B
The purpose of a Digital Comparator is to compare a set of variables or unknown
numbers, for example A (A1, A2, A3, …. An, etc) against that of a constant or unknown
value such as B (B1, B2, B3, …. Bn, etc) and produce an output condition or flag
depending upon the result of the comparison. For example, a magnitude comparator of
two 1-bits, (Aand B) inputs would produce the following three output conditions when
compared to each other.
Which means: A is greater than B, A is equal to B, or A is less than B

This is useful if we want to compare two variables and want to produce an output when
any of the above three conditions are achieved. For example, produce an output from a
counter when a certain count number is reached. Consider the simple 1-bit comparator
below.
1-bit Digital Comparator Circuit
Then the operation of a 1-bit digital comparator is given in the following Truth Table.
Digital Comparator Truth Table

Inputs Outputs
B A A>B A=B A<B
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0
You may notice two distinct features about the comparator from the above truth table.
Firstly, the circuit does not distinguish between either two “0” or two “1”‘s as an output A =
B is produced when they are both equal, either A = B = “0” or A = B = “1”. Secondly, the
output condition for A = B resembles that of a commonly available logic gate,
the Exclusive-NOR or Ex-NOR function (equivalence) on each of the n-
bits giving: Q = A ⊕ B
Digital comparators actually use Exclusive-NOR gates within their design for comparing
their respective pairs of bits. When we are comparing two binary or BCD values or
variables against each other, we are comparing the “magnitude” of these values, a logic
“0” against a logic “1” which is where the term Magnitude Comparator comes from.
As well as comparing individual bits, we can design larger bit comparators by cascading
together n of these and produce a n-bit comparator just as we did for the n-bit adder in the
previous tutorial. Multi-bit comparators can be constructed to compare whole binary or
BCD words to produce an output if one word is larger, equal to or less than the other.
A very good example of this is the 4-bit Magnitude Comparator. Here, two 4-bit words
(“nibbles”) are compared to each other to produce the relevant output with one word
connected to inputs A and the other to be compared against connected to input B as
shown below.
4-bit Magnitude Comparator
Some commercially available digital comparators such as the TTL 74LS85 or CMOS 4063
4-bit magnitude comparator have additional input terminals that allow more individual
comparators to be “cascaded” together to compare words larger than 4-bits with
magnitude comparators of “n”-bits being produced. These cascading inputs are connected
directly to the corresponding outputs of the previous comparator as shown to compare 8,
16 or even 32-bit words.
8-bit Word Comparator
When comparing large binary or BCD numbers like the example above, to save time the
comparator starts by comparing the highest-order bit (MSB) first. If equality exists, A = B
then it compares the next lowest bit and so on until it reaches the lowest-order bit, (LSB).
If equality still exists then the two numbers are defined as being equal.
If inequality is found, either A > B or A < B the relationship between the two numbers is
determined and the comparison between any additional lower order bits stops. Digital
Comparator are used widely in Analogue-to-Digital converters, (ADC) and Arithmetic
Logic Units, (ALU) to perform a variety of arithmetic operations.
Binary Subtractor
https://www.electronics-tutorials.ws/combination/binary-subtractor.html
The Binary Subtractor is another type of combinational arithmetic circuit that produces an output
which is the subtraction of two binary numbers
As their name implies, a Binary Subtractor is a decision making circuit that subtracts two
binary numbers from each other, for example, X – Y to find the resulting difference
between the two numbers.
Unlike the Binary Adder which produces a SUM and a CARRY bit when two binary
numbers are added together, the binary subtractor produces a DIFFERENCE, D by using
a BORROW bit, B from the previous column. Then obviously, the operation of subtraction
is the opposite to that of addition.
We learnt from our math lessons at school that the minus sign, “–” is used for a
subtraction calculation, and when one number is subtracted from another, a borrow is
required if the subtrahend is greater than the minuend. Consider the simple subtraction of
the two denary (base 10) numbers below.
We can not directly subtract 8 from 3 in the first column as 8 is greater than 3, so we have
to borrow a 10, the base number, from the next column and add it to the minuend to
produce 13 minus 8. This “borrowed” 10 is then return back to the subtrahend of the next
column once the difference is found. Simple school math’s, borrow a 10 if needed, find the
difference and return the borrow.
The subtraction of one binary number from another is exactly the same idea as that for
subtracting two decimal numbers but as the binary number system is a Base-2 numbering
system which uses “0” and “1” as its two independent digits, large binary numbers which
are to be subtracted from each other are therefore represented in terms of “0’s” and “1’s”.
Binary Subtraction
Binary Subtraction can take many forms but the rules for subtraction are the same
whichever process you use. As binary notation only has two digits, subtracting a “0” from a
“0” or a “1” leaves the result unchanged as 0-0 = 0 and 1-0 = 1. Subtracting a “1” from a
“1” results in a “0”, but subtracting a “1” from a “0” requires a borrow. In other
words 0 – 1requires a borrow.
Binary Subtraction of Two Bits
For the simple 1-bit subtraction problem above, if the borrow bit is ignored the result of
their binary subtraction resembles that of an Exclusive-OR Gate. To prevent any
confusion in this tutorial between a binary subtractor input labelled, B and the resulting
borrow bit output from the binary subtractor also being labelled, B, we will label the two
input bits as X for the minuend and Y for the subtrahend. Then the resulting truth table is
the difference between the two input bits of a single binary subtractor is given as:
2-input Exclusive-OR Gate
Symbol Truth Table
Y X Q
0 0 0
0 1 1
2-input Ex-OR Gate 1 0 1
1 1 0
As with the Binary Adder, the difference between the two digits is only a “1” when these
two inputs are not equal as given by the Ex-OR expression. However, we need an
additional output to produce the borrow bit when input X = 0 and Y = 1. Unfortunately
there are no standard logic gates that will produce an output for this particular combination
of X and Y inputs.
But we know that an AND Gate produces an output “1” when both of its inputs X and Yare
“1” (HIGH) so if we use an inverter or NOT Gate to complement the input X before it is fed
to the AND gate, we can produce the required borrow output when X = 0 and Y = 1 as
shown below.
Then by combining the Exclusive-OR gate with the NOT-AND combination results in a
simple digital binary subtractor circuit known commonly as the Half Subtractor as shown.
A Half Subtractor Circuit
A half subtractor is a logical circuit that performs a subtraction operation on two binary
digits. The half subtractor produces a sum and a borrow bit for the next stage.
Half Subtractor with Borrow-out
Symbol Truth Table
Y X DIFFERENCE BORROW
0 0 0 0
0 1 1 0
1 0 1 1
1 1 0 0
From the truth table of the half subtractor we can see that the DIFFERENCE (D) output is
the result of the Exclusive-OR gate and the Borrow-out (Bout) is the result of the NOT-
AND combination. Then the Boolean expression for a half subtractor is as follows.
For the DIFFERENCE bit:
For the BORROW bit
If we compare the Boolean expressions of the half subtractor with a half adder, we can
see that the two expressions for the SUM (adder) and DIFFERENCE (subtractor) are
exactly the same and so they should be because of the Exclusive-OR gate function. The
two Boolean expressions for the binary subtractor BORROW is also very similar to that for
the adders CARRY. Then all that is needed to convert a half adder to a half subtractor is
the inversion of the minuend input X.
One major disadvantage of the Half Subtractor circuit when used as a binary subtractor, is
that there is no provision for a “Borrow-in” from the previous circuit when subtracting
multiple data bits from each other. Then we need to produce what is called a “full binary
subtractor” circuit to take into account this borrow-in input from a previous circuit.
A Full Binary Subtractor Circuit

The main difference between the Full Subtractor and the previous Half
Subtractor circuit is that a full subtractor has three inputs. The two single bit data
inputs X (minuend) and Y(subtrahend) the same as before plus an additional Borrow-
in (B-in) input to receive the borrow generated by the subtraction process from a previous
stage as shown below.
Full Subtractor Block Diagram
Then the combinational circuit of a “full subtractor” performs the operation of subtraction
on three binary bits producing outputs for the difference D and borrow B-out. Just like the
binary adder circuit, the full subtractor can also be thought of as two half subtractors
connected together, with the first half subtractor passing its borrow to the second half
subtractor as follows.
Full Subtractor Logic Diagram
As the full subtractor circuit above represents two half subtractors cascaded together, the
truth table for the full subtractor will have eight different input combinations as there are
three input variables, the data bits and the Borrow-in, BIN input. Also includes the
difference output, D and the Borrow-out, BOUT bit.
Full Subtractor Truth Table
Symbol Truth Table
B-in Y X Diff. B-out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 1
0 1 1 0 0
1 0 0 1 1
1 0 1 0 0
1 1 0 0 1
1 1 1 1 1
Then the Boolean expression for a full subtractor is as follows.

For the DIFFERENCE (D) bit:
which can be simplified too:
For the BORROW OUT (BOUT) bit:
which will also simplify too:
An n-bit Binary Subtractor

As with the binary adder, we can also have n number of 1-bit full binary subtractor
connected or “cascaded” together to subtract two parallel n-bit numbers from each other.
For example two 4-bit binary numbers. We said before that the only difference between a
full adder and a full subtractor was the inversion of one of the inputs.
So by using an n-bit adder and n number of inverters (NOT Gates), the process of
subtraction becomes an addition as we can use two’s complement notation on all the bits
in the subtrahend and setting the carry input of the least significant bit to a logic “1”
(HIGH).
Binary Subtractor using 2’s Complement
Then we can use a 4-bit full-adder ICs such as the 74LS283 and CD4008 to perform
subtraction simply by using two’s complement on the subtrahend, B inputs as X – Y is the
same as saying, X + (-Y) which equals X plus the two’s complement of Y.
If we wanted to use the 4-bit adder for addition once again, all we would need to do is set
the carry-in (CIN) input LOW at logic “0”. Because we can use the 4-bit adder IC such as
the 74LS83 or 74LS283 as a full-adder or a full-subtractor they are available as a single
adder/subtractor circuit with a single control input for selecting between the two
operations.
Bus Transceiver
https://www.electronics-tutorials.ws/combination/bus-transceiver.html
A transceiver uses back-to-back tri-state buffers to connect different devices to a common

communications bus sharing data in both directions
A Transceiver can be used to provide bidirectional, input or output control, of either digital
or analogue devices to a common shared data bus. Unlike the buffer, transceivers are
bidirectional devices which allow data to flow through them in either direction.
Thus their name “transceiver” is a portmanteau word coming from the amalgamation of
the two words trans-mitter and re-ceive (transmitter/receiver). Transceivers are also
known by the names of: send/receive or driver/receiver devices.
In the Digital Buffer Tutorial, we saw that a buffer performs no inversion or decision
making capabilities, unlike digital logic gates with two or more inputs, but instead produces
an output condition which matches exactly that of its input. Thus a buffer is a “non-
inverting” device producing the Boolean expression of: Q = A.
Digital Buffer
A Digital Buffer like the one shown on the left, is a unidirectional device, that is the signal
passes through them in one direction only, from input “A” to the output at “Q“.
Thus, when input A is at logic “1”, output Q is at logic “1”, and when input A is at logic “0”,
output Q is at logic “0” for a positive logic device such as the CMOS 74HC4050 Hex Buffer
Gate.
Buffers can be used to isolate other gates or circuit stages from each other preventing the
impedance or operation of one circuit from affecting the impedance or operation of
another. Also on their own, buffers can be used as drivers for high current loads such as
transistor switches because their output drive capability (fan-out) is generally much higher
than their input signal requirements. For example, the TTL 74LS07 Hex buffer/driver with
open collector, high-voltage (30 volts) outputs.
TTL 74LS07 Digital Buffer
The digital non-inverting buffer function can also be made using spare logic AND, or
logic OR gates or by using pairs of NOT gates (inverters) as shown.
Equivalent Buffer Designs
One of the disadvantages of a single input digital buffer is that the output at Q will always
be at the same logic level as the input possibly affecting whatever circuit or device is
connected to the buffers output terminal. One way to overcome this is to turn the basic
buffer into a 3-State Buffer, more commonly known as a Tri-state Buffer.
The “Tri-state Buffer”

A Tri-state Buffer is another type of buffer circuit which can be used to control the passage
of a logic signal from its input to its output. The tri-state buffer is a combinational device
whose output can be electronically turned “ON” or “OFF” by means of an external
“Control” or “Enable” (EN) signal input allowing them to be used in bus-orientated
systems.
As their name implies, the output at “Q” for a Tri-state Buffer can take on one of three
possible states, logic “0”, logic “1”, and High-Z (high impedance), that is, an open circuit,
rather than the standard “0” and “1” states.
The buffers enable or control signal can be either a logic “0” or a logic “1” level signal with
the output being inverting and non-inverting as the digital signal passes through it. The
two most commonly used tri-state buffer IC’s being the TTL 74LS125 and the TTL
74LS126.
Thus a tri-state buffer requires two inputs. One being the data input (A) and the other
being the control or Enable input (EN) as shown.
Tri-state Buffer Switch Equivalent
The tri-state buffer’s symbol is very similar to the standard buffer symbol above but with
the addition of a second input representing the enable/disable control function. When the
enable (EN) input is at a logic level “1” (for positive logic), it acts as a normal buffer
allowing the input signal, A to pass directly to the output at Q. Whether it is a logic “0” or a
logic “1”.
When the enable input is at logic “0”, the tristate buffer is activated into its third state and
disables or turns “OFF” its output producing an open circuit condition. This third condition
is neither at a logic “1” (high) or logic “0” (low), but instead gives an output state that is at a
very high impedance, High-Z, more commonly written as: Hi-Z.
Thus a tri-state buffer has two logic state inputs, “0” or a “1” but can produce three
different output states, “0”, “1” or “Hi-Z” which is why it is called a “Tri” or “3-state” device.
Note that this third state is NOT equal to a logic level “0” or a “1”, but is an high impedance
state as its output is electrically disconnected.
Then we can correctly state for a positively enabled tri-state buffer that:
 If the enable signal is HIGH, logic “1”, the input signal of the buffer gate is passed
directly to its output.
 If the enable signal is LOW, logic “0”, the output of the buffer gate acts like an open
circuit, that is, high impedance, (Hi-Z).
and we can present the truth table for a tri-state buffer as:
Active “HIGH” Tri-state Buffer
Symbol Truth Table
Enable IN OUT
0 0 Hi-Z
0 1 Hi-Z
1 0 0
Tri-state Buffer
1 1 1
Tri-state Buffers are available in integrated form as quad, hex or octal buffer/drivers such
as the TTL 74LS244 as shown.
74LS244 Octal Tri-state Buffer
Notice that the eight buffers are configured into two groups of four with the first group
(A1 to A4) being controlled by enable input, CA, and the second group (A5 to A8) being
controlled by the enable input, CB. The 74LS244 has very high sink and source current
capabilities if required to switch transistor loads.
Tri-state Buffer Control

So what can we use a 3-state or tri-state buffer for. Tri-state buffers can allow multiple
devices to share a common output wire or bus by having only one tri-state device drive the
wire bus at any one time while all other buffers remain in their Hi-Z state. Consider the
circuit below.
Multiple tri-state buffers on a single Bus
The outputs from each tri-state buffer are connected to a common wire bus but their
enable inputs are connected to a binary decoder. The decoder guarantees that only one
tri-state buffer will be active at any one time, due to its enable signal. This allows the data
of the active buffer to pass directly onto the common bus while the outputs of the other
non-enabled buffers are effectively disconnected and in their high-impedance state. Thus
which buffer is connected to the common line will depending on the binary value of the
decoders select inputs.
Therefore, no more than one tri-state buffer can be in an “active state” at any given time.
You may have noticed that the possible combination of different data inputs connected to
a single output line above resembles that of a 4-to-1 line multiplexer, and you would be
right, multiplexer circuits can be easily constructed using tri-state buffers.
Any tri-state buffer element can easily be converted into a normal digital buffer by simply
connecting their enable (EN) input directly to +Vcc or ground, depending on the tri-state
buffer used. Thus, the output is permanently enabled so any input signal present at “A” will
pass straight through the buffer to the output at “Q“.
We have seen thus far, that we can use tri-state buffers to send information in a uni-
directional way onto a common wire or bus. But how could we use them to send data in
both directions, that is, to send data too and receive data from a common wire bus.
Bi-directional Buffer Control

It is also possible to connect Tri-state Buffers “back-to-back” (inverse parallel) to produce
what is called a Bi-directional Buffer or transceiver circuit. By using an additional
inverter, one tri-state buffer is as an “active-high buffer”, while the other operates as an
“active-low buffer”, as shown.
Multiple tri-state buffers on a single Bus
Here, the two tri-state buffers are connected in parallel but in reverse from “A” to “B” with
the enable control input, EN acting more like a directional control signal thus allowing data
to be both read “from” and transmitted “to” the same data terminal.
So in this simple example, when the enable input is HIGH, (EN equals logic “1”) data is
allowed to pass from A to B via buffer 1, and when the enable input is LOW,
(EN equals logic “0”) data passes from B to A via buffer 2.
Thus the enable input “EN” acts as direction control allowing data to flow in either direction
depending upon the logic status of this control input. In this type of application a tri-state
buffer with bi-directional switching capability such as the TTL 74LS245 or the inverting
CMOS 74ALS620 can be used producing what is called a Bus Transceiver.
Bus Transceivers
Bus transceivers are tri-state bi-directional devices which allow the flow of data between
two points making them compatible with bus-oriented systems or the bi-directional (input
or output) control of interface circuitry. Bus transceivers can be inverting, the TTL
74LS242 or non-inverting, the TTL 74LS243 devices.
Thus we can use an 8-line octal transceiver to interface any input/output device to an 8-bit
data bus with the most common bus transceiver IC being used to both send and receive
data is the TTL 74LS245 given below.
74LS245 Bus Transceiver
The TTL 74LS245 is an octal bus transceiver (Transmitter/Receiver) designed for

asynchronous two-way communication between two data buses or input/output device.
The transceiver allows for the transmission of data from the terminals A to terminals B or
the reverse depending on the logic level at the direction-control (DIR) input, (pin 1).
So for example, if the direction-control input is HIGH at logic level “1”, then data will pass
from terminals A to terminals B. If the direction-control input is LOW at logic level “0”, then
data will pass in the reverse direction from terminals B to terminals A. When held HIGH at
logic level “1”, the output chip-enable (CE) input, (pin 19) can be used to disable the
device so that the terminals, and therefore any connected data buses are effectively
isolated from each other.
Transmission Gate
https://www.electronics-tutorials.ws/combination/transmission-gate.html
The transmission gate is a bilateral switch consisting of NMOS and PMOS transistors controlled by
externally applied logic levels
The analogue switch is a solid-state semiconductor switch that controls the transmission
path of analogue signals. The open and closed operations of the switch positions are
usually controlled by some digital logic network, with standard analogue switches
available in many styles and configurations. For example, single or dual normally open
(NO) or normally closed (NC), single-pole single-throw (SPST), single-pole, double-throw
(SPDT) configurations etc, in much the same way as for conventional electromechanical
relays and contacts.
The switching and routing of digital and analogue signals (both voltage and current) can
easily be done using mechanical relays and their contacts, but these can be slow and
costly. The obvious choice is to use much faster acting solid state electronic switches
which use metal oxide semiconductor (MOS) analogue gates to route the signal currents
from their input to their output, with the well-known CMOS 4016B bilateral switch being the
most common example.
MOS technology uses both NMOS and PMOS devices to perform the logical switching
functions, thus allowing a digital computer or logic circuit to control the operation of these
analogue switches. CMOS devices where both NMOS and PMOS transistors are
fabricated into the same gate circuit, can pass (closed-condition) or block (open-condition)
an analogue or digital signal, depending on the digital logic level that controls it.
The type of solid-state switch which allows for a signal or data transfer in both directions is
called a Transmission Gate, or TG. But first lets consider the operation of a Field Effect
Transistor, or FET as a basic analogue switch.
The MOSFET as an Analogue Switch

Both Bipolar Junction Transistors (BJTs) and Field Effect Transistors (FETs) can be used
as a single-pole electronic switch in a wide variety of different applications. The main
advantages of MOSFET, or metal-oxide-semiconductor FET, technology over bipolar
devices is that its gate terminal is insulated from the main conducting channel by a thin
layer of metal oxide, and the main MOSFET channel used for switching is purely resistive.
Consider the basic N-channel and P-channel enhancement MOSFET (eMOSFET)
configurations below.
The MOSFET as a Switch
Then we can see that for the n-channel (NMOS) and p-channel (PMOS) enhancement
MOSFET to operate as an open (OFF) or closed (ON) device the following conditions
must be true:
 An N-channel MOSFET behaves like an closed switch when the gate-source voltage,
VGS is greater than the threshold voltage, VT. That is VGS > VT
 An N-channel MOSFET behaves like an open switch when the gate-source voltage,
VGSis less than the threshold voltage, VT. That is VGS < VT
 A P-channel MOSFET behaves like an closed switch when the gate-drain voltage, VGDis
less than the threshold voltage, VT. That is VGD < VT
 A P-channel MOSFET behaves like an open switch when the gate-drain voltage, VGD is
greater than the threshold voltage, VT. That is VGD > VT
Note that a MOSFETs Threshold Voltage, VT is the minimum voltage applied to the gate
terminal for the main channel between the drain and source terminals to start conducting.
Also, since the eMOSFET is used mainly as a switching device, it generally operates
between its cut-off and saturation regions thus VGS acts as an ON/OFF control voltage for
the MOSFET.
The Ideal Switch
An ideal analogue switch would create a short-circuit condition when closed and an open-
circuit condition when open, in a similar fashion to a mechanical switch.
However, solid-state analogue switches are not ideal as there is always some loss
associated with the conducting channel due to its resistive value when ON.
We would like to think that if we applied a signal to its input pin this would result in the
signal being identical and without loss at the output pin, and vice versa. However, while
CMOS switches do make excellent transmission gates, their “ON” state resistance, R ON
can be several ohms creating an I2*R power loss, while their “OFF” state resistance can
be several thousand ohms allowing pico amperes of current to still flow through the
channel.
Nevertheless, the ability of complementary metal-oxide semiconductor FETs to perform as
analogue switches and transmission gates remains high, and MOSFET devices, in
particular the enhancement MOSFET which requires a voltage to be applied to the gate to
turn it “ON” and zero voltage to turn it “OFF” are the most commonly used switching
transistor.
The NMOS Switch

The N-channel metal-oxide semiconductor (NMOS) transistor can be used as a
transmission gate for the passing of analogue signals. Assuming that the drain and source
terminals are identical, the input is connected to the Drain terminal and the control signal
to the gate terminal as shown.
NMOS FET as an Analogue Switch
When the control voltage, VC on the gate is zero (LOW), the gate terminal will not be
positive with respect to either input terminal (drain) or the output terminal (source), thus
the transistor is in its cut-off region and the input and output terminals are isolated from
each. Then the NMOS is acting an open switch so any voltage at the input will not be
passed to the output.
When there is a positive control voltage +VC at the gate terminal, the transistor is turned
“ON” and in its saturation region acting as a closed switch. If the input voltage, VIN is
positive and greater than VC current will flow from the drain terminal to the source terminal,
thus connecting VOUT to VIN.
If however VIN becomes zero (LOW) while the gates control voltage is still positive, the
transistor channel is still open but the drain-to-source voltage, VDS is zero, so no drain
current flows through the channel and thus the output voltage is zero.
Therefore, as long as the gate control voltage, VC is HIGH, the NMOS transistor passes
the input voltage to the output. If it is LOW, the NMOS transistor is turned “OFF”, and the
output terminal is disconnected from the input. Thus, the control voltage, VC at the gate
determines whether the transistor is an “open” or “closed” as a switch.
One issue here with the NMOS switch is that the gate-to-source voltage, VGS must be
significantly greater than the channel threshold voltage to turn it fully-ON or there will be a
voltage reduction through the channel. Thus the NMOS device can only transmit a “weak”
logic “1” (HIGH) level but a strong logic “0” (LOW) without loss.
The PMOS Switch

The P-channel metal-oxide semiconductor (PMOS) transistor is similar but opposite in
polarity to the previous NMOS device with current flowing in the opposite direction, from
source to drain. Then for a PMOS device, the input is connected to the Source terminal
and the control signal to the gate terminal as shown.
PMOS FET as a Switch
For the PMOS FET, when the control voltage, VC on the gate is zero and is thus more
negative with respect to either input terminal (source) or the output terminal (drain), the
transistor is “ON” and in its saturation region acting as a closed switch. If the input voltage,
VIN is positive and greater than VC current will flow from the source terminal to the drain
terminal, that is ID flows out of the drain thus connecting VIN to VOUT.
If the input voltage, VIN becomes zero (LOW) while the gates control voltage is still zero or
negative, the PMOS channel is still open but the source-to-drain voltage, VSD is zero, so no
current flows through the channel and thus the voltage at the output (drain) is zero.
When there is a positive control voltage +VC at the gate terminal, the channel of the PMOS
transistor is turned “OFF” and in its cut-off region acting as a open switch. Thus no drain
current, ID flows through the conducting channel.
Therefore, as long as the gate control voltage, VC is LOW (or negative), the PMOS
transistor will pass the input voltage to the output. If it is HIGH, the PMOS transistor is
turned “OFF”, and the output terminal is disconnected from the input. Thus as with the
previous NMOS device, the control voltage, VC at the gate determines whether the
transistor is an “open” or “closed” as a switch.
The problem with the PMOS switch is that the gate-to-source voltage, VGS must be
significantly less than the channel threshold voltage to turn it fully-OFF or current will still
flow through the channel. Thus the PMOS device can transmit a “strong” logic “1” (HIGH)
level without loss but a weak logic “0” (LOW).
So we can see that for an NMOS device a positive gate-to-source voltage causes current
to flow in one direction from Drain-to-Source, while for the PMOS device, a negative gate-
to-source voltage will result in current flowing in the reverse direction from Source-to-
Drain.
However, the NMOS device only passes a strong “0” but a weak “1”, while the PMOS
device passes a strong “1” but a weak “0”. Thus by combining the characteristics of the
NMOS and the PMOS devices, it is possible to transmit both a strong logic “0” or a strong
logic “1” value in either direction without any degradation. This then forms the basis of
a Transmission Gate.
Transmission Gate
Connecting PMOS and NMOS devices together in parallel we can create a basic bilateral
CMOS switch, known commonly as a “Transmission Gate”. Note that transmission gates
are quite different from conventional CMOS logic gates as the transmission gate is
symmetrical, or bilateral, that is, the input and output are interchangeable. This bilateral
operation is shown in the transmission gate symbol below which shows two superimposed
triangles pointing in opposite directions to indicate the two signal directions.
CMOS Transmission Gate
Two MOS transistors are connected back-to-back in parallel with an inverter used
between the gate of the NMOS and PMOS to provide the two complementary control
voltages. When the input control signal, VC is LOW, both the NMOS and PMOS transistors
are cut-off and the switch is open. When VC is high, both devices are biased into
conduction and the switch is closed.
Thus the transmission gate acts as a “closed” switch when VC = 1, while the gate acts as
an “open” switch when VC = 0 operating as a voltage-controlled switch. The bubble of the
symbol indicating the gate of the PMOS FET.
Transmission Gate Boolean Expression

As with traditional logic gates, we can define the operation of a transmission gate using
both a truth table and boolean expression as follows.
Transmission Gate Truth Table
Symbol Truth Table
Control A B
1 0 0
1 1 1
0 0 Hi-Z
Transmission Gate
0 1 Hi-Z
Boolean Expression B = A.Control Read as A AND Cont. gives B
We can see from the above truth table, that the output at B relies not only the logic level of
the input A, but also on the logic level present on the control input. Thus the logic level
value of B is defined as both A AND Control giving us the boolean expression for a
transmission gate of:
B = A.Control
Since the boolean expression of a transmission gate incorporates the logical AND
function, it is therefore possible to implement this operation using a standard 2-input AND
gate with one input being the data input while the other is the control input as shown.
AND Gate Implementation
One other point to consider about transmission gates, a single NMOS or a single PMOS
on its own can be used as a CMOS switch, but the combination of the two transistors in
parallel has some advantages. An FET channel is resistive so the ON-resistances of both
transistors are effectively connected in parallel.
As a FETs On-resistance is a function of the gate-to-source voltage, VGS, as one transistor
becomes less conducting due to the gate drive, the other transistor takes over and
becomes more conducting. Thus the combined value of the two ON-resistances (as low
as 2 or 3Ω) stays more or less constant than would be the case for a single switching
transistor on its own.
When can demonstrate this in the following diagram.
Transmission Gate ON-resistance
Transmission Gate Summary

We have seen here that connecting a P-channel FET (PMOS) with an N-channel FET
(NMOS) we can create a solid-state switch which is digitally controlled using logic level
voltages and is commonly called a “transmission gate”.
The Transmission Gate, (TG) is a bilateral switch where either of its terminals can be the
input or the output. As well as the input and output terminals, the transmission gate has a
third connection called the control, where the control input determines the switching state
of the gate as an open or closed (NO/NC) switch.
This input is typically driven by a digital logic signal that toggles between ground (0V) and
a set DC voltage, usually VDD. When the control input is low (Control = 0), the switch is
open, and when the control input is HIGH (Control = 1) the switch is closed.
Transmission gates act like voltage-controlled switches, and being switches, CMOS
transmission gates can be used for switching both analogue and digital signals passing
the full range of voltages (from 0V to VDD) in either direction, which as discussed is not
possible with a single MOS device.
The combination of an NMOS and a PMOS transistor together within a single gate means
that the NMOS transistor will transfer a good logic “0” but a poor logic “1”, while the PMOS
transistor transfers a good logic “1” but a poor logic “0”. Therefore, connecting an NMOS
transistor with a PMOS transistor in parallel provides a single bilateral switch which offers
efficient output drive capability for CMOS logic gates controlled by a single input logic
level.

CT 111 Notes - Logic Circuits From References

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CT 111 Notes - Logic Circuits From References

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Binary Adder

Binary Adder Block Diagram

2-input Exclusive-OR Gate

2-input AND Gate

A Half Adder Circuit

Half Adder Truth Table with Carry-Out

A Full Adder Circuit

Full Adder Block Diagram

Full Adder Logic Diagram

C-in B A Sum C-out

Then the Boolean expression for a full adder is as follows.

For the SUM (S) bit:

SUM = (A XOR B) XOR Cin = (A ⊕ B) ⊕ Cin

CARRY-OUT = A AND B OR Cin(A XOR B) = A.B + Cin(A ⊕ B)

An n-bit Binary Adder

74LS83 Logic Symbol

7-Segment Display Format

Truth Table for a 7-segment display

Individual Segments Individual Segments

Binary Coded Decimal

Binary Pattern Binary Pattern

BCD to 7-Segment Display Decoders

Display Decoder Example No1

So for example, an inverter ( NOT-gate ) can be classed as a 1-to-2 binary decoder as 1-

A 2-to-4 Binary Decoders

74LS138 Binary Decoder

A 4-to-16 Binary Decoder Configuration

Memory Address Decoder

Memory Address Decoding

4-to-2 Bit Binary Encoder

8-to-3 Bit Priority Encoder

Digital Inputs Binary Output

Where X equals “dont care”, that is logic “0” or a logic “1”.

Priority Encoder Output Expression

Digital Encoder using Logic Gates

Priority Encoder Navigation

IRQ Number Typical Use Description

IRQ 0 System timer Internal System Timer.

IRQ 1 Keyboard Keyboard Controller.

IRQ 3 COM2 & COM4 Second and Fourth Serial Port.

IRQ 4 COM1 & COM3 First and Third Serial Port.

IRQ 5 Sound Sound Card.

IRQ 6 Floppy disk Floppy Disk Controller.

IRQ 7 Parallel port Parallel Printer.

IRQ 12 Mouse PS/2 Mouse.

IRQ 14 Primary IDE Primary Hard Disk Controller.

IRQ 15 Secondary IDE Secondary Hard Disk Controller.

Digital Encoder Summary

1-to-4 Channel De-multiplexer

4 Channel Demultiplexer using Logic Gates

The symbol used in logic diagrams to identify a demultiplexer is as follows.

The Demultiplexer Symbol

Basic Multiplexing Switch

2-input Multiplexer Design

4-to-1 Channel Multiplexer

Multiplexer Input Line Selection

The symbol used in logic diagrams to identify a multiplexer is as follows:

4-to-2 Channel Multiplexer

Adjustable Amplifier Gain

Classification of Combinational Logic

Solid State Switch Applications

Analogue Bilateral Switches

Solid State Analogue Switch