2019 19th International Symposium on Communications and Information Technologies

(ISCIT)

A 2.4GHz ISM Band Application Low Noise

Amplifier with Active Inductor Load Implemented on
65nm CMOS Process

Allenn C. Lowaton and Elaine Grace O. Tabacon

Microelectronics Laboratory
Electrical Engineering and Technology Department,
Mindanao State University – Iligan Institute of Technology, Iligan City, Philippines
allenn.lowaton@g.msuiit.edu.ph; elainegrace.tabacon@gmail.com

Abstract— This paper presents a Low Noise Amplifier will also apply on using Active Inductor aside from the
operating on 2.4GHz ISM Band Application. An active inductor passive inductors used in common LNA topologies to
is implemented as its tuning load which is designed in study in [9] minimize the chip area of the design and the use of off chip
and the core low noise amplifier circuit is a cascoded common- passive inductors to minimize cost.
source amplifier. To increase gain and matching parameters, two
stages of buffer were used. The amplifier is simulated using
Synopsys Custom Designer with 1.2V supply in 65nm CMOS II. LOW NOISE AMPLIFIER DESIGN ARCHITECTURE
technology process. The design exhibits a gain of 19.5dB, a
minimum noise figure of 3.91dB and return losses S11 of -20.1dB The overall system architecture of this study is composed
and S22 of -32.4dB over the desired frequency of 2.4GHz. of the input matching architecture which also exhibits the first
gain of the LNA, the active load which is configured to tune
Keywords—Low Noise Amplifier, Active Inductor the circuit to its desired operating frequency and the output
matching architecture which also increases the first gain that
I. INTRODUCTION the input matching produces. The system architecture is shown
Development of wireless system has come a long way in Fig. 1 below.
since last century. Many applications, ranging from high-
speed signal processing to target detection using wireless
signals have been enabled [1]-[8], [10]-[11]. In almost any
wireless system, the low-noise amplifier (LNA) is perhaps the
most indispensable component. The LNA is at the front-end
and the primary active amplification block in the receiver’s Fig. 1 Low Noise Amplifier Block Diagram
system. Because of it, LNA’s role is very crucial and that
could affect the RF receiver’s performance. Its first role is to A. Input and Output Matching
avoid the incoming signal from reflecting between the
The proposed input matching uses the cascode architecture
receiver’s systems by matching the LNA’s input with the
which is shown in Fig. 2. The cascode provides isolation
filter’s output. This is why; an input matching architecture is
between the input and output that is ideal for this design. It
needed in the LNA’s system. This work has an input
also provides a single transistor amplifier to maximize the gain
impedance of 50Ω is needed to achieve of the input matching
of the LNA design. This topology can be operate at very high
architecture.
frequencies. By having a low voltage gain, the cascode
Given those architectures and design, the LNA must
transistor can lessen the miller effect on capacitor Cgd1 of the
therefore perform its main function which is to amplify a very
common-source stage. The impedance at the drain of Q1 is
low wanted signal that came from the antenna without adding
quite low 1/gms2 which is impedance from source of Q2. With
noise to maintain the required signal to noise ratio at low and
this approach, stability and the gain of the LNA at higher
higher power levels to the receiver.
frequencies can be obtained. However, the disadvantage of the
This study will discuss the design of a Low Noise
cascode topology is reduced linearity due to stacking two
Amplifier focusing in high gain and high input matching in
transistors which reduces the available voltage swing.
2.4GHz ISM band which fits the receiver standards of IEEE
Moreover, the noise performance using the cascode LNA is
802.15.4 which is the Low-Rate WPAN network technology
poor as compared with a single transistor LNA. The cascode
also known as Zigbee to be simulated in Synopsys Custom
stage contributes more noise to the system.
Designer using 65nm CMOS technology process. This study

978-1-7281-5009-3/19/$31.00 ©2019 IEEE 590

 2019 19th International Symposium on Communications and Information Technologies
(ISCIT)
Fig. 2 Cascode Configuration
The total output matching of this design is composed of the
active inductor and the buffer. This design uses a buffer to
provide the output matching and addition gain of the amplifier
which is shown in Fig. 5.
B. Tuning Load
An active inductor of an achievable physical size is a good
replacement to spiral inductors for its passive equivalent.
Conventional active inductors are usually utilizing high gain
op-amp with a negative feedback. However, it is not suitable
for higher frequency operations. Alternatively, active inductor
can be implemented by using the inherent parasitics of the
transistor to obtain the needed poles and zeroes but linearity
and noise performance will be poor.
This active inductor configuration produces a high quality
factor which is essential in the linearity and minimizes the
noise of the active inductor. For this design, it is required for
the active inductor to have high quality factor (Q) for low
band matching. The active inductor for this LNA design uses
the architecture in [20] which is based on the gyrator-C
approach. It has MOS transistors in common source design for
both transconductance stages. The circuit contains a minimum
number of transistors, quite good for low voltage operations.
It also offers a wide inductive band, high quality factor and
low power dissipation. The active inductor proposed was
implemented in study [20] which is depicted in Fig. 3 with its
equivalent passive model shown in Fig. 4.
Fig. 3 Schematic of High-Q Active Inductor
591
Fig. 4 (a) Gyrator-C realization of active inductor (b) Equivalent passive
model
Shown below is the input impedance function Zi that has
two poles and a zero. Small signal analyses yield the
following:
(1)
(2)
(3)
(4)
(5)
(6)
As shown in Figure 3, M1 provides the negative
transconductance; M2 -M4 forms part of the positive
transconductance. The current mirror M3 and M4 inverts the
negative transconductance of M2. M5 and M6, forms a current
mirror is used for biasing.
From Eqn.(4), C2 and transconductance,G2 can be used to
vary the inductance (L) and its series resistances (Rs),
respectively. Ignoring the effect of output capacitance of M1,
a simplified C2 could be written as C2 = C + Ci2. Clearly,
capacitor C can be used for inductance tuning and Ci2 can be
minimized. Capacitor C helps to maintain the circuit stability.
To improve the stability of the system, a new dominant pole
should be inserted in between of the two poles. The attainable
value of the inductance range depends on the minimum value
of C1 which is being described by C1 = Ci1 + Co2 for a
constant value of L. By using an input transistor of a minimum
size this is achievable.
III. OVERALL LNA ARCHITECTURE
Figure 5 shows the overall architecture of the proposed LNA.
A cascade stage has been shown together with an inductor
load and buffers. The first buffer (M3, IB1) provides a local
parallel feedback (R3, C2). With this, the input impedance is
primarily dictated by the feedback resistor RF and the bias
current IB1, and can be adjusted by the capacitor C2.
 2019 19th International Symposium on Communications and Information Technologies
(ISCIT)

Moreover, this buffer serves as the bias for M1 of the cascode

stage.
The second buffer (M4, IB2) is utilized for the output
signal. Making an adjustment for IB2, a wideband matching
for the output can be achieved. Also, this buffer improves the
gain of the overall loaded LNA.
Fig. 5 Proposed LNA Schematic
The gain of the first stage of the LNA is given by,
V. DESIGN SPECIFICATIONS SUMMARY &
COMPARISON
A collective summary of the data obtained throughout all
simulations is shown in Table 1. In the post simulation
process, the one that suffers from the layout design are the
Noise Figure and Matching parameters. These parameters are
sensitive to process variation due to parasitic extractions that
adds up unwanted resistance, capacitance or inductance in the
design.
It is mentioned that the input matching or S11 of this
architecture is mostly defined by the feedback resistor and
capacitor while the output matching impedance or S22 is
defined mostly by the output buffer M4 and IB2 and the load
which is shown in Figure 3.6. With this, a change in the total
capacitance or resistance of the input and output impedance
can greatly affect the matching of the LNA design. The use of
a high Q load for matching purposes provides an optimal noise
figure and gain performance because of the minimal loss but
to the expense that these type of networks is often quite
sensitive to variations in process, voltage, temperature and
component value [22].

TABLE I. DATA SUMMARY

Where, Req and Leq is the equivalent resistance and LNA’s Pre- Post-
inductance of the active inductor. Parameter Simulation Simulation %
IV. SIMULATION RESULTS AND DISCUSSION Difference

The low noise amplifier is a front end device in the Frequency 2.4GHz 2.4GHz
receivers system. Thus it is commonly found after the antenna.
One of the common property of the antenna is that it must be Input Matching
-37.2 -20.1 60%
properly matched to obtain a maximum power transfer. Hence, S11 (dB)
the LNA needs to follow the rule of matching to properly
receive all the signals from the antenna and do its role to S12 (dB) -29.3 -29.5 0.68%
amplify it while contributing minimum noise to the signal.
In order to perform the simulation process, the designed
LNA must be tested according to the test fixture shown in Fig. Gain, S21 (dB) 20.7 19.5 5.97%
6. A DC blocking capacitor, RF choke inductor and ports are
used to conduct the s-parameter of the design. A 50Ω ports Output
was matched in the input and output of the design representing Matching S22 -43.1 -32.4 28.34%
the impedance of the antenna to be matched. The researcher (dB)
chooses the 50Ω impedance because it is the most common
NF (dB) 5.8 7.33 23.30%
characteristic impedance of an antenna. The design is
supplied with a 1.2V.
Nfmin (dB) 2.55 3.91 42.10%

Fig. 6 Design Test Fixture

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 2019 19th International Symposium on Communications and Information Technologies
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TABLE II. COMPARISON OF STUDY WITH THE SAME TECHNOLOGY S12 -29.5
Parameter This [15] [15] [18] [19] (dB) N/A N/A
Work LNA1 LNA2 Noise 7.3
Technology 65nm 65nm 65nm 65nm 65nm Figure Nfmin:
Supply 1.2 1.5 1.5 & 1& (dB) 2.5 4.1dB
(V) 1 1.2
Frequency 2.4G 100M, 2.4G 56G 80G
(Hz) 1M & This study compared from the references has a well
100K balance design in the parameters of gain and matching. There
Bandwidth 83.5 N/A N/A N/A N/A might be some parameters that this study may be slightly
(MHz) inferior from the references; still there is a parameter in which
S11 -20.1 -19.49 -37.7 N/A -13 & - it is better to compensate this. The other studies referred in
(dB) 11 this study has different technology, thus there is a difference in
S21 19.5 26.64 10.5 22.4 & 2.1 & the difficulty of achieving the post simulation parameters
(dB) 18.7 7.2 close enough to its pre simulation parameters due to the
different parasitic extractions between different technology
S22 -32.4 N/A -28.1 N/A -6 & -9
process in the layout design. The researcher also found out
(dB)
that there are few designs being studied in 65nm process in the
S12 -29.5 N/A N/A N/A N/A
same technology process and operating frequency. It may be
(dB)
due to the difficulty in the layout design. Study [15] in the
Noise 7.3 2.22 & Nfmin: Nfmin: 4.5 &
references is only conducted or simulated in its schematic
Figure (dB) 3.51 2.5 4.5 & 5.7
design and there is no implementation to it in the layout design
5.2
process. This study relaxed its value on noise figure to achieve
a high gain and high matching parameters due to trade off of
TABLE III. COMPARISON OF STUDY WITH DIFFERENT TECHNOLOGY
the parameters. Study [18] and [19] both implemented on the
same technology process but different in the operating
Parameter This [9] [9] [9] [9] frequencies. These study compared to others in the higher
Work LNA1 LNA2 LNA3 LNA4 technology process has a greater noise figure and lower
Technology 65nm 0.18µm 0.18µm 0.18µm 0.18µm matching parameter which might be because of the challenges
Supply 1.2 1 1 0.6 1 in the layout design in lower technology process.
(V)
Frequency 2.4G 2.4G 2.4G 2.4G 2.4G
(Hz)
Bandwidth 83.5 83.5 83.5 83.5 83.5
(MHz)
S11 -20.1 -11 -20 -22 -12
(dB)
S21 19.5 15 14.8 14 21.7
(dB)
S22 -32.4 N/A N/A N/A N/A
(dB)
S12 -29.5 -63.1 -37 -35.1 -63.1
(dB)
Noise 7.3 5 4.5 3.55 4.9
Figure
(dB)
Parameter This [16] [17]
Work
Technology 65nm 0.13µm 0.18µm
Supply 1.2
(V) 0.9 N/A
Frequency 2.4G 3GHz-
(Hz) 2.4GHz 5GHz
Bandwidth 83.5
(MHz) N/A 2GHz
S11 -20.1
(dB) -37.7 -7.8
S21 19.5 Fig. 18 Proposed LNA Layout Design
(dB) 10.5 19.5
S22 -32.4
(dB) -28.1 -14

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 2019 19th International Symposium on Communications and Information Technologies
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VI. CONCLUSIONS AND RECOMMENDATIONS
There is clearly a huge difference between the pre
simulation and post simulation of the matching parameters and
in the noise figure. The layout design suffers in the parasitic
capacitance and resistance that greatly affects the schematic
design of the LNA system. The LNA design implemented in
this research applies the use of an active inductor which
utilizes the transconductance and capacitance of a transistor
(shown in eqn. 3.3) through a gyrator-C network to form a
synthesized inductor. Thus adding a parasitic capacitance or
resistance to the system can change the tuning of the
frequency. Also, the input impedance of the system is mostly
defined by the feedback resistor and the bias current of the
cascode stage which can be adjusted by the feedback capacitor
while the output matching is mostly achieved by the output
buffer thus the matching parameters also suffers a great
change to the addition of the parasitic capacitance and
resistance to the system. However, given this drastic change,
the researcher still manages to satisfy the requirement for
IEEE 802.15.4 application for LNA. Careful considerations
must be thought in the layout design for smaller technology
processes such as 65nm because of the many parasitic that can
greatly affect the design.
ACKNOWLEDGEMENT
The researchers would like to thank the Microelectronics
Laboratory of MSU-IIT and the Department of Science and
Technology - Philippine Council for Industry, Energy, and
Emerging Technology Research and Development (DOST-
PCIEERD) for the integrated circuits design tools being
provided for this research.
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