EXPERIMENT NO.

AIM: To construct and analyse JK flip-flop and T flip-flop using NAND gate

APPARATUS:
 Breadboard
 Connecting wires
 ICs (7404 NOT gate, 7410 NAND gate)
 LEDs
 Resistors

THEORY:

The sequential operation of the JK flip flop is exactly the same as for the previous SR flip-flop
with the same “Set” and “Reset” inputs. The difference this time is that the “JK flip flop” has
no invalid or forbidden input states of the SR Latch even when S and R are both at logic “1”.

The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that
prevents the illegal or invalid output condition that can occur when both inputs S and R are
equal to logic level “1”. Due to this additional clocked input, a JK flip-flop has four possible
input combinations, “logic 1”, “logic 0”, “no change” and “toggle”. The symbol for a JK flip
flop is similar to that of an SR Bistable Latch as seen in the previous tutorial except for the
addition of a clock input.

Then the JK flip-flop is basically an SR flip flop with feedback which enables only one of its
two input terminals, either SET or RESET to be active at any one time thereby eliminating the
invalid condition seen previously in the SR flip flop circuit.

Also when both the J and the K inputs are at logic level “1” at the same time, and the clock
input is pulsed “HIGH”, the circuit will “toggle” from its SET state to a RESET state, or visa-
versa. This results in the JK flip flop acting more like a T-type toggle flip-flop when both
terminals are “HIGH”.

Although this circuit is an improvement on the clocked SR flip-flop it still suffers from timing
problems called “race” if the output Q changes state before the timing pulse of the clock input
has time to go “OFF”. To avoid this the timing pulse period ( T ) must be kept as short as
possible (high frequency). As this is sometimes not possible with modern TTL IC’s the much
improved Master-Slave JK Flip-flop was developed.

T flip – flop is also known as “Toggle Flip – flop”. To avoid the occurrence of intermediate
state in SR flip – flop, we should provide only one input to the flip – flop called Trigger input
or Toggle input (T). Then the flip – flop acts as a Toggle switch. Toggling means ‘Changing
the next state output to complement of the present state output’.
We can design the T flip – flop by making simple modifications to the JK flip – flop. The T
flip – flop is a single input device and hence by connecting J and K inputs together and giving
them with single input called T we can convert a JK flip – flop into T flip – flop. So a T flip –
flop is sometimes called as single input JK flip – flop.

CONCLUSION:
We have successfully implemented the experiment by constructing JK flipflop using NAND
gates and NOT gates. The results have been verified using truth table. The J-K flip-flop, the
most widely used flip-flop design, is considered as the universal flip-flop circuit. Its sequential
operation is the same as the S-R flip-flop with set and reset inputs. But it has no forbidden or
invalid input states of the S-R Latch, when both inputs S and R, are both equal to logic 1. Due
to its added clocked input circuitry, a JK flip-flop has four possible input combinations, “logic
1”, “logic 0”, “no change” and “toggle”. When both inputs are low, then no change occurs but
if both are high, the output will toggle from one state to the other. It can perform the functions
of the set/reset flip-flop and has the advantage that there are no ambiguous states.The T or
“toggle” flip-flop changes its output on each clock edge, giving an output which is half the
frequency of the signal to the T input. It is useful for constructing binary counters, frequency
dividers, and general binary addition devices. It can be made from a J-K flip-flop by tying both
of its inputs high.