8086

Microprocesso
r
Jibesh Kanti Saha

Dept of EEE, SUST.

 Microprocessor

Program controlled semiconductor device (IC)

which fetches (from memory), decodes and
executes instructions.

It is used as CPU (Central Processing Unit) in

computers.
Microprocessor
Third Generation
During 1978
HMOS technology  Faster speed, Higher packing
density
16 bit processors  40/ 48/ 64 pins
Easier to program
Dynamically relatable programs
Processor has multiply/ divide arithmetic hardware
More powerful interrupt handling capabilities
Flexible I/O port addressing
Intel 8086 (16 bit processor)
First Generation
Between 1971 – 1973
PMOS technology, non compatible with TTL
4 bit processors  16 pins
8 and 16 bit processors  40 pins
Due to limitations of pins, signals are multiplexed
Fifth Generation Pentium
Fourth Generation
During 1980s
Low power version of HMOS technology (HCMOS)
32 bit processors
Physical memory space 224 bytes = 16 Mb
Virtual memory space 240 bytes = 1 Tb
Floating point hardware
Supports increased number of addressing modes
Intel 80386
Second Generation
During 1973
NMOS technology  Faster speed, Higher density,
Compatible with TTL
4 / 8/ 16 bit processors  40 pins
Ability to address large memory spaces and I/O ports
Greater number of levels of subroutine nesting
Better interrupt handling capabilities
Intel 8085 (8 bit processor)
 Heart of a Microprocessor
• Heart of the microprocessor is
known as central processing
unit.
• It consists:
1. Registers.
2. Arithmetic Logic Unit (ALU)
3. Control Unit (CU)
• Processor also have memory
unit with bus interface units.
• Microprocessor as its own has
no meaning.
• It needs input devices and
output devices.
 How does the processor connect to the external world
• Processor has 3 kinds of buses:
1. Address bus
2. Data bus
3. Control bus
• Bus = configuration that contains many
wires of similar kinds.
• These buses are connected to various
I/O devices, peripheral devices and
memory devices.
• Input devices gives data and output
device takes data.
• How does the processor know if the
device is input or output?
• Using address decoder: it takes address
lines from processor, decodes it and
triggers various devices we connect.
What does your processor understands?
 Architecture of 8086
• How is a processor defined?

7
 Architecture of 8086
• Divided into two parts:
1. Bus Interface Unit (BIU)
2. Execution Unit (EU)\
• Execution unit : Executes everything for
the processor. Consists :
1. ALU: Performs arithmetic and
logical operations required of any
program.
2. General purpose registers : these
register can be addressed as 8 bit
or 16 bit register.
• Bus interface unit: communication
purpose. Consists of:
1. Segment registers: used to address
memory space. (ROM/RAM).
2. Address compute Engine: Converts
the logical address that is held by
the segment register into a physical
address.
8
3. Instruction queue.
8086 Microprocessor
Bus Interface Unit (BIU)

Architecture
Segment Code Segment Register
Registers

16-bit

CS contains the base or start of the current code segment;

IP contains the distance or offset from this address to the
next instruction byte to be fetched.

BIU computes the 20-bit physical address by logically

shifting the contents of CS 4-bits to the left and then adding
the 16-bit contents of IP.

That is, all instructions of a program are relative to the

contents of the CS register multiplied by 16 and then offset
is added provided by the IP. 9
8086 Microprocessor
Bus Interface Unit (BIU)

Architecture
Segment Data Segment Register
Registers

16-bit

Points to the current data segment; operands for most

instructions are fetched from this segment.

The 16-bit contents of the Source Index (SI) or Destination

Index (DI) or a 16-bit displacement are used as offset for
computing the 20-bit physical address.

10
8086 Microprocessor
Bus Interface Unit (BIU)

Architecture
Segment Stack Segment Register
Registers

16-bit

Points to the current stack.

The 20-bit physical stack address is calculated from the

Stack Segment (SS) and the Stack Pointer (SP) for stack
instructions such as PUSH and POP.

In based addressing mode, the 20-bit physical stack

address is calculated from the Stack segment (SS) and the Base
Pointer (BP).

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8086 Microprocessor
Bus Interface Unit (BIU)

Architecture
Segment
Registers Extra Segment Register

16-bit

Points to the extra segment in which data (in excess of 64K

pointed to by the DS) is stored.

String instructions use the ES and DI to determine the 20-bit

physical address for the destination.

12
8086 Microprocessor
Bus Interface Unit (BIU)

Architecture
Segment Instruction Pointer
Registers

16-bit

Always points to the next instruction to be

executed within the currently executing code
segment.

So, this register contains the 16-bit offset address

pointing to the next instruction code within the
64Kb of the code segment area.

Its content is automatically incremented as the

execution of the next instruction takes place.
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8086 Microprocessor
Bus Interface Unit (BIU)
Architecture
Instruction queue

A group of First-In-First-Out
(FIFO) in which up to 6 bytes
of instruction code are pre
fetched from the memory
ahead of time.

This is done in order to speed

up the execution by
overlapping instruction fetch
with execution.

This mechanism is known as

pipelining.
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8086 Microprocessor
Execution Unit (EU)

Architecture
EU Accumulator Register (AX)
Registers

Consists of two 8-bit registers AL and AH, which can be

combined together and used as a 16-bit register AX.

AL in this case contains the low order byte of the word, and
AH contains the high-order byte.

The I/O instructions use the AX or AL for inputting /

outputting 16 or 8 bit data to or from an I/O port.

Multiplication and Division instructions also use the AX or

AL.

15
8086 Microprocessor
Execution Unit (EU)

Architecture Base Register (BX)

EU
Registers

Consists of two 8-bit registers BL and BH, which can

be combined together and used as a 16-bit register
BX.

BL in this case contains the low-order byte of the

word, and BH contains the high-order byte.

This is the only general purpose register whose

contents can be used for addressing the 8086
memory.

All memory references utilizing this register content

for addressing use DS as the default segment
register. 16
8086 Microprocessor
Execution Unit (EU)
Architecture
Counter Register (CX)
EU
Registers
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.

When combined, CL register contains the low order byte

of the word, and CH contains the high-order byte.

Instructions such as SHIFT, ROTATE and LOOP use the

contents of CX as a counter.
Example:

The instruction LOOP START automatically decrements CX

by 1 without affecting flags and will check if [CX] = 0.

If it is zero, 8086 executes the next instruction; otherwise

the 8086 branches to the label START. 17
8086 Microprocessor
Execution Unit (EU)

Architecture
EU
Registers Data Register (DX)

Consists of two 8-bit registers DL and DH, which can

be combined together and used as a 16-bit register
DX.

When combined, DL register contains the low order

byte of the word, and DH contains the high-order byte.

Used to hold the high 16-bit result (data) in 16 X 16

multiplication or the high 16-bit dividend (data) before
a 32 16 division and the 16-bit reminder after
division.

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8086 Microprocessor
Execution Unit (EU)

Architecture
EU Stack Pointer (SP) and Base Pointer (BP)
Registers
SP and BP are used to access data in the stack
segment.

SP is used as an offset from the current SS during

execution of instructions that involve the stack
segment in the external memory.

SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH
instruction.

BP contains an offset address in the current SS,

which is used by instructions utilizing the based
addressing mode.
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8086 Microprocessor
Execution Unit (EU)
Architecture
EU Source Index (SI) and Destination Index (DI)
Registers
Used in indexed addressing.

Instructions that process data strings

use the SI and DI registers together
with DS and ES respectively in order
to distinguish between the source and
destination addresses.

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 8086 Microprocessor
Execution Unit (EU)
Architecture Auxiliary Carry Flag Carry Flag
Flag Register
This is set, if there is a carry from the lowest nibble, This flag is set, when there is a carry out
i.e, bit three during addition, or borrow for the of MSB in case of addition or a borrow in
lowest nibble, i.e, bit three, during subtraction. case of subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the result of This flag is set, if the result of the This flag is set to 1, if the lower byte of the
any computation is negative computation or comparison performed by result contains even number of 1’s ; for odd
an instruction is zero number of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
Over flow Flag If this flag is set, the processor enters the
This flag is set, if an overflow occurs, i.e, if the result of a signed operation is large
single step execution mode by generating
enough to accommodate in a destination register. The result is of more than 7-bits in
size in case of 8-bit signed operation and more than 15-bits in size in case of 16-bit sign
internal interrupts after the execution of
operations, then the overflow will be set. each instruction

Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit is ‘0’, the string is
processed beginning from the lowest address to the highest address, i.e., auto Causes the 8086 to recognize external mask
incrementing mode. Otherwise, the string is processed from the highest address interrupts; clearing IF disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 21
 8086 Microprocessor
Addressing Modes
Every instruction of a program has to operate on a data.
The different ways in which a source operand is denoted in an instruction are
known as addressing modes.

1. Register Addressing
Group I : Addressing modes for register and immediate data
2. Immediate Addressing

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing
Group II : Addressing modes for memory data
6. Indexed Addressing

7. Based Index Addressing

8. String Addressing

9. Direct I/O port Addressing

Group III : Addressing modes for I/O ports
10. Indirect I/O port Addressing

11. Relative Addressing Group IV : Relative Addressing mode

12. Implied Addressing Group V : Implied Addressing

22 mode
 8086 Microprocessor
Addressing Modes Group I : Addressing modes for register and immediate data

1. Register Addressing The instruction will specify the name of the register which holds the
data to be operated by the instruction. Source operand, destination
2. Immediate Addressing operand or both contained in 8086 register

3. Direct Addressing Example:

MOV CL, DH
4. Register Indirect Addressing

5. Based Addressing NB:The register size must be same

6. Indexed Addressing MOV BX, CH is illegal

The content of 8-bit register DH is moved to another 8-bit register
7. Based Index Addressing CL

8. String Addressing (CL)  (DH)

9. Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

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 8086 Microprocessor
Addressing Modes Group I : Addressing modes for register and immediate data

1. Register Addressing
In immediate addressing mode, an 8-bit or 16-bit data is specified
2. Immediate Addressing as part of the instruction
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is moved to DL
6. Indexed Addressing
(DL)  08H
7. Based Index Addressing

8. String Addressing MOV AX, 0A9FH

9. Direct I/O port Addressing The 16-bit data (0A9FH) given in the instruction is moved to AX
register
10. Indirect I/O port Addressing

11. Relative Addressing (AX)  0A9FH

12. Implied Addressing Source operand is in immediate mode and destination operand is in
register mode

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86 Microprocessor
Addressing Modes : Memory Access
20 Address lines  8086 can address up to 220 = 1M bytes of memory

However, the largest register is only 16 bits

Physical Address will have to be calculated Physical Address : Actual address of a byte in
memory. i.e. the value which goes out onto the address bus.

Memory Address represented in the form – Seg : Offset (Eg - 89AB:F012)

Each time the processor wants to access memory, it takes the contents of a segment
register, shifts it one hexadecimal place to the left (same as multiplying by 1610), then add
the required offset to form the 20- bit address

16 bytes of contiguous memory

89AB : F012  89AB  89AB0 (Paragraph to byte  89AB x 10 = 89AB0)

F012  0F012 (Offset is already in byte unit)
+ -------
98AC2 (The absolute address)
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 8086 Microprocessor
Addressing Modes Group II : Addressing modes for memory data

1. Register Addressing

2. Immediate Addressing
Here, the effective address of the memory location at which the
3. Direct Addressing
data operand is stored is given in the instruction.
4. Register Indirect Addressing
The effective address is just a 16-bit number written directly in
5. Based Addressing the instruction.

6. Indexed Addressing Example:

7. Based Index Addressing MOV BX, [1354H]

MOV BL, [0400H]
8. String Addressing
The square brackets around the 1354H denotes the contents of the
9. Direct I/O port Addressing
memory location. When executed, this instruction will copy the
contents of the memory location into BX register.
10. Indirect I/O port Addressing

11. Relative Addressing This addressing mode is called direct because the displacement of
the operand from the segment base is specified directly in the
12. Implied Addressing instruction.

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Process
• IF EA= 0040 and DS=3050 then BIU generates 20 bit physical address
by adding 4 zeros to LSB of DS in binary and then add EA+DS=
0040+30500=30540
• BIU generates this address 30540 on the 8086 pins and then initiates
memory read cycle to read the 16 bit data starting from 30540
location.
• Memory logic places 16 bit contents of locations 30540 and 30541 on
data pins.
• BIU transfer this data to EU
• EU then moves the data to CX

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 8086 Microprocessor
Addressing Modes Group II : Addressing modes for memory data

1. Register Addressing In Register indirect addressing, name of the register which holds
the effective address (EA) will be specified in the instruction.
2. Immediate Addressing
Registers used to hold EA are any of the following registers:
3. Direct Addressing
BX, BP, DI and SI.
4. Register Indirect Addressing
Content of the DS register is used for base address calculation.
5. Based Addressing
Example:
6. Indexed Addressing

7. Based Index Addressing MOV CX, [BX]

8. String Addressing Operations:

Note : Register/ memory enclosed in brackets
refer to content of register/ memory
9. Direct I/O port Addressing EA = (BX)
BA = (DS) x 1610
10. Indirect I/O port Addressing MA = BA + EA

11. Relative Addressing (CX)  (MA) or,

12. Implied Addressing (CL)  (MA)
(CH)  (MA +1)

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Process
• MOV [DI] BX : The offset value is stored in DI(0020) and this is added
with DS(5004). After adding this will give 20 bit address (50060).
• Then the contents of BL and BH are moved to memory location 50060
and 50061 respectively

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 8086 Microprocessor
Addressing Modes Group II : Addressing modes for memory data

1. Register Addressing In Based Addressing, BX or BP is used to hold the base value for
effective address and a signed 8-bit or unsigned 16-bit
2. Immediate Addressing displacement will be specified in the instruction.

3. Direct Addressing In case of 8-bit displacement, it is sign extended to 16-bit before

adding to the base value.
4. Register Indirect Addressing
When BX holds the base value of EA, 20-bit physical address is
5. Based Addressing calculated from BX and DS.
6. Indexed Addressing
When BP holds the base value of EA, BP and SS is used.
7. Based Index Addressing
Example:
8. String Addressing
MOV AX, [BX + 08H]
9. Direct I/O port Addressing
Operations:
10. Indirect I/O port Addressing
0008H  08H (Sign extended)
11. Relative Addressing EA = (BX) + 0008H
BA = (DS) x 1610
12. Implied Addressing MA = BA + EA

(AX)  (MA) or,

(AL)  (MA)
(AH)  (MA + 1)

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 8086 Microprocessor
Addressing Modes Group II : Addressing modes for memory data

1. Register Addressing SI or DI register is used to hold an index value for memory data
and a signed 8-bit or unsigned 16-bit displacement will be specified
2. Immediate Addressing in the instruction.

3. Direct Addressing Displacement is added to the index value in SI or DI register to

obtain the EA.
4. Register Indirect Addressing
In case of 8-bit displacement, it is sign extended to 16-bit before
5. Based Addressing adding to the base value.
6. Indexed Addressing
Example:
7. Based Index Addressing

8. String Addressing MOV CX, [SI + 0A2H]

9. Direct I/O port Addressing Operations:

10. Indirect I/O port Addressing FFA2H  A2H (Sign extended)

11. Relative Addressing EA = (SI) + FFA2H

BA = (DS) x 1610
MA = BA + EA
12. Implied Addressing
(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA + 1)

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 8086 Microprocessor
Addressing Modes Group II : Addressing modes for memory data

1. Register Addressing
In Based Index Addressing, the effective address is computed from
2. Immediate Addressing the sum of a base register (BX or BP), an index register (SI or DI)
and a displacement.
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DX, [BX + SI + 0AH]
5. Based Addressing
Operations:
6. Indexed Addressing
000AH  0AH (Sign extended)
7. Based Index Addressing

8. String Addressing EA = (BX) + (SI) + 000AH

BA = (DS) x 1610
9. Direct I/O port Addressing MA = BA + EA

10. Indirect I/O port Addressing (DX)  (MA) or,

11. Relative Addressing (DL)  (MA)

(DH)  (MA + 1)
12. Implied Addressing

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 8086 Microprocessor
Addressing Modes Group II : Addressing modes for memory data

1. Register Addressing Employed in string operations to operate on string data.

The effective address (EA) of source data is stored in SI register
2. Immediate Addressing and the EA of destination is stored in DI register.

3. Direct Addressing Segment register for calculating base address of

source data is DS and that of the destination data is ES
4. Register Indirect Addressing
Example: MOVS BYTE
5. Based Addressing
Operations:
6. Indexed Addressing
Calculation of source memory location:
7. Based Index Addressing
EA = (SI) BA = (DS) x 1610 MA = BA + EA
8. String Addressing
Calculation of destination memory location:
9. Direct I/O port Addressing EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE

10. Indirect I/O port Addressing

(MAE)  (MA)
11. Relative Addressing
If DF = 1, then (SI)  (SI) – 1 and (DI) = (DI) - 1
12. Implied Addressing If DF = 0, then (SI)  (SI) +1 and (DI) = (DI) + 1

Note : Effective address of the Extra segment

register

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 8086 Microprocessor
Addressing Modes Group III : Addressing modes for I/O ports

1. Register Addressing These addressing modes are used to access data from standard I/O
mapped devices or ports.
2. Immediate Addressing
In direct port addressing mode, an 8-bit port address is directly
3. Direct Addressing specified in the instruction.

4. Register Indirect Addressing Example: IN AL, [09H]

5. Based Addressing Operations: PORTaddr = 09H

(AL)  (PORT)
6. Indexed Addressing

7. Based Index Addressing

8. String Addressing
9. Direct I/O port Addressing
10. Indirect I/O port Addressing
11. Relative Addressing
12. Implied Addressing
Content of port with address 09H is moved to AL register
In indirect port addressing mode, the instruction will specify the
name of the register which holds the port address. In 8086, the 16-
bit port address is stored in the DX register.
Example: OUT [DX], AX
Operations: PORTaddr = (DX)
(PORT)  (AX)

Content of AX is moved to port whose address is specified by DX

register.

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 8086 Microprocessor
Addressing Modes Group IV : Relative Addressing mode

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing In this addressing mode, the effective address of a program

instruction is specified relative to Instruction Pointer (IP) by an 8-
4. Register Indirect Addressing bit signed displacement.

5. Based Addressing Example: JZ 0AH

6. Indexed Addressing
Operations:
7. Based Index Addressing
000AH  0AH (sign extend)
8. String Addressing
If ZF = 1, then
9. Direct I/O port Addressing
EA = (IP) + 000AH
10. Indirect I/O port Addressing BA = (CS) x 1610
MA = BA + EA
11. Relative Addressing
If ZF = 1, then the program control jumps to new address
12. Implied Addressing calculated above.

If ZF = 0, then next instruction of the program is executed.

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 8086 Microprocessor Group IV : Implied Addressing mode

Addressing Modes
1. Register Addressing

2. Immediate Addressing

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing

6. Indexed Addressing
Instructions using this mode have no operands. The instruction
itself will specify the data to be operated by the instruction.
7. Based Index Addressing

8. String Addressing Example: CLC

9. Direct I/O port Addressing This clears the carry flag to zero.

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

36
8086 Microprocessor

Instruction Set
8086 supports 6 types of instructions.

1. Data Transfer Instructions

2. Arithmetic Instructions

3. Logical Instructions

4. String manipulation Instructions

5. Process Control Instructions

6. Control Transfer Instructions

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8086 Microprocessor

Instruction Set
1. Data Transfer Instructions

Instructions that are used to transfer data/ address in to registers, memory locations and I/O ports.
Generally involve two operands: Source operand and Destination operand of the same size.

Source: Register or a memory location or an immediate data

Destination : Register or a memory location.

The size should be a either a byte or a word.

A 8-bit data can only be moved to 8-bit register/ memory and a 16-bit data can be moved to 16-bit register/
memory.

38
 8086 Microprocessor
Instruction Set
1. Data Transfer Instructions
Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

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8086 Microprocessor
Instruction Set
5. Processor Control Instructions
Mnemonics Explanation
STC Set CF  1

CLC Clear CF  0

CMC Complement carry CF  CF/

STD Set direction flag DF  1

CLD Clear direction flag DF  0

STI Set interrupt enable flag IF  1

CLI Clear interrupt enable flag IF  0

NOP No operation

HLT Halt after interrupt is set

WAIT Wait for TEST pin active

ESC opcode mem/ reg Used to pass instruction to a coprocessor which shares the address and data bus
with the 8086

LOCK Lock bus during next instruction

 8086 Microprocessor
Instruction Set

6. Control Transfer Instructions

 8086 signed conditional branch  8086 unsigned conditional branch

instructions instructions

Checks flags

If conditions are true, the program control is transferred to the new

memory location in the same segment by modifying the content of IP

41
 8086 Microprocessor
Instruction Set

6. Control Transfer Instructions

 8086 signed conditional branch  8086 unsigned conditional branch

instructions instructions

Name Alternate name Name Alternate name

JE disp8 JZ disp8 JE disp8 JZ disp8
Jump if equal Jump if result is 0 Jump if equal Jump if result is 0

JNE disp8 JNZ disp8 JNE disp8 JNZ disp8

Jump if not equal Jump if not zero Jump if not equal Jump if not zero
JG disp8 JNLE disp8 JA disp8 JNBE disp8
Jump if greater Jump if not less or equal Jump if above Jump if not below or
equal
JGE disp8 JNL disp8
Jump if greater than or Jump if not less JAE disp8 JNB disp8
equal Jump if above or equal Jump if not below
JL disp8 JNGE disp8 JB disp8 JNAE disp8
Jump if less than Jump if not greater than Jump if below Jump if not above or
or equal equal
JLE disp8 JNG disp8
Jump if less than or Jump if not greater JBE disp8 JNA disp8
equal Jump if below or equal Jump if not above

42
8086 Microprocessor
Instruction Set

6. Control Transfer Instructions

 8086 conditional branch instructions affecting individual flags

Mnemonics Explanation

JC disp8 Jump if CF = 1

JNC disp8 Jump if CF = 0

JP disp8 Jump if PF = 1

JNP disp8 Jump if PF = 0

JO disp8 Jump if OF = 1

JNO disp8 Jump if OF = 0

JS disp8 Jump if SF = 1

JNS disp8 Jump if SF = 0

JZ disp8 Jump if result is zero, i.e, Z = 1

JNZ disp8 Jump if result is not zero, i.e, Z = 1

43
 Interrupt of 8086

Why do we need Interrupt?

• We have an endless loop of program

execution
• Assume a whole loop of program
compeltes in 20 ms.
• Suppose we want an input from an
keyboard.
• The built in keyboard driver checks if
any key is pressed once in every
20ms. {polling}
• Which is very slow.
 Interrupt of 8086

What happens with interrupt?

• When a key is pressed interrupt
controller gets into operation.
• Interrupt controller maybe a part of
the processor or a external device.
• It interrupts the processor
• Processor services the interrupt
service routine (ISR) (Stopping earlier
process).
• After that processor return to its past
program
Interrupt of 8086
 Interrupt of 8086
Steps:
At the end of each instruction cycle 8086 checks
to see if any int service is requested:
1. SP-2 and push flag register to stack
2. Disables 8086 by clearing IF in flag
register
3. Resets trap flag
4. SP-2 and pushes current instruction
pointer on the stack
5. Starts the interrupt service program
(ISR)
6. IRET instruction at the end of the
interrupt service
7. Returns to main program
 Interrupt of 8086
Software Interrupts: Type 32-255 (80h-3ffh) free
Predefined 5 for user defining.

1. Every interrupt contains CS and IP

values (4 byte).
2. Type 0 (Divide by Zero)
• How It works? (from hall)
3. Type 1 (Single Step)
• What it does?
4. Type 2 (NMI)
• Examples
5. Breakpoint
6. Overflow
• Why do we need it?
• In response of overflow error
 Interrupt of 8086

When do you use what kind of interrupts?

 Interrupt of 8086
The INT instrutions Type 32-255 (80h-3ffh) free
for user defining.
1. INT interrupt_number
It invokes a software interrupt routine
INT 21h
This instructions have a lot of functions.
Particular functions are requested by placing a
number in AH register.
Function Number Routine
1 Single key input
2 Single character input
9 Character string input

INT 21h, function 9 enables us the LEA (LOAD EFFECTIVE ADDRESS) instruction.
LEA DX, MSG ; providing msg is stored before
MOV AH,9;
INT 21h
 Programmable Interrupt Controller

8259A
• It’s a specific peripheral device that
can be connected to 8086 to manage
complex interrupt Systems.
• 8086 only have two hardware
interrupts.
• So complex systems cant be utilized.
• So we use 8259A
• It supports 8 different hardware
interrupts at a time.
• IR0 – IR7
 Programmable Interrupt Controller
8259A Block diagram
 Programmable Interrupt Controller
8259A Block diagram

• This is the heart of 8259A

• It controls the interrupting system coming from external
world.
• IRR = accepts, blocks and stores interrupt requests
• PR = This logic blocks prioritizes the interrupt services.
• ISR = tells what interrupt services are serviced by the
processor.
• IMR = Masks a specific interrupt and prevents it from
being recognized.

• Cascaded buffer allows more complex

interrupt systems to be build.
• Its three terminals can be used to cascade
multiple 8259A.
 Programmable Interrupt Controller
Master-Slave configuration

• Connect interrupt pin of slaves to

one of input of master
• If SP/EN = Vcc = Master
• If SP/EN = GND = Slave
• Data bus is common for master and
slaves
• Connect all the cascade pins
altogether
• The master INT output goes to
processor.
 Programmable Interrupt Controller
Master-Slave configuration
How processor knows which interrupt to execute out of all 64?

All of these works is configured by programming 8269A

 Memory Devices
Kinds of READ/WRITE and READ only memory devices

• All kinds of ROM, RAM

• Advantage-disadvantage
• Flash memory devices
• Mathivanan page 63-65
 Memory Devices
Memory map in 8086
 Memory Devices
Hardware organization of memory banks

• 8086 have 16 data lines.

• Design such as we have two memory bank :
EVEN and ODD.
• EVEN memories resides to D0-D7 lines.
• ODD memories resides to D8-D15 data lines.
• Both have common A1-A19 address lines.
• A1-19 addresses a specific location on
memory bank.
• If A0 is high we get access to even memory
bank and get data in d0-d7 data lines.
• If BHE is low we get access to odd memory
bank and get data in d8-d15 data lines.
 I/O Access
How can one access I/O using 8086
 I/O Access
Memory mapped I/O

• I/O devices are treated as memory locations and

referred by address of memory locations.
• Data bus, Address but and control signals are
connected to memory.
• The I/O devices are located anywhere between
the reserved memory locations.
• MOV is used to access input from input device
• Also to write output to output device.
• MEMR pin of 8086 is used for read operations of
I/O devices.
• MEMW pin is used for wire operations of I/O
devices.
 I/O Access
I/O mapped I/O
• We have another separate I/O space (64 KB)
• Data bus is common and interconnected.
• Address lines are same and interconnected.
• For I/O mapped I/O different read/write control
signals are used.
• For programming IN/OUT instructions are used.
• 8086 automatically detects what I/O process is being
used:
• When MOV instruction is detected M/IO~ pin is
set to high automatically
• When IN/OUT instruction is detected this pin is
set to low automatically.
 I/O Communication
Parallel I/O methods
• 8 or 16 bit data transferred on 8 or 16 parallel lines.
• Processor needs to check readiness of peripherals as they are slow to generate or accept data

1. Simple I/O
I. Assume peripheral is always ready to send or receive data.
II. I/O read operation enables the input port and transfers status information to data bus.
III. Similarly, I/O write operation enables the output port and transfers the data byte to peripheral.
2. Strobe I/O
I. Used when peripheral devices are slow and not always ready.
II. Slow devices must generate a control signal called Strobe.
III. Data is sent with the strobe signal and strobe signal indicates that data is ready.
IV. Readiness of peripheral is checked by microprocessor by the method of polling and interrupt.

Detail mathivanan
 I/O Communication
Parallel I/O methods
1. Handshake
I. Processor and peripheral exchange handshake signals to indicate readiness of peripherals
and to synchronize timing of data transfer.
II. Two types:
A. Single handshake: Only microprocessor checks for readiness
B. Double handshake: Both microprocessor and peripheral exchange signals.
2. DMA controlled I/O
I. Usually microprocessor controls the process of data transfer between processor and
peripherals.
II. But peripherals with high speed in this case takes over.
III. Capable of transferring at much higher rate than processor.
IV. DMA controlled is used to manage all transfers.

Detail mathivanan
 Programmable Peripheral Interface
8255A
• 40 pin DIP chip that helps 8086 to manage I/O devices and data in different modes
• Has 24 input/output pins divided among 3 ports : port A, Port B and Port C.
• Port A and port B are two 8 bit parallel ports
• Port C can be one port or individual bits or two 4-bit port
 Programmable Peripheral Interface
8255A
• Port A and port B are bidirectional I/O port.
• They are either latched output or buffered input.
• Port C is the control port.
• Port C can also assist I/O function of port A and B.
• 8255 has a control register and a byte written into it which controls
the i/o functions of the ports.
• The I/O ports of 8255 can be configured to operate in three
different mode:
1. Mode-0 : Simple I/O
2. Mode-1 : handshake I/O
3. Mode -2: bidirectional bus
• The other mode that 8255 offers is the BSR mode
1. Involves port C
2. Each of the port C can be individually set or reset
 Programmable Peripheral Interface
8255A
• Mode 0: (simple I/O)
1. Port A and B are used as two simple 8 bit I/O port.
2. Port C is used as two 4 bit I/O port.
3. Each port is programmed to function as an input port or an output port.
• Mode 1: (single handshake I/O)
1. Port A and B function as 8 bit I/O port.
2. Ports A and B each use three lines from port C as control signal.
3. Remaining lines of port C are used as simple I/O function.
4. I/O data can be latched and interrupt logic is supported.
• Mode 2: (bidirectional handshake)
1. Only port A is configured for bidirectional handshake I/O operation.
2. It enables data bytes to be transmitted and received on the same 8 lines.
3. Used to transfer data bytes to and from another slave processor.
4. Port B is in mode 1 or mode 0.
5. PC3- PC7 of port C carry 5 handshake signals for bidirectional op.
6. PC0-PC2 used as general purpose I/O or handshake for port B.
 Programmable Peripheral Interface
Programming of 8255A
• The ports are configured
to any mode by writing
control word into the
control register.
Programmable Peripheral Interface
Interfacing 8255A with 8086
 Direct Memory Access
• Needs a DMA controller (8237)
• 8086 in min mode has HOLD input.
• Data from I/O to memory = DMA
write
• Data from memory to I/O = DMA read
• I/O sends DREQ to controller
requesting DMA read/write.
• Controller sends HRQ(hold request) to
HOLD of microprocessor.
• Processor samples HOLD in the
middle of every clock cycle.
• When HOLD is detected, it stops
executing, floats its buses and sends
out HLDA( hold acknowledge) to
controller.
• The DMA controller sends out a
control signal that disconnects all
buses from processor and connect
them to itself.
 Direct Memory Access
• DMA controller gets control of the
buses and sends out the memory
address on the address bus where firs
byte of data from or to I/O device is
gonna be transferred.
• Finally, controller sends DACK (DMA
acknowledge) signal to I/O device.
• MEMR and IOW control signals DMA
read
• MEMW and IOR for DMA wirte on the
control bus.
• So, data transfer from or to I/O to
memory without passing through
microprocessor or DMA controller.
• Transfer complete? DMA controller
disables HOLD signal and releases
control of all buses.
• Processor regains control.
 Programmable Interval Timer (8254)
• 8254 contains three 16 bit counters: counter-0, counter-1
and counter-2.
• A data bus buffer
• A read/write control logic and
• A control word register.
• Data bus 8254 is connected to the data bus of the system
through bidirectional data line D0-D7.
• Read/wrote control logic receives control signals from
processor.
• It enables appropriate counter register or control register
for the transfer of count or control word.
• Each counter is individually programmed to operate in
one of six mode by writing separate control word into the
control register.
• Clock frequency of up to 8MHz is applied to CLK input.
• GATE enables or disables the counting in some mode of
operation.
 Programmable Interval Timer (8254)
• Clock frequency of up to 8MHz is applied to CLK input.
• GATE enables or disables the counting in some mode of operation.
• Counter generates output waveforms on the OUT line.
• 8255 has two address input pins A0 and A1, hence four internal addresses.
• The addresses are assigned to various counter and control registers:
CS RD WR A1 A0 Data bus operation
0 1 0 0 0 Write into counter-0
0 1 0 0 1 Write into counter-1
0 1 0 1 0 Write into counter-2
0 1 0 1 1 Write into control register
0 0 1 0 0 Read from counter-0
0 0 1 0 1 Read from counter-1
0 0 1 1 0 Read from counter-2
0 0 1 1 1 Tri-state
1 X X X X Tri-state
0 1 1 X X Tri-state
Programming the 8254
 Programming the 8254
• Write control word into control register.
• Clock signal is applied to the CLK input
• Gate input held high.
• Count value is loaded into a counter register.
• Counter decrements the count for each CLK pulse and gives out a pulse at its OUT when
count reaches zero.
• The current count value = counter register.
• Using control word load 8254 with a count between 0001h and FFFFh for binary sequence or
00001d and 9999d for BCD sequence.
• Steps for initializing a counter:
1. Write control word into control register.
2. Write Low-order byte followed by high order byte into counter register.
 8254 Modes of Operation
Six modes of operation:
1. Mode-0, Interrupt on terminal count
I. Gate controls Low and High on the OUT.
II. Can be used as interrupt signal.
2. Mode-1, Hardware-retriggerable one-shot
I. Gate triggers the counter and for the period of counting OUT=low.
II. Behaves like a retriggarable monostable mulitvibrator.
3. Mode-2, rate generator
I. Generates string of pulses.
II. Example: for count of 4, Out give pulse of 3 count (high), stops for 1 count (low)
4. Mode-3, square wave generator
I. Generates square wave
II. Same as mode-2, but OUT high for count/2 clock periods, low for the other half.
5. Mode-4, Software-triggered strobe
I. Produces a single pulse at its output.
6. Mode-5, Hardware-triggered strobe
I. Same as mode-4.
Detail Mathivanan
 Interfacing 8254 with 8086

Interfacing 8254 with 8086

Figure : Mathivanan
 Serial I/O Communication

• Used when data needs to transferred over a long distance.

• 8 or 16 bit data word from a transmitting system is converted to stream of bits by
parallel to serial conversion.
• One bit at a time is transferred via a single line to a receiving system.
• At receiving end the word is reconstructed by serial to parallel conversion.
• Serial data transfer system types:
1. Simplex : data transferred only in one direction, e.g: computer to printer.
2. Half duplex: data transferred in either direction but only one direction at a time.
3. Full duplex: data transferred to both directions simultaneously.
• Mark and Space: In serial communication logic high = mark and logic low = space.
• Baud: Speed of data transfer is specified by BAUD. The rate at which the bits are
transmitted = BAUD = number of bits per second.
• In serial communication data is transferred in two formats:
1. Synchronous format
2. Asynchronous format
 Serial I/O Communication
Synchronous Communication:
• Transmission occurs as continuous stream bits without any indication of character bounderies.
• Used for high speed and bulk data transmission.
• Synchronizing:
I. Both receiver and transmitter use a common clock signal.
II. One or two character (synchronizing characters) are added to the data bytes to be
transferred for the syncing between the systems.
• Error detection:
I. Error detected by checksum technique.
II. Sum of all bytes in the block is transferred and its 2’s complement is transmitted as the
last byte in the block.
III. Receiver adds all the bytes (including the last) and checks if it is zero.
IV. Zero = no error.
 Serial I/O Communication
Asynchronous Communication:
• Used for low speed communication :
110,300,600,1200…… .up to 19.2 k BAUD.
• Framing:
1. No synchronizing clock or timing signal.
2. Adds up bits in a frame.
3. When no character is sent = logic high.
4. Transmission starts with a start bit (0).
5. Followed by character (LSB to MSB)
bits.
6. A parity after character bits.
7. One or two end bits.
• The line remains in logic 1 till the transmission of next character begins with a start bit (logic 0).
• Parity bit:
1. Included in frame to check errors during transmission.
2. Creates 1 or 0, so that number of 1s in the character + parity is always odd in odd parity or even
in even parity.
3. M has even number of 1s, the parity is made 0 for the even parity system.
 Serial I/O Communication
Error detection:
Three ways:
• Parity error: It Informs that the
received byte has wrong parity.
• Framing error: It informs that the
start and stop bit are not at their
places.
• Overrun error: It indicates that a
new byte has been received
before microprocessor takes away
the previous byte.