 VLSI

 Our project is software based.

 The project is divided into sub modules.

1. Cache memory design

2. Block identification

3. Block replacement algorithm

4. Mapping algorithm

5. Finite state machine design for cache controller

 The software is ISE Design Suit from Xilinx version 14.7

 ISE design suite runs on Windows XP/7/Server and Linux operating systems. Additionally, ISE
supports Spartan-6 devices on Windows 10.