TOSHIBA TMP82C55A 1. CMOS PROGRAMMABLE PERIPHERAL INTERFACE TMP82C55AP-2/TMP82C55AM-2 TMP82C55AP-10/TMP82C55AM-10 GENERAL DESCRIPTION AND FEATURES The TMP82C55A (hereinafter referred to as PPI) is a CMOS high Speed programmable input/output interface with three 8-bit V0 ports, 24 1/0 Ports are divided into two groups (Port A and Port B) which are programmable independently by control words provided by MPU. The PPI has three operation modes (Mode 0, 1 and 2) and is copable of versatile interface between MPU and peripheral devices. ‘The TMP82C55A is fabricated using Toshiba’s CMOS Silicon Gate Technology. (1) High Speed Version (TRD =100ns MAX: TMP82C55AP-10/AM-10) (2) Low power 2mA Type. 10zA Max. (@BV, Stand-by) sumption (3) 5V £10% Single power supply (4) 24 programmable I/O ports 5) Three operation modes (Mode 0, Mode 1, Mode 2) (6) Bit set/reset capability (7) Up to 8 output ports of port B and C are capable of driving a darlington transistor (Min,-1.0mA @VOH=1.5V) ture: —40°C to +85°C (9) Available 40pin Standard DIP and SOP (8) Extended operating temper: puss-133TOSHIBA 2 a TMP82C55A PIN CONNECTIONS (TOP VIEW) BLOCK DIAGRAM past? 7 a0 DAs Pag? 39 PAs Pag 38 PAG Pag 4 37 [1PAD ROgs 36 WR qe 35 (GND) vss 7 34 ange 3B Aats 2 Perf 10 u Pce 11 30 Pst 12 29 PCa G13 28 Peat 14 27 PCG 15, 26 fVee(+5¥) Peed 16 25 P87 Pes 17 24 DP BG Pept 18 23 PBs Part 19 22 [1B Pa2f 20 21 fpB3 TNPBICSSAP-ZIAP-10 TMIPB2CSBAM-2/AM-10 soa DyxDo BIDIRECTIONAL DATA > a READ WRITE CONTROL LOGIC Ao —| DATA BUS BUFFER a, —| Reset —— > — —t_ GROUP A [ GaouPs CONTROL CONTROL} NTERNALS-BIT BUS [group a PORT A[PORTC ‘js vo 0 PAy=PAg PC]~PCa soos Wo WO PC3~PCp PBI~PBO Mpugs-134TOSHIBA TMP82C55A PIN NAMES AND PIN FUNCTIONS Number |inputioutput! Pin Name Function ofPin | 3-state ]3:state bidirectional 8-bit data bus. Used for data transfer with Do~Dr 8 | vosstate |IMPU. Also, used for transfer of control words to PPI and status information from PPI | B.state 8-bit/O Port A, Pao~Pa,| 8 | WO3state |Operation mode and input/output configuration are defined by software. Port A contains the output latch buffer and input latch B.state 8-bit /O Port 8 PBo~PBy | 8 | VO3state |Operation mode and inputioutput configuration are defined by {software. Port 8 contains the output latch buffer and input latch. 3.state B-bit VO Porte. Operation mode and inputioutput configuration are defined by pc | stare |50ftware. Port C can be divided into two 4-bit ports by the mode PoomPE? |B | HOS Hate control and also, used as the control signal for Port and Port Bin this case, 3 bits of PCo to PC2 are used for Port B and 5 bits of PC3 to PCy forPort A, ] Chip select input Ss | When this terminal is at “L level, data transfer PPI and MPU a ' mp leecomes possible. At*H" level, the data bus is placed in the high impedance state and control from the processor i ignored. _ Read signal FO 1 Input | When this terminal is at “t” level, data that is input into the port is | transferred to MPU. Write signat wR Input | When this terminal is at “LY level, data or control word is written into PPI from MPU, | Used for selecting Port A, B, C and the contral registers. Normally, 1 2 Input ace Input [this terminal s connected to low order 2 bits ofthe adaress bus, | [When this terminals is at “1H level, all internal registers including Reser 1 | Input |the control register are cleared. in addition, all ports (Port A, B, C) are placed in the input mode (high impedance) of made 0. Vee 1 [Power supply|5v V5 + PPower Supply| GND MPUB5-135TOSHIBA TMPB2C55A 54 FUNCTIONAL DESCRIPTION ‘The PPI is a programmable peripheral interface device with three 8-bit ports (Port A, B and C) and two control registers. 24 V/O ports are divided into 12-bit group A and group B. Group A consists of Port A and high order 4 bits of Port C, while Group B consists of Port B and low order 4 bits of Port C. Each group is independently programmable by control words provided from MPU. There are three operation modes available for the PPI. In mode 0, two 8-bit 1/0 ports and two 4-bit I/O ports can be programmed as input or output ports, respectively. In mode 1, 24 1/0 ports are divided into Group A and Group B. 8 bits of each group are used as input or output port and of the remaining 4 bits, 3 bits are used as handshaking and interrupt control signal. Mode 2 is applicable only to group A and the ports are used as a bidirectional 8-bit data bus and 5-bit control signal. In case of Port C being used as the output, any bits of Port C can be setireset. There are two control registers; one is used for mode setting and the other for bit set/reset control. The control registers can only be written into. Further, when the reset input (RESET) becomes “1”, the control registers are reset and all I/O ports are placed in input mode (high impedance status). Table 5.1_Basic Operation of TMP82C55A, Ai | Ao | | RD | WR Function O70] 0] 0] 1 | Oatabus <— PonaA o}1 {a lo] |oatabus « Ports rv}o} oa} a} 1 | oatabus < Porte o}oj}o fr] o]Pota « databus o}1}o}1]o ]Pore © Databus r}olo)1|o |Poc « Databus 1] 1} 0 | 1 | 0 | Controtregister Data bus x |x | 1] x | x | Datebus = astate x |x | o | 1] 1 | databus = 3-state 1} it fo | a | 1 | inhibition of combination 8 MODE SELECTION ‘There are three basic modes of operation that can be selected by control wards. Mode 0-Basic 10. (Group A, Group B) Mode 1-Strobe input/Strobe output (Group A, Group B) Mode 2-Two-way bus (Port A only) Operation modes for Group A and Group B ean be independently defined by the control word form the MPU. If Dy is set to “1” in writing a control word into the PPI, operation mode is selected, while of Dy="0", the set/reset function for Port Cis selected. MPU8S-136TOSHIBA TMP82C55A 5.1.1 Control word to define operation mode Figure 5.1 shows the control words to define operation mode of the TMP82C55A. Control word 7 Group A Control Group Control br [oe [os [om [os | o [ o | oo Ss Inpuvoutput selection of low order 4 bits of Port ‘0'= Output ‘ainput i _____ inpuvoutput selection of Port 8 ‘dre output "VZinput Mode selection of Group & i D; Mode o Mode 1 Inpuvoutput selection of high gider 4 bits of Port C ‘0’ = Output "Teinput | (____inputioutput selection of Port A ‘of output "Zinput _________stode selection Group A "= Mode 0 tion of mode set flag 1 x x Don’ Figure 5.1. Control Word for Mode Selection MPU85-137TOSHIBA TMP82C55A, 5.1.2 Port C bit set/reset control word Any bit of 8 bits of Port C can be set/reset by Port C bit set/reset control word, Fig. 5.2 shows the Port C bit set/reset, control word. contrat word 6 | Os | Da | D3 | De ale Don't care Do L sitseresersctecton “renee Bit sevreset flag “0” = Active bet Bit selection 0 @ 0 1 1 1 1 Figure 5.2 Control Word for Bit SetReset 5.2 OPERATION MODES 5.2.1 Mode 0 (Basic /0) This functional configuration is used for simple input or output operations. No ‘handshaking’ is required and data is simply written to or read from a specified part. Output data to the ports from MPU are latched out but input data from the ports are not latched. In Mode 0, 24 /O terminals are divided into four groups of Port A (8 bits), Port B (8 bits), high order 4 bits of Port C and low order 4 bits of Port C. Each port can be programmed to be input or output. The configuration of each port are determined according to the contents of Bit 4 (Dg), 3 (Dg), 1 (Dy) and 0 (Do) of the control word for mode selection, ‘The I/O configuration of each port in Mode 0 are shown in Table 5.2. MPU85-138TOSHIBA TMP82C55A, Mode Setting Control Word bona Pore ponte Pore De D3 Dy Do (PCy~PCa) (Pea~PCo) 0 0 0 ° Out Out Out Out 0 0 ° 1 out out Out In o 0 1 0 Out Out Ia Out o a 1 1 out out Ia In ° 1 ° ° Out in out Out, 0 1 ° 1 Out in out In 0 1 1 ° Out im een out ° 1 1 1 out In 0 In 1 0 0 ° In our | out Out 1 0 o 1 Ia our | out f 1 o 1 ° In out in out i 0 1 1 In ut n In 1 1 0 ° In In out out 1 1 0 1 i aan Out In 1 1 1 o |} in | in n | out 1 1 1 ee Lin in jin 5.22 a Figure 5.3 Port Definition in Mode 0 ae Mode 1 (Strobe /0) In Mode 1, input/output of port data is performed in conjunetion with the strobe signals or ‘handshaking’ signals. Port C is used to control Port A or Port B. ‘The basic operatings in Mode 1 are as follows: © Mode 1 can be set for two groups of Group A and Group B. © Each group consist of 8-bit data port and 4-bit control/data port, © The 8-bit data port can be set as input or output port. © The control/data port is used as control or status of the 8-bit data port, When used as the input port in Mode 1: ¢ SFB (Strobe Input) At “0”, input data is loaded in the internal input lateh in the port. In this case, a control signal from MPU is not concerned and data is input from the port any time. This data is not read out on the data bus unless MPU executes an input instruction. © IBF (input Buffer Full F/F Output) When data is loaded in the internal input latch from the port, this output is set tol”. IBF is set (“1”) by STB input being reset and is reset (“0”) by the rising edge of RD input. MPUB5-139TOSHIBA ‘TMP82C55A © INTR Interrupt Request Output) Jsed for the interrupt process of data loaded in the internal input latch. When STE input is at “0” if INTE (INTE flag) in the PPI is in the enabled state (“1”) , IBF is set to “1”, INTR is set to “I” immediately after the rising edge of this STB input ind reset to “0” by the falling edge of RD input. ‘The INTE flag of Group A and Group B are controlled as follows: INTEA-Control by bit set/reset of PCg INTEB-Control by bit set/reset of PC (2) When used as the output port in Mode 1: © OBF (Output Buffer Ful P/F Output) ‘This is a flag which shows that MPU has written data into a specified port. OBF. is set to becomes “0” at the rising edge of WR signal and is set to “1” at the falling edge of ACK (Acknowledge input) signal. © ACK (Acknowledge ut) KCK signal is sont to the PPI as a response from a peripheral device taht received data from the port. © INTR (Interrupt Request Output) When a peripheral device received data from MPU, INTR is set to “1” and the interrupt is requested to MPU. If ACK signal is received when INTE flag is in the enable state, OBF is set to “1” and INTR signal becomes “1” immediately after the rising edge of ACK signal. Further, INTR is reset at the falling edge of WR signal when data is written into the PPI by MPU. The INTE flags of Group A and Group B are controlled as follows: INTEA-Control by bit set/reset of PCs INTEB-Control by bit set/reset of PCa MpUss-140TOSHIBA TMP82C55A, £1 0RTA) ‘CONTROL WORD PAr— Pao fart 0; 0s Dy Ds 05 Or Ds Dp Zl GDh Ea cacy _ Fe tes Tear | pega 2c bebo (O05 (PORTE) conTRoLWoRD 27 6 Ds Ds 03 7 Ds dp CbEGEOCEI i team =| EE we Figure 5.4 Example of Strobe Input in Mode 1 MODE PORTA) 2 aaaraca lees . — Pe Pei~ Py ohv0 t } | MODE 1 PORTS) re re —_c me a Figuire 5.5 Example of Strobe Output in Mode 1 Mpuas-141TOSHIBA TMP82C55A f ] ay ~ Pag be y= Pag wa vs |= OR — Pe STH contro. woro gj BR contro. worD pes He ara 27 O4 0s Da Dr 01 1.05 | pee iMRA D7 Dg Ds De Ds D2 Ds Oy re [om ita Oo CRE ; ; ey~Pe Re 0 co; whe 10 c Pa) ~ Poy [a = | 98) ~ 8p A = Sieur | on we re 3 0 eT Re 0 +o | rch aes 2g RE cg > is eco R= wre vont ASFRORE OUTeUn vont AtRORE RUD PORT a STROBE NOU Pont eisteose Oureun) Figure5.6 Example ofPort A Output, Figure 5.7 Example of Port A input, Port B Input in Mode 1 Port B Output in Mode 1 5.2.3 Mode 2 (Strobed Bidirectional Bus /0) In this mode, Port A is used as 8 bits bidirectional bus for data transfer with a peripheral device. This mode is applicable only to Group A, which consists of an 8-bit, bidirectional bus (Port A 8-bit) and 5-bit control signals (high order 5 bits of Port C). The bidirectional bus (Port A} has both the internal input and output registers. When group A is set in Mode 2, Group B can be set independently. There are 5 control signals as follows when Group A is used in Mode 2. © OBF (Output buifer Full F/F Outp ) When MPU writes data into of Port A, OBF is set to “0” to inform a peripheral device that the PPI is ready to output data. However, Port A is kept in the floating (high impedance) state until ACK input signal is received. © ACK (Acknowledge Input) When ACK signal is set to “0”, the data of the 3-state output buffer of Port A is send out. If ACK signal is at “1”, Port A is in the high impedance state. © STB (Strobe Input) When STB input is set to “0”, the data from peripheral devices are held in the input latch. When the active RD signal is input into the PPI, the latched input data are output on the system data bus (Dz-Dg) Mpuas-142TOSHIBA ‘TMP82C554 © IBF (input Buffer Full F/F Output) When data from peripheral devices are held in the input latch, IBF is set to “I”. © INTR (Interrupt Request Outpu INTR is the output to request the interrupt to MPU and its function is the same as that in Mode 1. There are two interrupt enable flip-flop (INTE), INTE1 corresponds to INTEA in Mode 1 output and INTE2 to INTEA in Mode 1 input. INTE 1-Used to generate INTR signal in conjunction with OBF and ACK signals, and is controlled by PCg bit set/reset. INTE 2-Used to generate INTR signal in conjunction with IBF and STB signals, and is controlled by PC, bit set/reset. Fig. .8 shows the operating example and the timing diagram in Mode 2. Figure 5.8 Operating Example in Mode 2 MPUss-143TOSHIBA Contrl Word in Mode? Dy De Ds. Dy Dz 02 Dy Do Cee De Te De a0 [0 [a0 TC pc,~Pe9 x =Don’t care Ports TMP82C55A = Output Input 0= Output Teinput GroupBMode 0 =Mode0 1=Mode 1 Figure 5.9 Control Word and Configuration in Mode 2 Control Words Ds__De Ds D2) iO p> Intra Pay Pag abe (2707 «Tx Tx Te 71 [a0 Port Porte Control Words Dy Ds _Ds__Dy__Os_ Op iD} _—iD ie ah ceded | | OP PCy -—> OBFR C5 |-— KCKA PCy |+-— STBR Pcs|-—> 1BFA PCp~PCa ferme 1/0 PBy~PBg =P Mode2 v0 Mode Input ea inte paysoay ee 2c} —> OBR a wR— PCE RCKA ocala rei ora PC; |-—~ ACKE Port A- Ports Mode2 U0 ModeO Input Figure 5.10 Examples in Combination with Mode 2 and Other Mode Mpugs-144TOSHIBA ‘TMP82C55A 5.2.4 Precautions f ruse in mode 1 and 2 When used in Mode 1 and 2, bits which are not used as control or status in Port C can be used as follow. Itprogrammed as the input, they are accessed by normal Port C read. If programmed as the output, high order bits of Port C (PC7-PCq) are accessed using the bit set/reset function. As to low order b s of Port C (PC3-PCo), in additions to access by the bit set/reset function, only 3 bits can be accessed by normal writing. 5.3. READING PORT C STATUS When Port C is used as the control port, that is, when Port C is used in Mode 1 or Mode 2, the status information of the cont operation of Port C. word can be read out by a normal read Table 5.2 Status Word Format of Port C Mode an br | oe | os | om | os | m | o Dg Mode 1 Input | vo | wo | BFA irra | ites | are | iNTRB Mode 1output | OBR | wwieA | 170 | 170 | wna | wreo | Gore | wae Mode 2 [opex | wrer | wea | inrez | wana | ay Groupe Mode MPU8S-145TOSHIBA TMP82C55A 6. ELECTRICAL CHARACTERISTICS 6.1 ABSOLUTE MAXIMUM RATINGS Vee Supply Voltage -05t070 | Vv Po. Power Dissipation 250 | mw 6.2 DC ELECTRICAL CHARACTERISTICS TA= -40T to +85, Vcc =5V + 10%, Vs: Vou Output Low Voltage | Iq, = 2.5mA. - - 0.45 v ho (High Impedance State) 05 Vours Vec a BA oar |Current Rexr= 11k aa a a | Vcc-0.2V | Note: Applied for optional 8 VO terminals in Port B and Port C. MPUB5-146TOSHIBA TMPB2CS5A 63 AC ELECTRICAL CHARACTREISTICS TAz - 400 to +850, Voc =5V#10%, Veg =0V svwo. PARAMETER AO ANE ROO AM ey MIN. [MAX MIN, [ MAX. tua [Addresssecup ume for RB fan of- | of -| om ‘wa [Address had time for RD rise of - | of - | tee [RO pulse width wo — | 150] - | as to [Delay rom RD falto decided data output = [40] — | 100] ns ‘or __ [Time from RD rise to data bus floating o| «| 0| 40] ns uy __ Time rom RD or Wik se tonext RD or WR fall 200 | — [| 150] — | os Taw [Adres setup time for WR fal of - | of - [os ‘wa __ [Address holding time for WA rae Se a aw [Wi pulse width ol | vo] — | as [ow [Bus data setup time for WR rise wo] - | ro] - | ms ‘wo | us data holding time for WA rise of - | of - las ‘we [Delay rom WR rae to decided data output = | 3s0[ = [350 os tx [Portdata setup time forD tau of - | of -}o Twn [Pore data holding time for RO rise =| of = [as tax [ACK pulse wiath 300| = [300] = | as ‘sr__[STBpuise wisth aso! - | asof — | as ‘es__[Poridata setup ume for STB se of - | e| - |v ‘on __[Porkdata holding time for STB nse wo] — | 150, - | os tao _ [Delay rom ACK falto decided data output = [300 [= | 300 ns reo _ [Tite fom ROR ise upto wor Por A im Moge 2] a5 a56] a0] aso| os {wos _[Delay rom WR ise to OOF fal = [300 [| =| 300] as ‘os | Delay rom ACK fall to GBF rise = | 350] — | 350] ns ‘se | Delay from STB fal to 1BF rise = | x00} = | 300] ns ths [Delay rom RD fal to TBF rise = | 300] = [300] ns [ tar [Delay from RO fall toinTa fa = [a0 =] a00 | ns tsit__[Delay rom ACK rise to NTR se = | 300[ — | 300] ms ‘ar [Delay from ACK rise to INTR rise = |-350[ = | 350[ ns twat [Delay from WR se to NTR = [aso] = | 450] ns Note: 1. When the power supply is turned ON, reset pulse duration must be active for atleast 500° 2, AC Measuring Point InputVoltage Vuc=2.4V, Vi Output Voliage Vou CL=150pF. 45V 2V,Vou=0.8V MPUB5-147TOSHIBA TMP82C55A 6.4 CAPACITANCE TA#25C, Vec=Vss=0V SYMBOL re testconomion | win. | tye, | max.) unit Cw input Capacitance | feaiMHe —[- | «© | Cour [Outout Capacitance | (*) = [= | 2 | (*): All terminals except that to be measured should be earthed. Mpugs-148TOSHIBA TMP82C55A 7. TIMING DIAGRAM MODE 9 INPUT OPERATION ‘to —>] ‘ a our > we — MODE 1 INPUT OPEARATION tes a ton ay wneur post ——h Bata hr | v8 | ior Jets Jota INTR r— \ eter et Figure 7.1 Timing Diagram MPUss-149TOSHIBA TMP82C55A WR NTR Pom DATA nF ACK PERIPHERAL BUS se ®D MODE 1 GUTPUT OPERATION |] tw —o} a betwirey ro TF MODE 2 BIBIRECTION OPERATION be ww wn tn, Figure 7.2 Timing Diagram MPU8S-150TOSHIBA TMP82C55A 8. PACKAGE DIMENSION 8.1 PLASTIC PACKGE DIP40-P-600 Unit: mm 2 507202 2B Note: Hach lead pitch is 2.54mm, and all the leads are located witehin +£0.25mm from their theoretical positions with respect to No.l and No.4 leads. MpUuss-151TOSHIBA TMP82C55A_ 8.2. 40PIN SMALL OUTLINE PACKAGE SSOP40-P-450 Unit : mm fs) (450mi |) 1asrye, | 5202. [uastye o.wsofaago2 2 OMAK os e2 rests Mpuas-152TOSHIBA TMP8255A aa PROGRAMMABLE PERIPHERAL INTERFACE TMP825SAP-5 GENERAL DESCRIPTION AND FEATURES ‘The TMP8255A (hereinafter referred to as PPI) is a high Speed programmable inputfoutput interface with three 8-bit /O ports. 24 1/0 ports are divided into two groups (Port A and Port B) which are programmable independently by control words provided by MPU. The PPI has three operation modes (Mode 0, 1 and 2) and is cap: versatile interface between MPU and peripheral devices. a (2) (3) 4) avi ‘Single power supply 24 programmable 1/0 ports ‘Three operation modes (Mode 0, Mode 1, Mode 2) Bit set/reset capability PIN CONNECTIONS (TOP VIEW) Pas Pad PA Pao! ROG ce (GND) vss zz | C Pcp 10 Pci 11 Pcs PCa PC Pe; PCa PCs PB PBy PBs 2 a 4 5 6 7 3 «0 beva 39 bens bone 37 pPAy 36 DWR 35 RESET 34 1p 33 DOr 32 bO2 31: 30 104 29 Dds 28 ds 27 1D; 26 1Vec(+5V) 25 DPB, 24 PBs 23 DPBS 19 22 fas 20 21 Pes TMPR255AP-5 of Mpuss-153TOSHIBA TMP8255A 3. BLOCK DIAGRAM D7~Do it BIDIRECTIONAL DATA —_ WR —< ss READ WRITE CONTROL LOsiC Ag ——+! DATA BUS BUFFER a — aeser ROUPA GROUPS CONTROL eSntRot NTERWALS oTTaUS GROUP GROUPE porTAlpoRTe] [PORT [POATS 7 1% me 6 PA7~PAg PCy~PCq — PCa~PCo PB7~PBo ‘oxoen9 MPUBS-154TOSHIBA TMP8255A, 4. PIN NAMES AND PIN FUNCTIONS Number [Input/Output | : Pinweme | Str [state | Function ro _|3state bidirectional 8-bit data bus. Do~D7 8 aatare [Used for data transfer with MPU. Also, used for transfer of control words to PPI and status information from PPI B.state 8-bit VO Port A. pay~Pag| 8 Operation mode and inputioutput configuration are defined by software. Port A contains the output latch buffer and input latch, fo [state B-bit VO Port B PBy~PB | 8 g.stare [Operation mode and input/output configuration are defined by I © _|software. Port B contains the output latch buffer and input latch, Bostate 6-bit VO Port C Operation mode and inputioutput configuration are defined by _ | software. Port C can be divided into two 4-bit ports by the made ote control and also, used as the control signal for Port A and Port 8. In | this case, 3 bits of PCp to PC? are used for Port B and S bits of PC3 to I PC? for Port A, Chip setect input. x When this terminal is at "L" level, data transfer PPI and MPU i 7 'nPut | becomes possible. At "H’ level, the data bus is placed in the high [impedance state and control from the processor is ignored. = | Read signal 4 Input | When this terminal is at "L" level, data that is input into the port is transferred to MPU, write signal wr 1 Input | When this terminal is at "L” level, deta or control word is written nto PPI from MPU, 1 2 Input When this terminal isat Used for selecting Port A, B, C and the control reg) this terminalis connected to low order 2 bits of the address bus. ers. Nurmally, evel, all internal registers including the RESET 1 Input | control register are cleared. In addition, all ports (Part A, B, ©) are placed in the input mode (nigh impedance) of mode 0. Power Vee 1 Sona [Y Power Vs 1 GND S Supply MPUs5-155TOSHIBA TMP8255A 5. 5a FUNCTIONAL DESCRIPTION ‘The PPI is a programmable peripheral interface with three 8-bit ports (Port A, B and ©) and two control registers. 24 1/0 ports are divided into 12-bit group A and group B. Group A consists of Port A and high order 4 bits of Port C, while Group B consists of Port B and low order 4 bits of Port C. Each group is independently programmable by control words provided from MPU. There are three operation modes available for the PPI. In mode 0, two 8-bit 1/0 ports and two 4-bit 10 ports can be programmed as input or output ports, respectively. In mode 1, 24 I/O ports are divided into Group A and Group B. 8 bits of each group are used as input or output port and of the remaining 4 bits, 3 bits are used as handshaking and interrupt control signal. Mode 2 is applicable only to group A and the ports are used as a bidirectional 8-bit data bus and 5-bit control signal. In case of Port C being used as the output, any bits of Port C can be set/reset. There are two control registers; one is used for mode setting and the other for bit set/reset control. The control registers can only be written into. Further, when the reset input (RESET) becomes "1", the control registers are reset and all 1/0 ports are placed in input mode (high impedance status) Table 5.1_ Basic Operation of TMP8255A Ar] Ao] | RO WR Function O70] 0) 0] 1 | databus —< Porta t}holo | Databus < Porte oj}o}o} Databus © Porc o}o]}o]1) 0 | Porta « Ddatabus 0} 1]0}1 | 0 | Pots < Databus t}o]o]} 1] 0] Porc © dDatabus 1] 1 | 0] 1 | o | Controt register — Data bus x |x | 1 | x | x | Datebus Bstate x |x }a] 1 | 1 | oatabus Bstate vito | o | 1 | inhibition of combination MODE SELECTION ‘There are three basic modes of operation that can be selected by control words. Mode 0-Basie 1/0 (Group A, Group B) Mode 1-Strobe input/Strobe output (Group A, Group B) Mode 2-Two-way bus (Port A only) Operation modes for Group A and Group B can be independently defined by the control word from the MPU. If D7 is set to "1" in writing a control word into the PPI, on operation mode is selected, while of D7="0", the set/reset function for Port C is selected MPU85-156TOSHIBA TMP8255A 5.1.1 Control word to define operation mode Figure 5.1 shows the control words to define operation mode of the TMP8255A, Control Word Group A condtol Group 8 Control (27 [96 [os [os [o; [2 [To Too L Inpuvoutput selection of iow orde: dbits of Portc "0! = Output Y's input Inputfoutput selection of Ports. 0 ” Output Input | | | - ——— Mode selection of Group 8 | "0! = Mode O | 1! =Made 1 Inpuvioutput selection of high order 4bits of Port C Port a —— Mode Selection Group A ‘d' =Mode 0 p05 G9=Hodeo esignation of mode st flag SheMode 2 x: Don’teate Figure 5.1. Control Word for Mode Selection MPU8S-157TOSHIBA TMP8255A 5.1.2 Port C bit setireset control word Any bit of 8 bits of Port C can be set/reset by Port C bit set/reset control word. Figure 5.2 shows the Port C bit sot/reset control word. Control Mord Dr | os | 0s | d« | os [ 02 | 0; | de L axsenest secon Bit setireset flag “0 =Active Bit selection Figure 5.2 Control Word for Bit Set/Reset 5.2 OPERATION MODES 5.2.1 Mode 0 (Basic /0) ‘This functional configuration is used for simple input or output operations. No ‘handshaking’ is required and data is simply written to or read from a specified part. Output data to the ports from MPU are latched out but input data from the ports are not latched. In Mode 0, 24 1/0 ports are divided into four groups of Port A (8 BITS), Port B (8 bits), high order 4 bits of Port C and low order 4 bits of Port C. Each port can be programmed to be input or output. ‘The configuration of eack port are determined according to the contents of Bit 4 (Dg), 3 (Dg), 1 (Dy) and 0 (Do) of the control word for made selection. ‘The 1/0 configuration of each port in Mode 0 are shown in Table 5.2. MPUg5-158TOSHIBA TMP6255A Node Setting Control Word Pore Porte Be [os [| oe] | ercr~rcn | PS | ercs~Pco 3 ° ° ° out out Out ° o 0 1 out out te o 0 1 o | out | in out ° 0 1] 4 out in in o | 4 o | 6 to ou | out o | 4 o | 4 tn or | on ° 1 1 o tn in| out ° 1 1 1 to to in 1 0 | o ° out out out 1 ° ° 1 out out tn 1 ° 1 o out tn out 1 ° 1 1 | out bo to 1 1 ° ° in out out 1 1 o | 4 in | Out in 1 1 1 | 0 in in out 1 1 1 fa n im Figure 5.3 Port definition in Mode 0 5.2.2 Mode 1 (Strobe 0) In Mode 1, input/output of port data is performed in conjunction with the strobe signals or ‘handshaking’ signals. Port C is used to control Port A or Port B. ‘The basic operatings in Mode 1 are as follows: Mode 1 can be set for two groups of Group A and Group B. Each group consist of 8-bit data port and 4-bit control/data port. ‘The 8-bit data port can be set as input or output port. The control/data port is used as control or status of the 8-bit data port. (1) When used as the input port in Mode t STB (Strobe Input) ALO! ", input data is loaded in the internal input latch in the port. In this case, a control signal from MPU is not concerned and data is input from the port any time. This data is not read o input instruction. mn the data bus unless MPU executes an IBF (Input Buffer Full F/F Output) When data is loaded in the internal input latch from the port, this output is set, to"1". IBF is set ("1") by STB input being reset and is reset ("0") by the rising edge of RD input. MPU85-159TOSHIBA ‘TMP8255A © INTR (Interrupt Request Output) Used for the interrupt process of data loaded in the internal input latch. When STB input is at "0" if INTE (INTE flag) in the PPI is in the enabled state ("1") , IBF is set to "1". INTRis set to "1" immediately after the rising edge of this STB input reset to "0" by the falling edge of KD input. ‘The INTE flags of Group A and Group B are controlled as follows: INTEA-Control by bit setireset of PCy INTEB.Control by bit set/reset of PC2 (2) When used as the output port in Mode 1 © DBF (Output Buffer Full F/F Output) ‘This is a flag which shows that MPU has written data into. specified port. OBF is set to becomes "0" at the rising edge of WR signal and is set to "I" at the falling edge of ACK (Acknowledge input) signal * KCK (Acknowledge Input) ‘ACK signal is sent to the PPI as a response from a peripheral devi received data from the port. © INTR (Interrupt Request Output) When a peripheral device received data from MPU, INTR is set to "1" and the interrupt is requested to MPU. If ACK signal is received when INTE flag is in the enable state, OBF is set to "1" and INTR signal becomes "1" immediately afler the rising edge of ACK signal. Further, INTR is reset at the falling edge of WE signal when data is written into the PPI by MPU. ‘The INTE flags of Group A and Group B NTEA-Control by bit set/reset of PCs INTEB.-Control by bit setireset of PC e controlled as follows: MPU8S-160TOSHIBA TMP8255A, MODE 1 PoRT A conTROLWoRD Clete Tel TT] = bea pao? Avo 5 CONTROLWORO | Dy De Ds Ds Ds Dy Di Oy Th sree > iNTaa conTROLWoRD Pag fm’ Dy Dg Ds Ds Ds 2 Dr Dy conTROL WORD Dy De Os Os 03 D2 Or Oy (kee [epi] oT] Figure 5.5 Example of Strobe Output in Mode 1 MPU85-161TOSHIBA TMP8255A, a= Pag Be is co Py > OR ro 519A contmoLworo P| RR conrRoLWwoRD i+ tora Dy De Os De Ds Dy Ds Op peyfm inten Br Ds Os Ds Ds Dr Dr Dp GToT To [oft Ti Tx] La ERED Tof jot] Paresh iro ore Po; ~P09 fab ree O= ovteur es o= oureut veinpur RO Py be ~sTEB tein Wh Pc, > F8 cg > wa b= nvnee PORT A (stROBE OUTPUT) PORT A STROBE INPUT PORT (STROBE INPUT) PORTS (STROBE QUI2UT Figure 5.6 Example of Port A output, Figure 5.7 Example of Port Ainput, Port B Input in Mode 1 Port 8 Output in Mode 1 5.2.3 Mode 2 (Strobed Bidirectional Bus 1/0) In this mode, Port A is used as 8 bits bidirectional bus for data transfer with a peripheral device. This mode is applicable only to Group A, which consists of an 8-bit bidirectional bus (Port A 8-bit) and 5-bit control signals (high order 5 bits of Port C). The bidirectional bus (Port A) has both the internal input and output registers. When group A is set in Mode 2, Group B can be set independently. These are 5 control signals as follows when Group A is used in Mode 2. ©) OBF (Output buffer Full F/F Output) When MPU writes data into of Port A, OBF is set to "0" to inform a peripheral device that the PPI is ready to output data. However, Port A is dept in the floating (high impedance) state until ACK input signal is received. © ACK (Acknowledge Input) When ACK signal is set to "0", the data of the 3-state output bufler of Port A is send out. If ACK signal is at "1", Port A is in the high impedance state. © STB (Strobe Input) When STB input is set to "0", the data from peripheral devices are held in the input latch, When the active RD signal is input into the PPI, the latched input Gata are output on the system data bus (D7-Dp) MPU85-162TOSHIBA TMP8255A ¢ IBF (input Buffer Full F/F Output) When data from peripheral devices are held in the input latch, IBF is set to "1 © INTR Unterrupt Request Output) INTR is the output to request the interrupt to MPU and its function is the same as that in Mode 1. There are two interrupt enable flip-flop (INTE), INTE1 corresponds to INTEA in Mode I output and INTE2 to INTEA in Mode 1 input. INTE 1-Used to generate INTR signal in conjunction with OBF and ACK signals, and is controlled by PC bit set/reset. INTE 2-Used to generate IN'TR signal in conjunction with IBF and STB signals, and is controlled by PC, bit set/reset. Figure 5.8 shows the operating example and the timing diagram in Mode 2 | ves~tey fed 0 Figure 5.8 Operating example in Mode 2 MPU85-163TOSHIBA ‘TMP8255A Control Word in Mode 2 Dy De Ds De D202 Dy 1.4 [x x | x [10 [1 | 0 x =Don't care Group 8 mode ‘d= Output 1 =Input O= Output, Y=Input 0=Modeo = Mode 1 Figure 5.9 Control Word and Configuration in Mode 2 Contro! Words Dy__Ds__Ds__De_—Ds_—Dy_D__—OO ata [x [x Tx Te Ts Ti PCa PAy~PAg PCr js INTRA, 8 | ouFe Pc2~PCo Output Input 5 —+| wi —| Pcs, PCa Pcs, PCa~PCo PB)~PBo, RCRA |-— sea — IgFA 3 ee 1/0 & Port A-Mode2 v0 Port B - Mode Ong. ut Control Words Dy Dg Ds Dy D3 Bp ata [x [xx Tito x D+ wa —-| Port A-Mode2v0 Port B-Mode 1 Output <— 318A |— BFA [> oars | ACKB [— tre Figure 5.10 Example in Combination with Mode 2 and Other Mode MPUBS-164TOSHIBA ‘TMP8255A 5.2.4 Pecautions for use in Mode 1 and 2 ‘When used in Mode 1 and 2, bits which are not used as control or status in Port C can be used as follows. Ifprogrammed as the input, they are acce: If Programmed as the output, high order bits of Port C (P7-PC,) are accessed using the bit set/reset function. As to low order bits of Port C (PC-PCo), in additions ot access by the bit setireset function, 3 bits only can be accessed by normal writing. 5.3 READING PORT C STATUS When Port C is used as the control port, that is, when Port C is used in Mode 1 or Mode 2, the status i operation of Port C. ‘mation of the control word can be read out by a normal read Table 5.2. Status Word Format of Port C datamode | or | oe | os | o% | o | o | mo | Do Mode 1Output | OBFR | wren | 10 | vo | inten | inTee [oar | inne Mode 2 wvrer | ora [onrea | wea | By Groupe Mode MPU85-165TOSHIBA ‘TMP8255A 6. ELECTRICAL CHARACTERISTICS 6.1 ABSOLUTE MAXIMUM RATINGS Syed rem fang [uni ec | Supply vorage Zoe |v vn | love Votage cosevee +70 |v ro [Power Biipaion w SOLDER | soisering Temperature ia 260 = Tore __| Strobe Temperature west | © Torn [operating Temperature ow+7 [© 6.2 DC ELECTRICAL CHARACTERISTICS TAs 0°C to 70°C, Vec = 5V 5%, Vss=0V s¥MB0L re restconomon | san. | 7. [max | UN vi [Input tow votage -os| - Jos | v in [input igh votage | a|- [ve] v : + + Oxtputiow Vakage (8) ~ [= fea |v Vou a =| = los |v Vow [OutputHigh votage (03) 2 ~ [Tv a (PER) 2403 sects Anco We input Leak Current -~f- 210) pA + Ousput sak Cent coe (High Impedance State) cat aleas + (Note ®)| Dartington Drive Curren eae 10] = | 40) mo loar eee cena * Rexy = 7500 ° ee a tcc [operxngsuppivcurens — |aeietimes | TV 30 | ma Note: Applied for optional 8 VO terminals ia Port B and Port C. MPUB5-166TOSHIBA TMP8255A 6.4 AC ELECTRICAL CHARACTREISTICS TA=0°C to 70°C, VCC = 5V #5%, VSS = 0V SYMBOL PARAMETER Pe SAP unr in, [wax tak [Address set-up time for RD fall ory =e ee tha ‘Address hold time for RO rise o[ - [ms tee RD pulse width 300 | = | ns ta Delay from RD fall to decided data output =| 200 [ns oF Time from RO rise to data bus foating wo [ 100 | 1s tw Time from RO o- WA rise to next RD or WR fall 0 | - [as taw [Address setup time for WR fall o[ - [= twa __| Address holding time for WR rise 20 | - | os tww [Wi pulse width 300 | = [1s tow __|Busdata setup time for WR rise roo | — | ns two | Busdata holding time for WR rise 30 | — | ns twa __| Delay from Wi rise to decided data output =| 350 [ns tn Port data set-up time for RD fall of - [om th Port data holding time for ROrise of -|[o- tak ACK pulse width 300 | - | as sr STS pulse width soo | — [as tes Port data set-up time for STB rise of - [= te Port data holding time for STB rise wo | - | os ta0 Delay from ACK fal to decided data output =| 300 | ns ko Time from ACK rise up to port (Port A in Mode2) ftoating 20 | 250 | ns ‘twos [Delay from WR rise to O8F fall = [650 [ns taos___ [Delay from ACK fali to OFF rise =| 350 [as ts Delay from 378 fall to IBF rise = | 300 [as ‘th Delay from RO fell to IBF rise = | 300 [as tat Delay from RD fal to INTR fall =| 400 | ns ‘sit Delay from ACK rise t0 INTR rise =| 300 [os tan Delay from ACK rise to INTR rise =| 350 [as twit ___ | Delay from WR rise to INTR fall = [450 [ns Note: 1. When the power supply is turned ON, reset pulse duration must be active for at east 500 ns or more. 2. ACMeasuring Point InputVoltage Vi Output Voltage Vou CL=150pF. 20V) OV. Vip=0.8V Vou=0.8¥ ‘MPU85-167TOSHIBA 6.4 CAPACITANCE TA=25°C, Vec=V55=0V ‘TMP8255A syMBoL mem conpirion | min, | rye, | max. | UNIT cin Input Capacitance Yom iMine = | - | 0 | oF Cu0 VO Capacitance © = | = [2 | Ali terminals except that ta be measured should he earthed. MpUs5-168TOSHIBA TMP8255A, 7. TIMING DIAGRAM MODE INPUT OPERATION j= tin | INPUT a fe tar —>| Gan Ao x Dy~Dp = MODE ‘OUTPUT OPERATION wr _— a f—— ta ——-} twa, Ay, Ao x x oureut [ome ems MODE 1 INPUT OPERATION gp Input PoRT DATA 318 8 iF ls [etna INTR — + tera 9 tee —+, RD : Figure 7.1. Timing diagram MPUaS-169TOSHIBA TMP8255A MODE 1 (OUTPUT OPERATION [— tww wr btw b-twoe+ ar 7 el urpur {¥—_______| PORT DATA | ee aoe ORF or aeeemeeeeeeee ee eeeemeeereees — A MODE 2 BIDIRECTION OPERATION PERIPHERAL BUS sre Figure 7.2. Timing diagram ‘MpU85-170TOSHIBA ‘TMP8255A 8. PACKAGE DIMENSION 8.1 PLASTIC PACKGE DIP40-P-600 Unit: mm Yy } 3.4202 Each lead pitch is 254mm, and all the leads are located within +0.25mm from their Note theoretical positions with respect to No.1 and No.40 leads. MPU85-171