STTP on Design & Development of System on chip using Low Power VLSI

Cadence Tutorial: Schematic Entry and Circuit Simulation of a

CMOS Inverter

Introduction
This tutorial describes the steps involved in the design and simulation of a CMOS inverter using
the Cadence Virtuoso Schematic Editor and Spectre Circuit Simulator. GPDK 0.18um CMOS
process technology kit is used. LMB, MMB and RMB refer to left, middle and right mouse
buttons. The LMB is used for selecting and positioning objects and making selections in dialog
boxes in Cadence applications. The MMB brings up pop-up menus depending on the context.

The basic steps you will go through are: 1) create a library where your design files will reside; 2)
enter a schematic using the Virtuoso Schematic Editor; 3) run circuit simulation with the
Virtuoso Spectre Circuit Simulator. These steps are all done through the use of the Cadence
application.

The Command Interpreter Window (CIW) is the first window that appears. From the popup
menu, choose
Tools > Library Manager
The Library Manager window pops up and you will see three columns: Library, Cell, and View.
A library is a container for cells. Libraries typically contain multiple cells and cells often have
multiple views. A cell is the basic design component. For example, in this tutorial you will create
an inverter cell with two views: schematic and symbol. Libraries containing user-defined cells
are called design libraries whereas libraries containing technology-specific components (e.g.
transistors for the gpdk 0.18um technology) are called reference libraries.

Create a new design library by choosing

File > New > Library
In the dialog window, type in Tutorial as the name and click OK. In the new dialog window
select Don’t need a techfile and click OK. Next, click LMB on tutorial and you can see the name
appears in the Library field. You can create a new cell by choosing
File > New > Cell View
In the dialog box, type inverter for the Cell Name and set Tool to Composer-Schematic, then
click OK. This will automatically set the view to schematic. A new window will open called
Virtuoso Schematic Editing. Later in the semester, you can create a new library for each of your
homework assignments or projects.

Schematic Entry
First, expand the schematic window to its maximum size by clicking on the square box in the
upper right corner. The pull-down menus at the top of this window and the icon bar on the left
provide two ways to complete various editing tasks. For example, you can add an instance by
choosing
Add > Instance
or by clicking on the icon bar entry that looks like an IC (the Instance entry label will appear
when the cursor is over this entry). Bindkeys are shortcuts for common editing tasks. Notice the
letter "i" next to the Add > Instance menu entry. This indicates that you can activate the add
instance task by typing the "i" key while the cursor is in the main edit window (the window with
the black background).
STTP on Design & Development of System on chip using Low Power VLSI

After activating the add instance task in one of these ways, click Browse in the ensuing dialog
box. Choose gpdk180 for the library, nmos for the cell in this library and the symbol view. Move
your cursor over the main edit window and you will see a ghost image of the nmos transistor.
Click with the LMB to place the instance. Type the ESC key to end the add instance task. Repeat
these steps, adding a pmos symbol to the schematic.
The transistors and other technology-specific components used in your designs will always be
selected from the gpdk180 library. Generic symbols like vdd, gnd and voltage sources will be
selected from the analogLib library.

Add the remaining symbols to the inverter schematic. Add a vdc, vsin, two vdd, three gnd
symbols and a cap symbol with its default value from analogLib. Complete the schematic as
shown in Figure 1. You don’t have to be concerned about the relative placements of the
instances.

Figure 1. Inverter Schematic

You can select an instance by clicking on it with the LMB. You can then move it
with Edit > Move
or simply by dragging the instance while holding down the LMB. Instance pins are connected
together by wires. The connections can either be explicit, in which the wire extends to each pin,
or by name, in which pins connect to two graphically separate wires bearing the same name. To
make an explicit connection, first type the bindkey "w" or click the LMB on the Wire (narrow)
icon in the icon bar. Click the LMB at the desired starting point in the schematic window and
move the mouse to the destination and double click the LMB at the end point (single click if the
endpoint is another wire or pin). You can draw as many different wires as you need until the task
is cancelled by pressing the Esc key. If you wish to connect by name, give the same wire name to
two separate wires.
STTP on Design & Development of System on chip using Low Power VLSI

To name a wire, choose

Add > Wire Name
Fill in the wire name in the dialog box then move the cursor over the wire to be named. Note that
the schematic in Figure 1 uses only explicit connections. Do not forget to connect the bulk of the
nmos to gnd and the bulk of the pmos to vdd.

Next, add input and output pins to the schematic. Type the bindkey "p" or click the LMB on the
pin icon in the icon bar. In the dialog box, give a pin name and specify the direction of the pin
(input, output, or input/output). Then move your cursor on the schematic window to place the
pin.

The next step is to edit the properties of various components. First select the instance, then type
the bindkey "q" or click the LMB on the Property icon in the icon bar. In the lower part of the
dialog box that appears, you will see the CDF parameter fields. Different parameters mean
different things to downstream tools and you typically will only be interested in a few of the
parameters. Edit the parameter fields of interest and click Apply. You can use variables as well
as constants for parameters. For example, for the vsin voltage source at the input, type vdc for
the DC voltage parameter. Later in analog simulation, you will sweep this variable. Also, for
vsin set AC magnitude = 1, this normalizes the vout/vin small signal transfer function so that
only vout is needed when plotting the frequency response. Finally, set Amplitude = 5m (10mV
peak to peak) and Frequency = 1M. Click on Apply and OK. Now, set the DC voltage parameter
for the source between vdd and gnd to 1.5. Change the widths of the nmos and pmos transistors
to 400n and 1u, respectively. Change the cap capacitance to 100f. Your schematic should now
look like Figure 1.

The final step in the schematic capture is to Check and Save. Click the LMB on the Check and
Save icon in the icon bar. Look in the CIW for errors or warnings.

Circuit Simulation
You will use the Spectre circuit simulator via the Cadence Analog Environment. Enter the
Analog Environment as follows:
Tools > Analog Environment
You can also invoke this from the CIW by choosing:
Tools > Analog Environment > Simulation
If you open the simulator from CIW, you have to load the design. You can do this by choosing:
Setup > Design
In the dialog box, choose the library and cell you want to simulate.
Before running any simulations, the simulator needs to know about the process and the device
models.

Choose:
Setup > Model Libraries
Click on Browse and add these file
Next, load and edit the design variable vdc. Choose:
Variables > Copy From Cellview
STTP on Design & Development of System on chip using Low Power VLSI

You will see the design variable appear in the window. Click the LMB on the Edit Variables icon
in the icon bar. Click on vdc, set the value to 0 and click OK. Note that you can overwrite this
value later when you run the simulation. But you must always set the variables to some default
values before you run the simulation. The next step is to select the analysis type. Click the LMB
on the Choose Analysis icon in the icon bar. In the dialog box, choose dc analysis. DC analysis
simulates a circuit’s steady-state (i.e. time-independent) behavior. Select Design Variable in the
field of Sweep Variable. Click on the Select Design Variable and choose vdc. In the field of
Sweep range, type 0 for start and 1.5 for stop. For Sweep Type, click and select Linear then
select Step Size and enter 0.005 (i.e. 5mV) in the field of Step Size. Click OK.

To run the simulation, click the LMB on the Netlist and Run icon in the icon bar. A general
information window will pop up along with a simulation log. To show the waveform, choose:
Results > Direct Plot > DC
In the schematic window, click on the vin and vout wires or pins. Press ESC to finish selection.
Figure 2 shows the resulting DC transfer characteristic curve. Next, from the waveform window
click:
Tools > calculator
The calculator can also be brought up by clicking the calculator icon from the tools menu of the
waveform window or from the tools menu of Analog Environment.

Figure 2. Inverter DC transfer characteristics

From the calculator window, click the "swept_dc" tab then the “vs” button and in the schematic
window click on the vout pin.

In general, use “vs”(“is”) for voltage(current) data from a DC sweep analysis, “vdc”(“idc”) for
voltage(current) data from a DC analysis, “vf”(“if”) for voltage(current) data from an AC
analysis and “vt”(“it”) for voltage(current) data from a transient analysis. Now return to the
calculator window and click:
STTP on Design & Development of System on chip using Low Power VLSI

deriv
Now click the “Eval” button on the calculator. To separate the curves, from the waveform
window click:
Axis > Strip
Or click on the Switch Chart Mode icon in the waveform window. You can also overlay curves
by clicking and dragging them onto one another. Click and drag the “VS(“/vout”) curve onto the
VS(“/vin”) curve and you should have a plot similar to the one in figure 3.

Using the Crosshair marker icon, find the value for vdc that corresponds to the maximum
magnitude of the slope. You should get a value of 0.745 V for vdc corresponding to a magnitude
of about 11.20 for the slope of the curve. This is the maximum gain of the circuit.

Figure 3. Inverter DC transfer characteristics

Next, run the AC analysis. AC analysis simulates a circuit’s small-signal frequency dependent
behavior. Choose ac analysis in the Choosing Analyses dialog box, and for Sweep Range select
the Start-Stop option. Enter 10 in the start field and 100M in the Stop field. Click OK.

In the Analog Environment window, set the value for vdc to 0.745 and then click the Netlist and
Run icon in the icon bar. Plot the output with:
Results > Direct Plot > AC Magnitude
In your schematic window click vout and then press ESC. Your curve should look like Figure 4.
Using a Crosshair marker, a low frequency magnitude of about 11.19 should be observed. Note
that this is the low-frequency gain of the circuit and agrees with our previous DC analysis.
STTP on Design & Development of System on chip using Low Power VLSI

Figure 4. Inverter AC transfer characteristic

Next, run the transient analysis. Transient analysis simulates a circuit’s behavior over time and is
the closest simulation to real operation. Choose tran analysis in the Choosing Analyses dialog
box, and set the stop time as 5u. Run the simulation by clicking the LMB on the Netlist and Run
icon. You can plot the output with:
Results > Direct Plot > Transient Signal
In your schematic window, first click vin, then vout and then press ESC. Click on the Switch
Axis Mode Icon and your curves should look like Figure 5. Use the Crosshair markers:
Trace>Place> Trace Marker
to help you determine the ratio of the peak-to-peak output voltage and the peak-to-peak input
voltage. A value of about 11.2 should be observed for the gain. Note that this value agrees with
those observed in the previous two simulations.

Operating point characteristics for devices and elements can be viewed as well. In the Analog
Environment window click:
Results > Print > Transient Operating Points

` Figure 5. Transient Analysis of Inverter

STTP on Design & Development of System on chip using Low Power VLSI

In the schematic window select the NMOS device and then select the PMOS device. A window
displaying their respective device parameters and operating points will appear. Locate the
“region” parameter and observe the number to the right of it. This number indicates the region of
operation in which the device is operating. In general a “0” means the device is operating in
cutoff, a “1” indicates triode, a “2” indicates saturation and a “3” indicates the subthreshold
region. From this window use the “gm” and “gds” values of both devices to calculate the
following:
The previous expression is the small signal gain of the circuit and a value around 11.18 should be
calculated. Note that it is in agreement with all previous simulations.
You can save the state of a simulation so that you don’t have to repeat these steps every time you
want to simulate this or a similar circuit. To save the state, choose:
Session > Save State
Click on OK. This will save the state to the default name state1. You will load this state in a later
simulation session.
Plots
You can print waveforms by choosing:
File>Save as Image > snapshot.png
in the waveform window. In the terminal window:
$ lpr snapshot.png
To print schematics choose:
Design > Plot > Submit
in the schematic window. Select the destination printer via Plot Options in the ensuing dialog
box.
Design Hierarchy Using hierarchy effectively is important when creating large designs.
Hierarchy helps to make the design task more manageable by adding levels of abstraction and
reducing the overall complexity of a design. Lowlevel "leaf cells" composed of primitive
transistor instances and wires can be represented by a black box or symbol. This symbol can then
be instantiated in other schematics to represent circuits of greater complexity. The remainder of
this tutorial demonstrates how to generate a symbol, instantiate it and simulate the new circuit.
The resulting design isn’t truly hierarchical but it demonstrates the techniques involved with
creating and simulating hierarchical circuit representations.
Symbol Generation
The schematic you’ve entered to this point has voltage sources on vdd and the input that should
not be present in a leaf cell. Therefore, create a new schematic cell view called cmos _inverter in
your design library. Copy the inverter schematic into it (select all by click/drag with LMB, then
click on the Copy icon), then remove the voltage sources and add new pins as shown in Figure 4.
STTP on Design & Development of System on chip using Low Power VLSI

Save the schematic and choose:

Design > Create Cellview > From Cellview
In the dialog box, make sure that the field of To View Name is symbol and then click OK.
Accept the defaults for the Symbol Generation Options dialog. You can redraw the symbol if you
want by using the icon bar. Check/Save with:
Design > Check and Save
The symbol can be used as a subcircuit in larger designs. The symbol is shown in Figure 5.

Figure 4. cmos inverter schematic

Figure 5. cmos_inverter symbol

Simulation Using a User Defined Symbol

Create a new cell and instantiate the inverter symbol by choosing:
Add > Instance
STTP on Design & Development of System on chip using Low Power VLSI

Click on Browse, choose the tutorial library, the cmos_inverter cell, and the symbol view. Place
this on the schematic. Add vdc , vsin and gnd symbols from the analogLib library. Add a
capacitor from the gpdk180 library to the output of the inverter. To add the capacitor, choose:
Add > Instance
Click on Browse, choose the gpdk180 library, and add an instance of the ncap_inh symbol to the
schematic. Rearrange and connect the symbols so the schematic looks like Figure 6. Click on the
vdc source and then click on the Properties icon. Enter 2.5 for the DC voltage. Set the properties
of the vsin source to AC magnitude = 1, Amplitude = 0.005, Frequency = 1M and set the DC
voltage to the vdc variable. Enter the properties of the ncap_inh and change the RX width to
4.56u.

Figure 6. Schematic using user defined inverter

To simulate the new circuit, choose:
Tools > Analog Environment
You can load the previously saved state, so it is not necessary to re-enter all of the device model
files and simulation commands. Choose:
Session > Load State
Make sure the Library is set to tutorial, the Cell is set to inverter. There should be a saved state
called state1 available. Click OK. Now click on the Netlist and Run icon.
You can view the output of the simulation by following the procedures used earlier in this
tutorial. Your dc, ac and transient plots should like Figure 7.
STTP on Design & Development of System on chip using Low Power VLSI

Figure 7. DC, AC, and transient curves of loaded inverter

STTP on Design & Development of System on chip using Low Power VLSI

Experiment
Aim: Design of Low Power CMOS logic gates using Footed Diode.
STTP on Design & Development of System on chip using Low Power VLSI

In diode-footed domino an NMOS transistor is there in a diode configuration i.e. gate and
drain terminals connected together in series with the evaluation network, as shown in Figure.
A diode connected transistor is exploited in this design in which the leakage flowing
through PDN in evaluation phase causes the voltage drop across the diode transistor. Which
makes the VGS negative and leakage reduces. The performance degradation can be
compromised by the mirror network. By varying the size of mirror, noise immunity can be
made. But when we compare it with standard footless domino this scheme is very slower.
Also the inverse clock increases the capacitive load of the clock driver.

(i)Evaluation phase- in this phase when clock pulse is kept high then the PMOS
transistor M1 is turned off and NMOS transistor is turned on so, the dynamic node
Z discharges through node B and therefore output node became high.

(ii) Precharge phase- in this phase when clock pulse is kept low then PMOS clock
transistor M5 is turned on and dynamic node Z is charged to VDD. The output is still
high because the clock pulse turns off the transistor M2 so, M6 is also off and
therefore output node is not able to discharge. Due to stacking effect power is
compensated.
STTP on Design & Development of System on chip using Low Power VLSI

HDL Designer

AIM: - To study Design Flow of HDL Designer with the help of counter design using
VHDL.

Introduction

This lab introduces the basic design process using FPGA Advantage. After completing
this lab, you will have an understanding of creating a new project, entering a design in
design pad, visualizing it (optional) and simulating & synthesizing the design. The flow
illustrated in this lab is same for VHDL & Verilog. VHDL has been used for this lab.

This lab comprises five primary steps:

1. Create a new project
2. Enter the code in design Pad
3. Visualize the Design and Document it (optional)
4. Simulate the Design
5. Synthesize the design

Following each general instruction for a given procedure, you will find accompanying
step-by-step directions and illustrated figures that provide more detail for performing the
general instruction. If you feel confident about a specific instruction, feel free to skip the
step-by-step directions and move on to the next general instruction in the procedure.

Create a New Project Step 1

Launch the FPGA Advantage - HDL Designer and create a new project.

 Select Start Programs FPGA Advantage 8.1 PP FPGAdv with PP

 Select File New Project, New Project Wizard opens (Figure 1.1). Enter the
following Details and Click Next.

Name of new project : counter

Optional Short Description : 4 bit binary counter with reset &
chip enable
Directory : C:/training/labs/lab1
Name for the default working library : work
Advanced : Unchecked
STTP on Design & Development of System on chip using Low Power VLSI

Figure 1.1: New Project Wizard

 View the Project Summary wizard and Click Next.

Create a New VHDL design in Design Pad using File Creation Wizard.
 After Clicking Next in the New Project Wizard, File Creation Wizard will
appear, Select Create new design Files and Click finish.
 In the Design Content Creation Wizard select VHDL File in Categories and
Combined in the File Types. (Figure 1.2) and click Next.

Figure 1.2: Design Content Creation Wizard

 Enter the below mentioned HDL specification (Figure 1.3) in the wizard and Click
Finish.
Library : work
Entity : counter
Architecture : rtl
STTP on Design & Development of System on chip using Low Power VLSI

File name : counter_rtl

File case : Always lower case
File Format : PC

Figure 1.3: HDL Specification

Now the Design Pad (advanced text editor of HDL Designer) window opens where in you
can enter the HDL code. Note that in the Design Manager window (Main GUI of HDL
Designer) a Counter component has been created under the work library.
Enter the code in Design Pad Step 2

Use the code snippet of Counter function and enter the code in Design Pad.

 The default view of the Design Pad window is shown in Figure 2.1. Note that
library, entity and architecture declaration are present and code browser is
present on the left hand side.

Figure 2.1: Default view of Design Pad

 Enter the below mentioned VHDL code for counter in design pad.
-----------------------------------------------------------------------
library ieee;
STTP on Design & Development of System on chip using Low Power VLSI

use ieee.std_logic_1164.all; use

ieee.std_logic_arith.all; use
ieee.std_logic_unsigned.all;

entity counter is
port( clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
count : out std_logic_vector(3 downto 0)
);
end entity counter;

architecture rtl of counter is

signal count_int : std_logic_vector(3 downto 0);
begin
counter_func:process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
count_int <= (others=>'0');
else
if (ce = '1') then
count_int <= count_int+1;
end if;
end if;
end if;
end process counter_func;

count <= count_int;

end architecture rtl;
-----------------------------------------------------------------------

 After completing the code entry, save the design by clicking on File Save.

When you save the design, Design Pad automatically performs Syntax Check of the code. If
any syntax violations are found, it displays the message with the line number (Figure 2.2).
Correct the errors if any.

Figure 2.2: Syntax Error Example

STTP on Design & Development of System on chip using Low Power VLSI

 Syntax check can also be performed manually by clicking on Document Check

Syntax (figure 2.3).

Figure 2.3: Check Syntax option

 Completed design entry window is shown in the figure 2.4. Note that code
browser window is showing the list of all ports, declarations and processes in the
design which can be used to quickly browse to required section of the code. Now
Design Pad window can be closed.

Figure 2.4: Completed Design Entry

Visualize the Design & Document it (optional) Step 3

Visualize the counter design as Flow Chart using Visualization.

Visualization feature of HDL designer allows you to create graphical views for your
HDL source code to which you can apply only layout changes and save; visualization
does not allow logical changes, thus enabling you to preserve your source code and at
the same time obtain a graphical documentation of your design. This Feature is can
also be used to easily understand the existing HDL codes.

 In Design manager, right click on Counter design under work library and select
Visualize Code As Flow Chart (Figure 3.1).
STTP on Design & Development of System on chip using Low Power VLSI

Figure 3.1: Invoking Visualization

 This converts the HDL counter design into Flow Chart using Visualization. Figure
3.2.

Figure 3.2: Flow Chart Visualization

 Analyze the flow chart and close the Visualization Window.

Document the Design as HTML.

 In the Design Manager, select the Counter design in the Design Explorer and
click on Document & visualize option in the Shortcut Bar.
 In the Document & Visualize wizard select HTML Export & change
the location to C:/training/labs/lab1/html_export and click ok. Figure
3.3.
STTP on Design & Development of System on chip using Low Power VLSI

Figure 3.3: Document & Visualize wizard

 This exports the design as a HTML page along with Diagram, Information,
Side data and HDL code which eases the documentation. Figure 3.4

Figure 3.4: HTML Documentation

Simulate the Design Step 4

Launch the Modelsim Simulator, using stimulus file simulate and verify the
functionality of the design.
 To simulate the design using ModelSim, select counter component in
the Design Explorer window and click on Simulate button in the
shortcut bar.
 Start ModelSim window appears, click on Browse Cmd File
button and brows to C:/training/sources location and select
counter_stimulus.do file (figure 4.1).
STTP on Design & Development of System on chip using Low Power VLSI

Figure 4.1: ModelSim Invocation

counter_stimulus.do is a pre-created stimulus file for the design. Upcoming labs
will illustrate the process of creating such a stimulus file and other ways of
applying stimulus to the design.
 Click Ok. This will invoke the ModelSim simulator and executes the below
mentioned simulation steps automatically.
1. Create a library by name work
2. Compile the counter design into the library
3. Load the Design in to the simulator
4. Open the Wave window and add all top level signals of the design to wave
window.
5. Apply stimulus specified in the counter_stimulus.do file and run the
simulation
 Simulation result is shown in the Wave window of ModelSim (figure 4.2).
Examine the waveforms and verify that the simulation result is matching the
counter functional description.

Figure 4.2: Simulation result

STTP on Design & Development of System on chip using Low Power VLSI

 After examining the simulation result, stop the simulation by clicking

on Simulate → End Simulation and close the ModelSim Simulator
window.

Synthesize the Design Step 5

Launch the Precision Synthesis tool and synthesize the design targeting Xilinx
Spartan 3E - XC3S500EFG320-4 FPGA.

 To synthesize the design using Precision, select the counter in the Design
Explorer window of HDL Designer and click on the Synthesize button in the
shortcut bar.
 Precision Synthesis Settings window appears, select the below mentioned
options (figure 5.1) and click on OK.

o Technology : Xilinx – SPARTAN3E

o Device : 3S500EFG320
o Speed Grade : -4
o Add IO Pads, Use safe FSM, Retiming, Frontend 2004 : Unchecked
o Design Frequency: 50 MHz
o I/O Constraints : None
o Output Format : EDIF
o Run Options : Compile, Synthesize, Launch Synthesis - Checked
Run Integrated Place and Route – Unchecked
Produce script file for batch run – Unchecked
o Implementation Options : Single Implementation Mode

Figure 5.1: Precision Synthesis settings

STTP on Design & Development of System on chip using Low Power VLSI

 This invokes Precision Synthesis and synthesizes the design. The view of the
synthesized design is shown in the Figure 5.2.



Figure 5.2: Precision Synthesis GUI

 Double click on RTL Schematic to view the RTL view of the design (Figure 5.3).


Figure 5.3: RTL Schematic of the design

 Double click on Technology Schematic to view the netlist generated by the tool
(Figure 5.4).
STTP on Design & Development of System on chip using Low Power VLSI

Figure 5.4: Technology Schematic

 Double Click on Area Report to view the area estimation for the design (figure
5.5) and double click on Timing Report to view the performance estimation for
the design (figure 5.6).


Figure 5.5: Area Estimation

Figure 5.6: Performance Estimation

 Save the Project by clicking on File  Save Project and close the
precision window. This completes the Design Entry, Simulation and
Synthesis of the Design.

Conclusion
In this demonstration, you completed the major stages of the FPGA Design Flow
using FPGA Advantage: creating a project, adding source Code, visualizing &
documenting the design, simulating and synthesizing the design.
STTP on Design & Development of System on chip using Low Power VLSI

EXPERIMENT
AIM: - To implement full adder using VHDL in HDL Designer.

VHDL Code:-

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY full_adder IS
port ( a, b, c : in std_logic;
sum, carry : out std_logic);
END ENTITY full_adder;

ARCHITECTURE rtl OF full_adder IS BEGIN

sum <= a xor b xor c;
carry <= (a and b) or (b and c) or (c and a);
END ARCHITECTURE rtl;

RTL Design:-

Simulation Result:


STTP on Design & Development of System on chip using Low Power VLSI

Semi-Custom-Back-End-Flow
Aim: To study Semi-Custom-Back-End-Flow using Mentor Graphics Tool.

In this lab we will be doing a semi-custom back-end flow using Mentor Graphics Tools.
SemiCustom (Backend) design flow:

1. Floorplanning
2. Placement
3. Routing
4. Physical Verification

1. Floorplanning:
Step1: Invoke Pyxis layout Design tool
csh
source<space><give your cshrc file path >
ic&

Step2: Click New-Verilog Button

STTP on Design & Development of System on chip using Low Power VLSI

Layout cell - cell name < give top level cell name >
Verilog netlist file – Verilog scan inserted gate level netlist
Module name - top module name (counter)
Power – VDD < VSS terminal name >
Ground – GND < GND terminal name >
Process - $ADK/technology/ic/process/tsmc018
Rule - $ADK/technology/ic/process/tsmc018.rules
Library - $ADK/technology/ic/process/tsmc018
Then Press OK

Step3: go to Plan & Place > Floorplaner > Autpfp > OK

STTP on Design & Development of System on chip using Low Power VLSI

2. Placement:
Step4: Auto Placement > StdCell

Step5: Ports

Press OK
STTP on Design & Development of System on chip using Low Power VLSI

3. Routing:

Step6: route > Aroute Setup > option > Advance >

Check following option

Check same net spacing
Fill net gaps
Route power first
Allow all directions for stubs
Center wires on pines
Pack wires

Press OK
STTP on Design & Development of System on chip using Low Power VLSI

Step7: Aroute commands > run

Step8: Right mouse click on layout Edit > add text on ports > OK

Step9: File > exports > GDSII

STTP on Design & Development of System on chip using Low Power VLSI

Now GDSII file Generated

4. Physical Verification:

Step10: For DRC check following option

Tools > Calibre DRC < select option >

Rules > $ADK/technology/ic/process/tsmc018.rules
Inputs > /home/HUSSAIN/SMDP/counter_scan.gds < give GDSII File Path >

Press Run DRC button

STTP on Design & Development of System on chip using Low Power VLSI

Step11: for LVS check first create Verilog gate

level net-list to spice net-list file Open new
terminal. Go to working directory.
cd SMDP < Working directory Name >
Source cshrc File
csh
source /home/software/cshrc/hep.cshrc
v2lvs -v counter_scan.v -o counter.spi –l
/home/software/FOUNDARY/adk3_1/technology/adk.v –s
/home/software/FOUNDARY/adk3_0/technology/adk.spi -sk -s0 GND -s1 VDD
generate spice net-list file <counter.spi>

Now open Calibre LVS tool

Tools > Calibre LVS < select option >
Rules > $ADK/technology/ic/process/tsmc018.rules
Inputs > Layout > /home/HUSSAIN/SMDP/counter_scan.gds < give GDSII File Path >
STTP on Design & Development of System on chip using Low Power VLSI

Inputs > SPICE > /home/HUSSAIN/SMDP/counter_scan.spi

Press Run LVS

STTP on Design & Development of System on chip using Low Power VLSI

Step12: For PEX extraction following option

Tools > Calibre PEX < select option >

Rules > $ADK/technology/ic/process/tsmc018.rules

Inputs > Layout > /home/HUSSAIN/SMDP/counter_scan.gds < give GDSII File Path >

Inputs > SPICE > /home/HUSSAIN/SMDP/counter_scan.spi

Outputs >
Format: - DSPF
File :- <file name>.dspf

Run PEX
STTP on Design & Development of System on chip using Low Power VLSI

dspf file generated for doing post layout simulation

STTP on Design & Development of System on chip using Low Power VLSI

EXPERIMENT

AIM: - To implement clock divider circuit in Mentor Graphics Tool.

VHDL Code:-

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY clock_div_pow2 IS
port (
i_clk : in std_logic;
i_rst : in std_logic;
o_clk_div2 : out std_logic;
o_clk_div4 : out std_logic;
o_clk_div8 : out std_logic;
o_clk_div16 : out std_logic
);
END ENTITY clock_div_pow2;

ARCHITECTURE rtl OF clock_div_pow2 IS

signal clk_divider : unsigned ( 3 downto 0 );

BEGIN

p_clk_divider : process(i_rst, i_clk)

begin
if (i_rst = '0') then
clk_divider <= (others => '0');
elsif (rising_edge(i_clk)) then
clk_divider <= clk_divider + 1;
end if;
end process p_clk_divider;

o_clk_div2 <= clk_divider(0);

o_clk_div4 <= clk_divider(1);
o_clk_div8 <= clk_divider(2);
o_clk_div16 <= clk_divider(3);

END ARCHITECTURE rtl;

STTP on Design & Development of System on chip using Low Power VLSI

RTL Design:-

Flow Chart:-
STTP on Design & Development of System on chip using Low Power VLSI

Simulation Result:-

Layout:-