COMPONENT INTERFACING Memory Interfacing: The memory structure will be simple, if a memory is bought which is of the exact size that is needed. If more memory is needed than that can be bought in a single chip, then several such memory chips are needed to construct the memory of required size. e.g. if 4GB Memory is needed and the single memory chip is available in 2GB then 2 Memory chips are needed. To build a memory that is wider than the one that can bought on a single chip. e.g. A 32-bit-wide memory chip cannot be bought generally, a memory of a given width can easily be constructed (32 bits, 64 bits, etc.) by placing RAMs in parallel. Also LOGIC may be needed to turn the Bus Signals into the appropriate memory signals. So appropriate refresh signals need to be generated. e.g. Most busses won’t send address signals in row and column form.COMPONENT INTERFACING cont’d.... Device Interfacing: Some I/O devices are designed to interface directly to a particular bus, forming glue-less interfaces. But glue logic is required when a device is connected to a bus for which it is not designed. An I/O device typically requires a much smaller range of addresses than a memory, so addresses must be decoded much more accurately. Some additional logic is required to cause the bus to read and write the device's registers.COMPONENT INTERFACING cont’d.... The device has four registers that can be read and written by presenting the register number on the regid pins, asserting R/W as required, and reading or writing the value on the regval pins. To interface to the bus, the bottom two bits of the address are used to refer to registers within the device, and the remaining bits are used to identify the device itselt. The top bits of the address are sent to. a comparator for testing against the device address. The device’s address can be set with switches to allow the address to be easily changed. When the bus address matches the device's, the result is used to enable a transceiver for the data pins. When the transceiver is disabled, the regval pins are disconnected from the data bus. The comparator’s output is also used to modify the R/W signal: The device's R/W pin is given the value (bus R/W + not-equal address), so that when the comparator’s result is not 1, the device’s R/W pin always receives a 1 to avoid inadvertently writing the device registers. A glue logic interface: Below is an interfacing scheme for a simple I/O device UW Data Addioss nw [ Read DL Real Ades) Rega | Reet Rew - Device =F adérew Device franscever Rogeal Rw nwa re Communication Interface |» Foran embedded product, the communication interface can be viewed in wwo | different perspectives; namely; Device/board level communication interface (Onboard Communication Interface) and Product level communication interface (Extemal Communication Interface), * Embedded product is a combination of different types of components (chi (devices) arranged on a printed circuit board (PCB). Serial interfaces liké 12C, SPI, UART, 1-Wire, ete and parallel bus interface are examples of ‘Onboard Communication Interface’.Onboard Communication Interfaces -* Onboard Communication Interface refers to the different | | communication channels/buses for interconnecting _ the _ various integrated circuits and other peripherals within the embedded system, The various interfaces for onboard communication are as follows: i, Inter Integrated Circuit (12C) Bus ii, Serial Peripheral Interface (SPI) Bus ili, Universal Asynchronous Receiver Transmitter (UART)= Inter Integrated Circuit (I2C) Bus «The Inter Integrated Circuit Bus is a synchronous bi-directional half duplex two wire serial interface bus. The 2C bus comprise of two bus lines, namely; Serial Clock-SCL and Serial Data-SDA. * SCL line is responsible for generating synchronization clock pulses and SDA is responsible for transmitting the serial data across devices. Devi s connected to the 12C bus can act as either ‘Master’ device or ‘Slave’ ‘he ‘Master’ device is responsible for controlling the communication by initiating/terminating data transfer, sending data and generating necessary synchronization clock pulses. ‘Slave’ devices wait for the commands from the master and respond upon receiving the commands. ‘Master’ and ‘Slave’ devices can act as cither iransmitter or receiver. I2C supports multi masters on the same bus.Vdd Fe || Master 1 i re | Slave 2 I2C Bus InterfacingExternal Communication Interfaces = The Extemal Communication Interface refers to the different | communication _channels/buses_used_by the embedded system to communicate with the external world. The various interfaces for external communication are as follows i, RS-232 C & RS-485 ii. Us fer Serial Bus (USB) IEE 1394 (Firewire) _/Infrared (IrDA) Bluetooth (BT) . Wi-Fi \. ZigBee neral Packet Radio Service (GPRS)BD RS-232 C & RS-485 | © RS-232C is a legacy, full duplex, wired, asynchronous serial communication interface. RS-232 supports two_different_types_of connectors, namely, DB-9; 9-Pin_connector_and DB-25: 25-Pin connector, RS-232 supports only point-to-point communication and not for multi-drop communication. 485 is the enhanced version of RS-422 and it supports multi-drop communication with up to 32 transmitting devices (drivers) and 32 receiving devices on the bus.E> Cont'd RS232 25 Pin RS232 [Fat [ix] S232 Pinout 25 Pin Male) [Fray Toco] S232 Pinout (9 Pin Male) \ DB-9 and DB-25 RS232 Connector InterfaceB Universal Serial Bus (USB) * Universal Serial Bus (USB) is a wired high speed serial bus for data communication. The USB host can support connections up to 127, including slave peripheral devices and other USB hosts.> IEEE 1394 (Firewire) IEEE 1394 (Firewire) is a wired, isochronous high speed serial communication bus. It is also known as High Performance Serial Bus (HPSB). = 1394 is a popular communication interface for connecting embedded devices like Digital Camera, Camcorder, Scanners to desktop computers for data transfer and storage. = Unlike USB interface, IEEE 1394 doesn’t require a host for communicating between devices. For example, you can directly /connect a scanner with a printer for printing. The data rate supported / by 1394 is far higher than the one supported by USB 2.0 interface. The 1394 hardware implementation is much costlier than USB implementation. ? %E> Infrared Data Association (IrDA) | * Infrared (IrDA) is a serial, half duplex, line of sight based wireless technology for data communication between devices. It is in use from the olden days of communication and you may be very familiar with it. The remote control of your TV, VCD player, etc works on Infrared data communication principle.Bluetooth (BT) Bluetooth is a low cost, low power, short range wireless technology for data and voice communication. Bluetooth supports point-to-point | (device to device) and point-to-multipoint (device to multiple device broadcasting) wireless communication. * A Bluetooth device can function as either master or slave. When a network is formed with one Bluetooth device as master and more than one device as slaves, it is called a Piconet. A Piconet supports a maximum of seven slave devices. fluctooth is the favorite choice for short range data communication in handheld embedded devices. Bluetooth technology is very popular among cell phone users as they are the easiest communication channel for transferring ringtones, music files, pictures, media files, etc between neighboring Bluetooth enabled phones. Tt supports a data rate of up to 1 Mbps and a range of approximately 30 feet for data communication. )DESIGNING WITH MICROPROCESSORS System Architecture: An Architecture is a set of elements and the relationships between them that together form a single unit. The architecture of an embedded computing system is the blueprint for implementing that system it gives an information about the components needed and how they are put together. It includes both hardware and software elements. It includes several elements, some of which may be less obvious than others. m CPU An embedded computing system clearly contains a microprocessor. There are many different architectures, and even within an architecture there are models that vary in clock speed, bus data width, integrated peripherals, and so on. The choice of the CPU is one of the most important, also the software that will execute on the machine. @ Bus The choice of a bus is closely tied to that of a CPU, since the bus is an integral part of the microprocessor. But in applications that make intensive use of the bus due to I/O or other data traffic, the bus may be more of a limiting factor than the CPU.System Architecture cont’d.... = Memory The most obvious characteristic of the memory is its total size, which depends on both the required data volume and the size of the program instructions. The ratio of ROM to RAM and selection of DRAM versus SRAM can have a significant influence on the cost of the system. The speed of the memory plays a great role in determining system performance. = Input and Output devices: For a given function, there may be several different devices of varying sophistication and cost that can do the job for the CPU. These devices are called the I/O devices based on fact whether such device is being used for input or output operation. e.g. A set of switches and knobs on a front panel may all be controlled by a single microcontroller, which is in turn connected to the main CPU. The difficulty of using a particular device, such as the amount of glue logic required to interface it, may also play a role in final device selection. :Hardware Design Step - 1: Consider evaluation boards supplied by the microprocessor manufacturer or another company working in collaboration with the manufacturer. Evaluation boards are sold for many microprocessor systems; they typically include the CPU, some memory, a serial link for downloading programs, and some minimal number of /0 devices. Figure below shows an ARM evaluation board manufactured by Sharp. The evaluation board may be a Complete Solution oF provide what is needed with only slight modifications. If the evaluation board is supplied by the microprocessor vendor, its design may be available from the vendor; If the evaluation board comes from a third party, it may be possible to contract them to design a new board with the required modifications, or start from scratch on a new board design. interrupt switch Powe ewply Revel eachHardware Design cont’d.... ‘Step-ll: The other major task is the choice of memory and peripheral components. In the case of I/O devices, there are two alternatives for each device: selecting a component from a catalog or designing from scratch. When shopping for devices from a catalog, it is important to read data sheets carefully; it may not be trivial to figure out whether the device does what it is intended for. Also due consideration must be given to the amount of glue logic required to connect the device to the bus. Simple peripheral logic can be implemented in Programmable Logic Devices (PLDs), while more complex units can be built from Field-programmable Gate Arrays (FPGAs).The PC as a Platform Personal computers are often used as platforms for embedded computing. ‘Advantages of a PC: it is a predesigned hardware platform with a great many features, a wide variety of 1/0 devices can be attached to it, and it provides a rich programming environment. Disadvantage: PC is larger, more power hungry, and more expensive than a custom hardware platform would be. However, for low-volume applications and environments such as factories and offices where size and power are not critical, using a PC to build an embedded system often makes a lot of sense. ‘As shown in adjacent Figure, a typical PC includes several major hardware components: = The CPU provides basic computational facilities. m= RAM js used for program storage. = ROM holds the boot program. = A DMA capabilities. m= Timers are used by the operating system for a variety of purposes. = A High-speed Bus, connected to the CPU bus through a bridge, allows fast devices to communicate efficiently with the rest of the system. = A Low-speed Bus provides an inexpensive way to connect simpler devices and may be necessary for backward compatibility as well, controller provides DMA ou rast | rom asp ewer ‘ervtur pas inten |°Tagr apd ar twa | [ amas exile bo Low peed hate ence Hardware architecture of a typical PCPCI (Peripheral Component Interconnect) PCI is the High-performance system bus which uses High-speed data transmission techniques and efficient protocols to achieve high throughput. The original PCI standard allowed operation up to 33 MHz; at that rate, a maximum transfer rate of 264 MB/s can be achieved using it transfers. The revised PCI standard allows the bus to run up to 66 MHz, giving a maximum transfer rate of 524 MB/s with 64-bit wide transfers. PCI uses wide buses with many data and address bits along with multiple control bits. The width of the PCI bus increases both the cost of an interface to the bus and makes the physical connection to the bus more complicated. PCI also allows devices to be chained together so that users need not worry about the order of devices on the bus or other details of connection. USB (Universal Serial Bus) and IEEE 1394 are the two major high-speed serial buses. Both of these buses offer high transfer rates using simple connectors.Basic Input / Output System (BIOS) A PC provides a standard software platform that interfaces to the underlying hardware as well as more advanced services. At the bottom of the software platform structure in most PCs is a minimal set of software in ROM. This software is designed to load the complete operating system from some other device (disk, network, etc.), and it may also provide low-level hardware interfaces. In the IBM-compatible PC, the low-level software is known as the Basic Input / Output System (BIOS). The BIOS pro facilities. les low-level hardware drivers as well as booting The operating system provides high-level drivers, control of executing processes, user interfaces, and so on.System organization of the Intel StrongARM SA-1100 and SA-1111 ‘The StrongARM SA-1100 provides a number of functions besides the ARM CPU, The chip contains two on-chip buses: a high-speed system bus and a lower-speed peripheral bus. The chip also uses two different clocks. A 3.686 MHz clock is used to drive the CPU and high-speed ‘peripherals, and a 32.768 kH2 clock is an input to the system control module, ‘The system control module contains the following peripheral devices: = Arealtime clock = An operating system timer = 28 general-purpose I/Os (GPIOs) m= An interrupt controller A power manager controller = A reset controller that handles resetting the processor. The 32.768 kHz clock’s frequency is chosen to 3.686 MHz clock: —————————tm] aay be useful in timing real-time events. cru The slower clock is also used by the power — sa 750 4147 clock ——pe core manager to provide continued operation of the manager at a lower clock rate and therefore lower power consumption.DEVELOPMENT AND DEBUGGING | Development Environments: A typical embedded computing system has a relatively small amount of everything, including CPU horsepower, memory, 1/0 devices, and so forth. ‘Asa result, it is common to do at least part of the software development on a PC or workstation known as a host as illustrated in Figure below. The hardware on which the code will finally run is known as the Target. The host and target are frequently connected by a USB link, but a higher-speed link such as Ethernet can also be used. The target must include a small amount of software to talk to the host system. That software will take up some memory, interrupt vectors, and so on, but it should generally leave the smallest possible footprint in the target to avoid interfering with the application software. The host should be able to do the following: m load programs into the target, Ww mm start and stop program execution on the target, and m examine memory and CPU registers. Ea Biba Connecting a host and a target systemDEVELOPMENT AND DEBUGGING cont'd... A Cross-compiler is a compiler that runs on one type of machine but generates code for another. After compilation, the executable code is downloaded to the embedded system by a serial link or perhaps burned in a PROM and plugged in. Host-target debuggers are often used, in which the basic hooks for debugging are provided by the target and a more sophisticated user interface is created by the host. A PC or workstation offers a programming environment which is much friendlier than the typical embedded computing platform. Problem with this approach emerges when debugging code talks to I/O devices, as the host will not have the same devices configured in the same way, the embedded code cannot be run as is done on the host. A Test-bench program can be built to help debug the embedded code. The Test-bench generates inputs to simulate the actions of the input devices; it may also take the output values and compare them against expected values, providing valuable early debugging help. The embedded code may need to be slightly modified to work with the Testbench, but careful coding (such as using the #ifdef directive in C) can ensure that the changes can be undone easily and without introducing bugs.Debugging Techniques (S/W based) A Software Debugging can be done by Compiling and Executing the code on a PC or workstation. But at some point it inevitably becomes necessary to run code on the embedded hardware platform. Embedded systems are usually less friendly programming environments than PCs but, the resourceful designer has several options available for debugging the system. The serial port found on most evaluation boards is one of the most important debugging tools. It is a good idea to design a serial port into an embedded system even if it is not likely to be used in the final product; the serial port can be used not only for development debugging but also for diagnosing problems in the field.Debugging Techniques (S/W based) cont’d...._| Another very important debugging tool is the Breakpoint. The simplest form of a Breakpoint is for the user to specify an address at which the program’s execution is to break. When the PC reaches that address, control is returned to the monitor program. From the monitor program, the user can examine and/or modify CPU registers, after which execution can be continued. Implementing breakpoints does not require using __exceptions or external devices.Debugging Techniques (S/W based) cont’d.... Following Programming Example shows how to use instructions to create breakpoints. Breakpoints: A breakpoint is a location in memory at which a program stops executing and returns to the debugging tool or monitor program. Implementing breakpoints is very simple, it only requires replacement of the instruction at the breakpoint location with a subroutine call to the monitor. In the following code, to establish a breakpoint at location 0x40c in some ARM code, the branch (8) instruction is replaced and is normally held at that location with a subroutine call (BL) to the breakpoint handling routine: @ x 400 MUL r4,r4,r6 @ x 400 MUL r4,r4,r6 © x 404 ADD r2,r2,r6 = > Bx 404 ADD r2,r2,r4 © x 408 ADD r0,r0,#1 © x 408 ADD r0,r0, #1 © x 4@c B loop @ x 48c BL bkpoint When the breakpoint handler is called, it saves all the registers and can then display the CPU state to the user and take commands. ‘To continue execution, the original instruction must be replaced in the program. if the breakpoint can be erased, the original instruction can simply be replaced and control returned to that instruction. This will normally require fixing the subroutine return address, which will point to the instruction after the breakpoint.Debugging Techniques (H/W based) cont’d.... When Software Tools are insufficient to debug the system, Hardware aids can be deployed to give a clearer view of what is happening when the system is running. The microprocessor In Circuit Emulator (ICE) is a specialized hardware tool that can help debug software in a working embedded system. An ICE is a special version of the microprocessor that allows its internal registers to be read out when it is stopped. The In-circuit Emulator surrounds this specialized microprocessor with additional logic that allows the user to specify breakpoints and examine and modify the CPU state. The CPU provides as much debugging functionality as a debugger within a monitor program, but does not take up any memory. Drawback of In-circuit Emulation: The machine is specific to a particular microprocessor, even down to the pinout. If several microprocessors are used, maintaining a fleet of In-circuit Emulators to match can be very expensive.Debugging Techniques (H/W based) cont’d.... The Logic Analyzer is the other major piece of instrumentation in the embedded system designer’s arsenal. Think of a logic analyzer as an array of inexpensive oscilloscopes; the analyzer can sample many different signals simultaneously (tens to hundreds) but can display only 0, 1, or changing values for each. All these logic analysis channels can be connected to the system to record the activity on many signals simultaneously. The logic analyzer records the values on the signals into an internal memory and then displays the results on a display once the memory is full or the run is aborted. The logic analyzer can capture thousands or even millions of samples of data on all of these channels, providing a much larger time window into the operation of the machine than is possible with a conventional oscilloscope.Debugging Techniques (H/W based) cont’d.... A typical Logic Analyzer can acquire data in either of two modes that are typically called State and Timing modes. The measurement resolution on each signal is reduced in both voltage and time dimensions. The reduced voltage resolution is accomplished by measuring logic values (0, 1, x) rather than analog voltages. The reduction in Timing resolution is accomplished by sampling the signal, rather than capturing a continuous waveform as in an analog oscilloscope. State and timing mode represent different ways of sampling the values. Timing mode uses an Internal Clock that is fast enough to take several samples per clock period in a typical system. State mode, uses the System’s own Clock to control sampling, so it samples each signal only once per clock cycle. As a result, timing mode requires more memory to store a given number of system clock cycles. On the other hand, it provides greater resolution in the signal for detecting glitches. Timing mode is typically used for glitch-oriented debugging, while state mode is used for sequentially oriented problems.Debugging Techniques (H/W based) cont’d ‘The Internal Architecture of a logic analyzer is shown in Figure below. The system's data signals are sampled at a latch within the logic analyzer; the latch is controlled by either the system clock or the internal logic analyzer sampling clock, depending on whether the analyzer is being used in state or timing mode. Each sample is copied into a vector memory under the contro! of a state machine. The latch, timing circuitry, sample memory, and controller must be designed to run at high speed since several samples per system clock cycle may be required in timing mode. After the sampling is complete, an embedded microprocessor takes over to control the display of the data captured in the sample memory. Logic analyzers typically provide a number of formats for viewing data. One format is a timing diagram format. Many logic analyzers allow not only customized displays, such as giving names to signals, but also more advanced display options. For example, an inverse assembler can be used to turn vector values into microprocessor instructions. ‘The logic analyzer does not provide access to the internal state of the components, but it does give a very good view of the externally visible signals. That information can be used for both Functional and timing debugging. [Architecture of a Logic AnalyzerDebugging Challenges Logical errors in software can be hard to track down, but errors in real-time code can create problems that are even harder to diagnose. Real-time programs are required to finish their work within a certain amount of time; if they run too long, they can create very unexpected behavior. Example below demonstrates one of the problems that can arise. A timing error in real-time code: To make it easier to compare input to output and see the results of the bug, assuming that the computation produces an output equal to the input, but that a bug causes the computation to run 50% longer than its given time interval. A sample input to the program over several sample periods follows:Debugging Challenges cont’d.... If the program ran fast enough to meet its deadline, the output would simply be a time shifted copy of the input. But when the program runs over its allotted time, the output will become very different. The behavior of the A/D and D/A converters is unpredictable make some assumptions like First, the A/D converter holds its current sample in a register until the next sample period, and the D/A converter changes its output whenever it receives a new sample. Next, a reasonable assumption about interrupt systems is that, when an interrupt is not satisfied and the device interrupts again, the device’s old value will disappear and be replaced by the new value. The basic situation that develops when the interrupt routine runs too long is something like this: 1. The A/D converter is prompted by the timer to generate a new value, saves it in the register, and requests an interrupt. 2. The interrupt handler runs too long from the last sample. 3. The A/D converter gets another sample at the next period. 4. The interrupt handler finishes its first request and then immediately responds to the second interrupt. It never sees the first sample and only gets the second one.Debugging Challenges cont’d Thus, assuming that the Interrupt Handler takes 1.5 times longer than it should, here is how it would process the sample input: * Input sample = Output sample The output waveform is seriously distorted because the interrupt routine grabs the wrong samples and puts the results out at the wrong times. The exact results of missing real-time deadlines depend on the detailed characteristics of the I/O devices and the nature of the timing violation. This makes debugging real-time problems especially difficult and if a system exhibits truly unusual behavior, missed deadlines should be suspected. In-circuit emulators, logic analyzers, and even LEDs can be useful tools in checking the execution time of real-time code to determine whether it in fact meets its deadline.SYSTEM-LEVEL PERFORMANCE ANALYSIS SYSTEM-LEVEL PERFORMANCE involves much more than the CPU. Though focus is on often the CPU because it processes instructions, but any part of the system can affect total system performance. More precisely, the CPU provides an upper bound on performance, but any other part of the system can slow down the CPU. Merely counting instruction execution times is not enough. Consider the simple system of Figure below. Data needs to be moved from memory to the CPU to process it. To get the data from memory to the CPU following must be done: m read from the memory; im transfer over the bus to the cache; and m transfer from the cache to the CPU. bus System level Data Flows and PerformanceSYSTEM-LEVEL PERFORMANCE ANALYSIS cont’.... The time required to transfer from the cache to the CPU is included in the instruction execution time, but the other two times are not. The most basic measure of performance is Bandwidth— the rate at which the data can be moved. The point of interest is real-time performance measured in seconds. But often the simplest way to measure performance is in units of clock cycles. However, different parts of the system will run at different clock rates. So, it has to be ensured that the right clock rate is applied to each part of the performance estimate while converting clock cycles to seconds. For simplicity, consider the bandwidth provided by only one system component, the bus. Consider an image of 320240 pixels, with each pixel composed of 3 bytes of data. This gives a grand total of 230, 400 bytes of data. If these images are video frames, then it is to be checked if one frame can be pushed through the system within the 1/30s that a frame has to be processed before the next one arrives.Embedded System Components * It embeds Hardware similar to a computer * Software usually embeds in the ROM, flash memory or media card * It embeds a Real Time Operation System (RTOS)INTRODUCTION TO EMBEDDED SYSTEMS * Introduction to Embedded Systems * The Build process for embedded systems * Structural units in Embedded processor * Selection of processor * Selection of Memory devicesINTRODUCTION TO EMBEDDED SYSTEMS * DMA * Memory management methods * Timer and Counting devices * Watchdog Timer * Real Time Clock * In circuit emulator * Target Hardware Debugging.Components of Embedded System Hardware wis oh 7 iBuilding Blocks of Embedded System Hardware * The Hardware consists of following building blocks and devices: Power source Clock Oscillator and Clocking Units system Timer Real Time Cock Reset Circuit Power Up Reset Watchdog Timer Reset Memory 1/0 ports 1/0 buses 1/0 Interfaces * DAC + ADC AWhat a Embedded System Is???The Build Process * The first step is selecting a processor * The processor is selected from the following considerations — Instruction Set — Maximum bits in an operand in an operation —Clock frequency in MHz or GHz and the processing speed in Million Instructions per seconds — Processor ability to solve the complex algorithms used in meeting the deadlines for their processingThe Build Process The build process for embedding software consists of the following steps — Project file consisting of source file and library files — Compilation of the project files — Linking all object files and locating onto a single re-locatable object file — Converting the object file in a form called hex-file to binary imageThe Build Process Translation HierarchyDesign Process in Embedded System * Concepts used during Design process — Abstraction — Hardware and Software Architectures — Extra Functional Properties — System Related family of Designs — Modular Design — Mapping — User Interfaces Design — Refinements) Design Process in Embedded System , » Software Design Process ge -Design Process in Embedded System * Design Metrics — Power Dissipation — Performance — Process Deadlines — User Interfaces — Size — Engineering Cost — Manufacturing Cost — Flexibility — Prototype Development Time — Time to Market — System and User Safety — MaintenanceConstraints of Embedded Systems Available System Memory Available Processor Speed Meeting Deadlines Performance Power Size Design and Manufacturing CostSelection of Processor * Different systems require different processor features * The processor is selected from the following considerations — Instruction Set — Maximum bits in an operand in an operation — Processing Speed — Ability to solve the complex algorithms — A processor gives high computing performance when it has * Pipeline and Superscalar architecture * Pre-fetch cache unit, caches, register files and MMU * RISC core architectureSelection of Memory Devices * Software designer coding is over and the ROM image file is ready, a hardware designer of a system is faced with the a questions, of - what type of memory ? — what to use? — how much size of each, should be to used???Selection of Memory Devices * Some of the selection process is, — Internal ROM — Internal EPROM — Internal EEPROM — Internal RAM — ROM Device — EPROM Device — EEPROM Device — Flash Device — RAM device — Parameterized Distributed RAM — Parameterized Block RAMMemory Management Methods Techniques of M.MSegmentation » A process encapsulates all the information that is involved in executing a program, including source code, stack and data. >» All of the different types of information within a process are divided into logical memory units of variable sizes called SEGMENTS » Most OS typically allow processes to have all or some combination of five types of information within segments such as »Code Segment » Data Segment > Block started by Symbol > Stack Segment