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Aci1 10 PDF
Aci1 10 PDF
System Document
Texas Instruments
April 30, 2003
ACI1-1 – System overview
Modules BOX_CAR RMP_CNTL
CAP_EVENT_DRV SINCOSPH
COMPWM SINTB360
DATA_LOG SPEED_PRD
PID_ID SYS_INIT
FC_PWM_O_DRV V_HZ_PROFILE
ADC04U_DRV
System S/W ASM “C”
Program memory 1402 words 1915 words 1
Data memory 205 words 495 words 1
Development / Code Composer Studio v2.2 (or above) with Real
Emulation Time debug
* Default target HW is F2407 eZdsp. If different target is used, the software may need to be modified.
1
Note: The C version of the software at this time excludes the modules COMPWM,
FC_PWM_O_DRV, and ADC04U_DRV. Instead, the module FC_PWM_DRV has been
used. Also, the incremental build level 4 is not implemented for the C system.
System Overview
Figure 1 shows the complete system configuration for a single-phase ACI motor drive. A
full H-bridge is utilized to control two phase voltages of the motor. Four PWM channels
from the DSP control four power devices of the inverter. Two analog to digital channels
are utilized to measure DC bus voltages. One capture input is needed to measure the
speed of the drive.
x24xx
DSP
PWM1
+
PWM2
Line PWM1 PWM3 ACI
PWM3
Single phase
PWM4
Neutral
ADCINx
+
PWM2 PWM4
ADCINx
CAP1
CAP1
Tacho
ADCINx
ADCINx
c_int0
INT2 interrupt
Initialize
S/W Modules Save contexts and
clear interrupt
Initialize timer T1 flags
and realtime time monitor
Execute the
Enable T1 selected
underflow interrupt incremental build
and core interrupt
INT2.
Execute
DATA_LOG
module
Refer to the User’s Guides and or Manuals fo r configuration of items 2 and 4 and their
connection to the system. The following are some of the other system level choices that
must be made:
It is also assumed that the emulator used is XDS510pp. Once the directory
“C:\TIDCS \DMC\C24\SYS\ACI1_1\ASM” contains all the necessary files (as
mentioned above), the next step is to provide the supply voltage (+5V DC) to the
x2407eZdsp and RESET the emulator. Then start the Code Composer and open the
project aci11.pjt. Now load the workspace file aci1_1.wks.
Loading the workspace will automatically open up the project file aci11.pjt and show all
the files relevant to the project. The following shows the expanded project view as part of
CC environment aci1_1.wks is loaded:
Note that the same project can be built from scratch easily if the workspace file,
aci1_1.wks, can’t be loaded directly because of differences in CC setup and or emulator
used. Refer to CC tutorial for information on a building project.
The variables in the Watch Window can be added manually according to CC tutorial.
From the ‘PROGRAM LOAD OPTIONS’ in CC select ‘Load Program After Build’ for
automatic loading of the program to the target once the program is compiled.
1.3 Loading and building CC Project for “C” case
The process for loading and building the C version of the ACI1-1 system is same as the
assembly case with the following exceptions:
dlog1.dlog_iptr1=&vhz.sc.sine_a1;
2. Incremental Build Control: The build level is set in the header file, build.h in the C
infrastructure. This header file is in the
C:\TIDCS \DMC\C24\SYS\ACI1_1\C\INCLUDE\ directory. The incremental build
level 4 is not implemented for the C system.
To set the build level, define the symbol BUILDLEVEL to one of the available levels.
/*--------------------------------------------------------------------------------------------------------
Following is the list of the Build Level choices.
-----------------------------------------------------------------------------------------------------------*/
#define LEVEL1 1
#define LEVEL2 2
#define LEVEL3 3
#define LEVEL3 4 /* This LEVEL4 is not implemented yet */
/*--------------------------------------------------------------------------------------------------------
This line sets the BUILDLEVEL to one of the available choices.
-----------------------------------------------------------------------------------------------------------*/
#define BUILDLEVEL LEVEL3
3. The target processor selection is in the header file, target.h. This file is included in
the code composer project and can also be found in the directory
C:\TIDCS \DMC\C24\SYS\ACI1_1\C\INCLUDE\
To change the processor set the TARGET macro to the desired one.
/*--------------------------------------------------------------------------------------------------------
Following is the selection list of the target choices.
Note that the F241 is represented by the F243 and the
LF2407 represents the LF2406 and the LF2402.
---------------------------------------------------------------------------------------------------------*/
#define F240 1
#define F243 2
#define F2407 4
#define UNKNOWN 8
/*--------------------------------------------------------------------------------------------------------
This line sets the target to one of the available choices.
---------------------------------------------------------------------------------------------------------*/
#define TARGET F2407
4. The object VHZ11_TI is defined in the header file, vhz11_ti.h and it is implemented
as vhz in aci11.c. This has many sub-objects such as PIDREG1, SINCOSPH,
RMPCNTL, etc. To modify variables such as pid coefficients, etc. watch:
i. The entire object vhz , and observe/modify vhz.pid.Kp_reg1.
ii. An alternative is to watch vhz.pid and modify pid.Kp_reg1.
Watching smaller objects in the watch window has the advantage of lowering the
amount of data that must be up- loaded to the debug tool.
In the SYSTEM OPTIONS section of the code, select phase 1 incremental build option
by setting the constant phase1_commissioning to 1. Save the program, compile it and
load it to the target.
2.1 Phase 1
• In this phase, two sine waves are generated based on the user speed input as
shown in Figure-1. Three software modules are utilized in this phase to generate two
sine wave forms.
• Set phase1_commissioning = 1 in ACI1_10.asm as shown below-
phase1_commissioning .set 1
phase2_commissioning .set 0
phase3_commissioning .set 0
phase4_commissioning .set 0
sine_a1
speed_setpt
RAMP_CNTL x V_Hz_PROFILE SINCOSPH
sine_a2
Graph Window1
DATA_LOG
Graph Window2
phase1_commissioning .set 0
phase2_commissioning .set 1
phase3_commissioning .set 0
phase4_commissioning .set 0
speed_setpt
X RAMP_CNTL V_Hz_PROFILE SINCOSPH
direction
CC GRAPH DISPLAY 1
CC GRAPH DISPLAY 1
PWM 1
PWM 2
FC_PWM_DRV
PWM 3
PWM 4
SPEED_PRD CAP_EVENT_DRV
Q1 Q3
C1
NEUTRAL-P19-P20
Q2 Q4
C2
PHASE 1
PHASE 2
In this phase, the same single phase AC induction motor is operated in variable speed
mode. However, in this phase, the speed of the motor is measured using a hall effect
sensor,and hardware capture module of the DSP controller in order to close the speed
loop. The following asm files are utilized to measure the motor speed–
phase1_commissioning .set 0
phase2_commissioning .set 0
phase3_commissioning .set 1
phase4_commissioning .set 0
• The Hall effect speed sensor output is connected to P30 of DMC1500. P30 has
ground, power and capture input. The available ground and power from P30 can be
utilized as sensor ground and power. The voltage output at P30 can be set at various
level to match the sensor requirement.
• The remaining hardware setup is similar to Phase-2b.
• After starting the software, the motor will start rotating as the DC bus voltage is
applied by rotating the variac from zero to higher voltages.
• The measured speed can be watched by adding the variable “speed_rpm” in the
watch window.
• The speed loop is closed by putting closed_loop_flag=1
• Appendix-3 shows the complete software block diagram of Phase-3.
5.1 Incremental System Build – Phase 4
In this stage, the same single phase AC induction motor is operated with DC bus
voltage ripple compensation. The configuration of single phase AC induction
motor drive inverter creates significant DC bus voltage ripple. This DC bus
voltage ripple distorts the inverter output voltage and consequently lowers the
drive performance. The drive is made immune to ripple voltage my adjusting
PWM outputs according to the DC bus voltage variation. In a single -phase
inverter, voltage across both capacitors is measured to implement independent
phase voltage compensation. The following asm files are utilized to implement
ripple compensation –
phase1_commissioning .set 0
phase2_commissioning .set 0
phase3_commissioning .set 0
phase4_commissioning .set 1
rpm_scaler
phase_in phase
SINCOSPH
RAMP_CNTL
sine_a2
V_Hz_
vhz_freq PROFILE v_out
gain_cs
APPENDIX -2 Phase – 2
rpm_scaler
phase_in phase
SINCOSPH
target_value setpt_value
speed_set freq_in
freq sine_a1
pt
RAMP_CNTL
sine_a2
V_Hz_
vhz_freq PROFILE v_out
gain_cs
direction
sine_a1 PWM1
FC_PWM EV
sine_a2 mfunc_c1
DRV PWM2
mfunc_c2
Q0 HW PWM3
EV CAP_ PWM4
EVENT_ SPEED_
CAPn CAP1FIFO time_stamp PRD speed_prd
H/W DRV mfunc_c3
0
Q15
APPENDIX – III Phase –3
closed_loop_flag
rpm_scaler
target_value setpt_value
RAMP_CNTL
EV CAP_
EVENT_ SPEED_ BOX_CAR
CAPn CAP1FIFO time_stamp PRD speed_prd BC_IN BC_OUT D_fb
H/W DRV
Q15
direction
phase_i phase
n SINCOSPH
PWM1
freq_in mfunc_c3 FC_PWM EV
freq
DRV PWM2
sine_a1
V_Hz_ Q0 HW PWM3
vhz_freq PROFILE v_out mfunc_c1
gain_cs sine_a2
PWM4
Q15 / Q15 mfunc_c2
APPENDIX – IV Phase – 4
rpm_scaler
phase_in
direction
phase phase_in
SINCOSPH freq
sine_a1
EV COMPWM
PWM1 gain_cs
mfunc_c1 sine_a2
PWM2
HW mfunc_c2
PWM3
PWM4
mfunc_c3
0
ADC channel connected to
VDC_ACTUAL total_bus
ADC04DRV EV measure total DC bus voltage
VDC_HOT HW
half_bus
ADC channel connected to
DC_RIPPLE ripple_on measure half of DC bus voltage