SERVICE MANUAL OIR/W CONTENTS |. SPECIFICATIONS ‘STRUCTURAL DIAGRAM BLOCK DIAGRAM .. 1. CIRCUITDIAGRAM . P.C.BOARDS .. 3. DIAGNOSTIC TEST 7. REFERENCE DATA PARTSLUIST ... exe awn1. SPECIFICATIONS Tone generation method : Tone generator Waveform ory Effects Programs Combinations Sequencer section Control inputs Outputs PCM card slot PROG/SEQ card slot MIDI Display Options Power consumption Dimensions Weight Al square synthesis system (full digital proessing) : 82 voices, 32 oscillators (single mode); 16 voices, 82 oscillators (double mode) 1 PCM 48 Nbits t two digital multi_effect systems 1 200 Programs + 200 Combinations : 10 Songs, 100 Patterns, maximum 7000 notes, 16 tracks, 16 timbers, (dynamic voice allocation) t Assignable pedals 1, 2 : W/L, 2/R, 3, 4, headphones : PCN data : for Progran/Conbination/Drum Kit/Globel parameters “Sequence data 2 IN, OUT, THRU : LOD 64 x 240 dots, full dot matrix, with backlight : RAN card (SRC-512), ROM card, PCK card DW : 430(H) x 405.3(D) x 89(H) 14.9 ke % Appearance and specifications are subject to change without notice for product improvement.PART HO. SOREWS & NUTS PART CODE a 1s F wes 791030808 8 ob wCS x6 718280808 c Wo we 7 ‘778060700 0 WBN 2 1778081200 E 8 wus x8 718280808 F PLAX B BZKC 8 x 10 145060310 c TS SSE 2NC 4 x 10 715130411, u FE B USE 2KC 8 x 6 ‘790080808 @ A ec. S~ ta BOARD KLW-1581 ( FOR 220/240V ) | 002158100 WVYDVIC IVUNLINULS “2Or in nawe pon tees |_| uses|_|pree|_| noe cain| | s7H cer [| mute, Rom DAC )—+ eaves. tL E LJ 1 - 5 | SYSTEM BUS omy 4 1 map| | cpu} | mae { fase | fore} fee} jeer) [Morr 25 260 | Ron RAtt RAC PANEL se wee | Ls sea ison: at j206K snan| vor vor aie pasesvsr 7 ts st] | asec on ee l PEDAL 2 0 “or Soa . sere Letter) INQ Saesal tie mipI auto THRU O o——{ power FE 738 Ac IN O-t untt > GND o— FS Sav WVYSVIC ND078 “EKLM-1580 WVYSVIC LINDUID “7KLM-1576 MAIN BOARD UAT FB n DATA a CT} MASTER cLooK S127, 21 UPDZSCSOOTEGH-339-€: 1048. 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Le ree 10 Sui? -Sup0" sue suTs Svae SWI GU30 Sues Sus avr KLM-1576 Main Board Te SY conse uss Suze suas Suse sues Sus) sve4 suSs ‘Svar Suze suse pstae-nsoarsse 7582, OST RIOM- 438223250 By 7 }ReBE € g s 57308 ' 8 Reg A B-. Fe dod 8 i SPURL a a : LEELERE Bo cenbbren}--¥ehofersibroesced glue $88 ' aba ea 7 ko VALUE © 18 0.1 9 Sah 1 BS Mane sa"afat Zs RE vse Sh Ett bes gety ause 135 SET ECHL EIS Sy Ml2%use0 arse. ser Tearveee? AS on tinsega cee ®KLM-15815. P.C. BOARDS KLM-1576A KLM-1576-1 i li. sa ill a 1€31—99105xx 1C32-39 104xx MOUNT PARTS SIDE ‘| 8 Y03-1777“ a SOME EE Y 2.0) JIS SLUVd IINNOW ON XX701L6<-ZEDI XXGOLELEDI AQBrISOA VOLSLINTAKLM-1578B/77B/79 Hol ; | prep 1 1 1 CEECEEEEEEEEN12 ° 3 ROA BAL!6. DIAGNOSTIC TEST Before you start the diagnostic test> Once this diagnostic test is started, the data in the O1R/# is initialized. If necessary data are memorized in it, please save the data into RAM cards before starting the test. Starting the test program> 1. Connect MIDI IN and OUT with a MIDI cable. 2. Insert a PCK card ( XSC-801 ) and a diagnostic test card into each card slot and turn the poer ON. At this time the protect switch of the test card must be OFF. 3. When the test program starts, the following tests are automatically carried out. x System ROM Check Sum ( Internal Test #00 ) x Internal RAM Test ( Internal Test #01 ) * RAM Card Test ( Internal Test #02 ) x LOD RAM Test ( Internal Test #03 ) = 1G & DF CPU I/F Test ( Internal Test #04 ) * Internal Battery Test ( Internal Test #05 ) x Card Battery Test ( Internal Test #06 ) * MIDI Loop Test (Internal Test #07 ) x PCN ROM TG I/F Test ( Internal Test #08 ) * PCM Card TG I/F Test ( Internal Test #09 ) If any error occurs to the result of the internal test, the error message will be indicated in the LCD and the panel LEDs will go on and off. When the internal test finishes normally, the program proceeds to TEST 1: SW & LED TEST. Then, when you turn the power ON while pressing '3’ and ‘RESET’ to start the test mode, you can omit the PCM card test and the MIDI loop test. In case that the protect switch of the RAN card is ON at the internal test #02 : RAM CARD TEST, the following message is indicated in the LCD. Error : ProtectIn case that an error occurs at the internal test #04 : TG & DF I/F TEST, the following message is indicated in the LCD. 1) In case that an error occurs between the TG and the LCD, * Voice flag * TG too long busy * Voice on flag 2) In case that an error occurs between the DF and the CPU, «VDA * EXC * VDF * PAN In case that MIDI IN and OUT are not connected with a MIDI cable at the internal test #07 : MIDI LOOP TEST, the following message is indicated in the LCD. x Error : OUT —X—— IN ( no connect ) TEST 1 : PANEL SW & LED TEST> ion of the LED’s lighting The test of the panel switches and the confirm are carried out. 1. Confirm that all the LEDs light red. 2. Press each switch according to the turn which is indicated in the LCD and confirm that they work correctly. ‘The turn to press the switches is as follows. COMBI, PROG, SEQ, INT/CARD, PAGE-, EDIT COMBI, EDIT PROG, GLOBAL, BANK, PAGE+, A, B, C, D, E, F, G, H, UP, DOWN, A. ¥. 7, 4, 1,10’sHOLD/-, 8, 5, 2, 0, 9, 6 3, COMPARE, REC/WRITE, START/STOP, RESET As for the switches whose LEDs light, confirm that the LEDs lisht red when the switches are pressed and then the LEDs light green when the switches are released. 3. When this check is finished to the RESET switch, the test program proceeds to the next autoxaticelly. 10TEST 2 : LCD PIXEL TEST> The test of the LCD’s indication is carried out. 1, Confirm that all the dots in the LCD light. If nothing is wrong with the LCD, press RESET to proceed to the next. 2. Confirm that all the dots in the LCD go out. If nothing is wrong with the LCD, press RESET to proceed to the next. TEST 3 : MDE/DF TEST> MDE and DF88 are checked. Connect an oscilloscope to OUTPUT 1. 1, Confirm that the output waveform of the MDE test is as follons. MDE TEST WAVEFORM If this test is N.G., check the circuit connected with MDE ( C37 ) and the analog circuit. If this test is 0.K., press RESET to proceed to the next. 2. Confirm that an explosion sound is output normally at the DF test. If this test is N.G., check the circuit between DF88 ( IC42 ) and MDE ( 1087 ). If this test is 0.X., press RESET to proceed to the next.TEST 4 : WS TEST> WS is checked with its test waveform. Confirm the following waveform appears when A, B, C or D is pressed. i it WS TEST WAVEFORM [A] WS TEST WAVEFORM [B] it rf WS TEST WAVEFORM [C] WS TEST WAVEFORM [D] Check to the test waveform D and if this test is N.G., check the circuit connected with TG ( IC45 ) and WS ( IC44 ). If this test is 0.K., press RESET to proceed to the next. TEST 5 : 1G TESTD TG is checked with its test waveform. Confirm the following waveform appears when one of A~H is pressed. ft E TG TEST WAVEFORM [A] TG TEST WAVEFORM [B] ~[D] TG TEST WAVEFORM(E] ~[H]The waveforms of B~D are different at their output levels. The waveforms of E~H are different at their terms of cycle. Check to the test waveform H and if this test is N.G., check the circuit connected with TG ( IC45 ). If this test is 0.K., press RESET to proceed to the next. The remaining noise and the output signal level from each output jack are checked. Set the master VR to the MAX and connect an oscilloscope or a noise meter to the OUTPUT jack which is to be checked. 1. Press any of A~F switches and measure the noise level of each OUTPUT jack with a noise meter. Confirm that the noise level of each QUTPUT jack is less than the regulation. After confirming the noise level of Ph-R of 'F’, press RESET to proceed to the next check. 2. Press any of A~F switches and measure the output signal level of each QUTPUT Jack with an oscilloscope. Confirm that the signal level of each OUTPUT jack is less than the regulation and each is the sine wave, Also, confirm that each output signal level changes at OUT-1 and OUT-2 when the master VR is operated. After confirming the output signal level of Ph-R of *F’, press ‘RESET’ to proceed to the next. remaining noise | output signal level | frequency ——— ouT-1 -17.0dBu 4.2 ~ 7.8 Vp-p 488 Hz our-2 out-3 -78.0 dBu + | 4.8 ~ 8.6 Vo-p 305 Hz ouT-4 Ph-L Ph-R The regulations of the remaining noise and the output signal level BTEST 7 : A/D TEST> The A/D test of the VALUE slider, the ASS.pedals 1 & 2 are carried out. 1. Confirm thet the value in the LCD changes between 0 ( KIN ) and 127 (MAX ) when the VALUE slider is operated. 2. Confirm that the value in the LCD changes between 0 and 127 when an EXP-2 is connected to the ASS.pedal 1 or 2 and it is operated. When all the checks are finished, press RESET to proceed to the menu screen. MENU SCREEND Selecting any number of 0 - 7 in the LCD with ten keys allows you to test the following. 0 : A/D Monitor 400s 1: Switch & LED 5: 16 2: Lop 6 : Noise & Level 3: MDE / DF 7: A/D Converter A: PCK ROM CheckSua =D : PCM CardSum XSC-801 There are some other functions which correspond to the ‘A’, *D’, ‘G’, 'H? switches. : PCM ROM Check Sum : PCM CARD Check Sum ( For XSC-801 ) : END > Refer to FINISHING THE TEST MODE> : CPY > Refer to COPY OF THE DIAGNOSTIC TEST CARDD =ao> 2% It takes a long time to complete A : PCN ROM Check Sum and D : PCH CARD Check Sum. Especially, it takes about 6 minutes to complete A? PCM ROM Check Sum. 1. PCM ROM Check Sum This is used to find the defect of the PCM ROK data. Even if the PCN ROM TG I/F test passes but the sound doesn’t sppear correctly, the defect of the ROM date will be considered. In this case, you will find the defect of the data with this check. But you will not know which ROM is defective from this check. The operation is as follows. When ’A’ is pressed, ‘Wait a minute’ is indicated and the check starts. It takes about 6 minutes to complete this check. When it is finished normally, ‘Completed’ is indicated in the LCD. 42. PCM CARD Check Sum This is used to find the defect of the PCM card ( XSC-801 ) data. The operation is as follows. Confirm that a PCM card is inserted into the PCM card slot. When ’D’ is pressed, ‘Wait a minute’ is indicated in the LCD and the check starts. It takes about 2 minutes to complete this check. When it is finished normally, ‘Completed’ is indicated in the LCD. FINISHING THE TEST MODE> 1, When the diagnostic test card and the PCM card are removed from each slot and ‘END’ is pressed, the preload data is loaded automatically and the program proceeds to the noraal mode. 2. After finishing the test mode, check the sound. COPY OF THE DIAGNOSTIC TEST CARD> ‘The 01R/W has the copy function of the RAM card for the diagnostic test and the data can be copied into the the other RAM card. Note that the internal data is initialized by using this function as well ‘as the diagnostic test because this test is in the test mode. The operation is as follows. 1, Insert the diagnostic test card into the PROG/SEQ DATA slot and set the protect switch of the RAM card to be OFF. 2. Turn the power ON while pressing *3’ and *RESET’ to start the test node. 8. When the test mode is started, press "REC/WRITE’ to proceed to the menu screen. 4, Remove the diagnostic test card from the slot and insert a new RAM card. Set the protect switch of the card to be OFF. 5. When "CPY’ is pressed, Save Start’ is indicated in the LCD and the test data is saved into the new RAN card. When saving is completed, ’Completed’ is indicated in the LCD. 6. Remove the RAM card and then press ’END’ to finish the test mode. 5CINITIALIZING THE INTERNAL DATAD When you turn the power ON while pressing ’RESET’ and any of ’COMPARE’, °3", '6’ or '9” together, the version number of the system ROM is indicated in the LCD and the internal deta is initialized. Then, if you would like to know the version number of the system ROW only, turn the power ON while pressing only "RESET’ - you will see the version number in the LCD without initializing the internal date. The D/A offset has been adjusted when the product is released on the warket but you need to adjust it only in case that the D/A converter and its connected electronic parts. Connect a digital volt meter to Ipin and Spin of the connector CNIIA on the KLN-1576 p.c.board. Then, confirm the offset voltage is OV. If it is slipped off, adjust it with the YRI. When you adjust it with the oscilloscope, the voltage range should be less than 51. 167. REFERENCE DATA M37450M4-601FP (KSP) PIN ASSIGNMENT versa ® M37450M4-601FP PN FUNCTION PIN MARK PIN NAME vo PIN MARK PIN NAME 0 ee a Ce cee ¢ rominc our | 0 [ass wmnuas ves‘ POO~POT 1/0 PORT 0 W/o | RO READ SIG. OUT 0 P20~P27 Tivo PORT 2 1/0 | RESETOUT RESET SIG. OUT Q (CHECK POINT FOR M37450M4-601FP 1.XIN (28pin) 2.RXD (77pin) 7 2v/SuS divMB87726 (TG88) PIN ASSIGNMENT O O KORG MB87726 MB87726 (TG88) PIN FUNCTION PIN NAME [ 1/0, FUNCTION VDD = [5v VSS) =__[Gno. ‘SMODE 1 [Sub 1G Mode CW:Sub 1G L:Master 1G ) MODE 1 [Sampling Rate Switch (H:48KHz —L:30KHz ) XRESET 1 [Tow Active Initial Clear CLK [Master Clock KCRO O_| System Counter Reset for Sub TG Chip XCRI 1__| System Counter Reset from Master 1G Chip TEsT0-3 | I | Test Node Selector XCsT 1 [Chip Select XRT 1 [Write Pulse Input from CPU ROT 1 [Read Pulse Input from CPU 40-9 [Address Input_from CPU 0-7, 1/0_| Data Input _frow CPU D815 70 {Data Input for 16bit Data Bus DMODE 1 [CPU I/F Data Bus Syze Select CL:bit_H-lebit ) EWO0-15 | 1 | Even-address Wave Data In ( from Wave ROM ) oW00-15 | I | Odd-address Wave Data In ( from Wave ROM ) wa0-19 | 0 [Address Bus for Wave ROM or RAW W50-3 OQ [Bank Number Out for Wave ROM (16 Banks ) 000-19 [| 0 | Voice Data Out for External Filters or NOE NO: 0 [Voice Number Out RAso-3_ [| for caso-3_| 0 | for OWEO-3_| 0 | Write Enable for MDE OWEF, O [Write Enable for New Filter Chip (MB87727 )CHECK POINT FOR MB87726 1.OWEF (119pin) { 2.0LK (11Ipin) duty cycle of 50% 1=0. 1uS 2/0. 5uS div 1/0.2uS div 2v/20uS div VN4 VN3 VN2 VNI VNO {—————_ 308. ———MB87727 (DF88) PIN ASSIGNMENT MB87727 (DF88) PIN FUNCTION NO. [1/0 [PIN NAME | GROUP. NOTE 1 = VSS = 2 [1 {10 3[1 [at 41 [re 5 [1 [8 61 [MM A | CPU ADDRESS 711145 a1 [ae 3 I AT jo [1 [as u = VSS = [1 [49 CPU_ADDRESS 13_[1/0 [00 7 ia {1/0 [ot CPU DATA BUS 16 | 1/0 [02 16 = VOD = 1 [i/o [0s 18 | 1/0 _| D4 1s Tots B | CPU DATA BUS 20 [1/0 [06 2i_| = [Vs = 22 {170 | 07 23 [1/0 | 08 24_| 1/0 [09 25] 1/0_[ 010, 26 [1/0 [ott c | cpu DATA BUS 27 {1/0 [p12 26_| 1/0 [013 29 [1/0 [014 1/0 [015NO. [1/0 [ PIN NAME | GROUP NOTE 31] = [ss = 32_{ 1 [ANG 33_[ [iv 34 1 IVN2 TG VOICE NO. 36_[ 1 [avs 36_[_1_ | na D 37 {| voo 3e_[ 1 [ivor 3-1 ie TG VOICE DATA 40_[- [vos 7 ee = az [i [ios] 43 1 105 “bs £ | TG VOICE DATA 45 [1 [vor 46_| =| v0 = a7 |_| vos 48_[_1_| vos eto E | TG vorce DATA so [von s1_| [ss = sz_{ 1 [ior 53 1 | ivois 4 | 1 _fivois oe [fv sev F | 1G voice DATA I i 1 TG VOICE DATA ENABLE ‘SYSTEM RESET PARALLEL OUT FORMAT SELECT CPU DBUS BIT LENGTH SELECT a FILTER MODE SELECT INCIRCUIT TESTER MODE SELECT LSI_TESTER MODE SELECT MASTER CLOCK NOT USE 4 [ourpuT ata CL IPER ON7OFF DATA SHIFT SELECT BITO DATA SHIFT SELECT BIT " DATA SHIFT SELECT BIT2 PARALLEL OUT VOICE DATA ENABLE SERIAL OUT DATA 21NO._[1/0_[ PIN NAME | GROUP. NOTE, a1_| - | ss = e2_[ 0 _| scx SERIAL OUT_BIT_CLOCK o_{ sen SERIAL OUT DATA ENABLE o_| scuz SERIAL_OUT_CH NO. BIT2 o__| scwi SERIAL _OUT_CH_NO._BITT 0 _| scko 1 | SERIAL_OUT_CH_NO._BITO O_| SCHEN ‘SERIAL GUT_CH DATA ENABLE o_[ 0013 VOICE/MIX o 0018 PARALLEL o_[oni7 OUTPUT = _ [ss 5 0 {oie 0 0015 oO [opis 95 | 0 | on1g 96_[_0__| oni2 J | ourpur 970 | oon 36_| 0 | opto 99 0 | 009 7oo_[-o [008 101 VSS 102 oO OD7 103 | 0 _| 006 ao {08 x | ovrpur 105 {0 | ond 706 | - [vod = a | 107_|_0 | 003 108_| 0 | 002. ac x | ovrpur tio [0 _[ 000 tm _| -_[¥ss = Tiz_| 0 | ovna PARALLEL OUT 13_[-o | ovna 4 {0 __| ovn2 iso : VOICE NO. 6 0 OVNO 17_[_1_| XRD. CPU_RO_ENABLE ris_|_1_[XWR CPU_WR ENABLE 113_[_1 [xcs CHIP SELECT 320 = yoo. = 2CHECK POINT FOR MB87727 1.0VNO~OVNS (116~113pin) 2.MCK (52pin) mn i ‘in A En 2v/2us div 2V/0.2uS div 20/0. 18S diy CLASSIFICATION OF CLASSIFICATION TERNINALS TERMINALS FOR DF88 CPU INTERFACE BSEL, XCS, XRD, KWR AD~AS, D0~D15 PARALLEL OUT OSEL, OD0~OD19 MDE INTERFACE ) | OVNO~OVNA, POEN SERIAL OUT ‘SOD, SCK, SEN (WOE2 INTERFACE ) | SCHO~SCH2, SCHEN WIXER ‘[sFto=srT2, CLIP PARALLEL IN 1o0~ vig (1G, DF INTERFACE ) | IVNO~IVNA, DEN WASTER CLOCK WK RESET ARES FILTER MODE MODEO~NODET TEST MODE TEST, LTEST TSELO, TSELL POWER SUPPLY voo1 ~voD6 Yssi~vssi2 23MB87405 (MDE) PIN ASSIGNMENT 81 O KORG 887405 O° / @ @ J MB87405 (MDE) PIN FUNCTION PIN NAME | 1/0 | PIN NAME | 1/0 | PIN NAME | 1/0 80 T OE 0 SKI, SX32 0 cs 1 | We 0 | Poo~Pp19 | 1 RD 1 |Rto~ea? | a Joc 1 WR 1 | roo~Ro1g | 1/0 | RESET 1 AO~ Az 1 |oao~paig | 0 J xTL I Do~n7 1/0 | sio~sHs | 0 |tso~ts5 | 1 RAS 0 | sar 1 | vovo~vops | ~~~ CAS o jo 0 | vsso~vss7 | --~ 24CHECK POINT FOR MB87405 1.XTL (63pin) + 2.SK1 (29pin) duty cycle of 50% 1=82uS 2V/BuS div 1V/0.2uS div 3.DA4~DAI8 (114~120, 2, spin) { 4,DAI9 (4pin) 2V/2mS div 2V/10mS div 2V/5uS div 25#PD71055GB-10-3B4 (PPI) PIN FUNCTION PIN NAME | 1/0 FUNCTION PIN NAME | 1/0 FUNCTION D7~D0 | 1/0 | Data Bus RESET | 1 | Reset cs 1 | Chip Select PO7~POO | 1/0 | 1/0 Porto RD 1 | Read Strobe pir~pi0 | 1/0 | 1/0 Portt AR | | frite Strobe P27~P20 | 1/0 | 1/0 Port2 ALAQ | 1 | Address Ic --- | Internally Connected # PD65016GF (MAP260) PIN ASSIGNMENT 26#PD65016-XXX-3BA (MAP260) PIN FUNCTION PIN NO. PIN NAME 1/0 FUNCTION or 02 - 03 caso 0 coluan address strobe to D_RAM 04 RAS 0 row address strobe to D_RAM 05 ROML. 0 lower byte ROM chip select 06 ROMU 0 upper byte ROM chip select 07 RANL 0 lower byte S_RAM chip select 08 RAMU. 0 upper byte S_RAM chip select 03 AT 0 address out 10 AS. 0 address out Ww ALS 0 address out 12 ALS 0 address out 18 Ald 0 address out 4 108, 0 address out 15 16 407 0 address out 7 409 0 address out 18 PAR 0 S_RAM write enable ( protectable write ) 19 SPI 0 1/0 chip select out 20 PPI 0 PPI chip select low active 2 FOC 0 FOC chip select low active 22 sp2 0 1/0 chip select out 23 SPs, 0 1/0 chip select out 24 Mo 0 address out 25 406 0 address out 26 405 0 address out 27 Ala G address out 28 29 30 404 0 address out 31 403 0 address out 32 AML 0 address out 33 402 0 address out 34 401 0 address out 35 400 0 address out 36 NSPI 0 —ewory chip select out 37 wsP2 0 memory chip select out 38 cKor 0 clock out 39 oxi 1 clock in 40 a a WCLK 1 master clock 42 1688 0 1688 chip select low active 43 Koz 0 clock out 4 kos 0 clock out ( 1/2 CKI2 ) 45 OF88 0 DF88 chip select low active 48 NOE 0 WDE chip select low active a7 TES3 1 TEST mode active high 48 SPI 0 chip select out 43 ckoo 0 clock out aPINNO, PIN NAME 1/0 FUNCTION SSS 50 ksP 0 serial data out to key scanner (RxD) 51 KSPI I serial data in from key_scanner (TxD) 52 53 54 SCLK 0 serial clock out to key_scanner (SCLK) 55 ARES 1 reset_input low active 56 ADOo 1 address data multiplex in from VS0FDC 57 ADO1 1 address data multiplex in from V5OFOC 58 Doz 1 address data multiplex in from VSOFDC 59 DOs 1 address data multiplex in from YSOFDC 60 Dod 1 address data multiplex in from VS0FOC 61 ADOS I address data multiplex in from VSOFOC 62 DOs 1 address data multiplex in from VS0FDC 63 ADOT 1 address date multiplex in from VSOFDC 64 Dos 1 address data multiplex in from V50FOC 65 66 1 address data mult in from V5OFDC 87 ADIO 1 address data multiplex in from VSOFOC 68 ADIL 1 address data multiplex in from YS0FOC 69 ADI2 1 address data multiplex in from YSOFDC 10 ADI3 1 address data multiplex in from VSOFDC 1 ADIA | address data multiplex in from VS0FDC 72 ADIS I address data multiplex in from V50FDC B AleP 1 address in from VS0FDC 4 ALTP 1 address in from V50FDC 6 AL8P 1 address in from V50FDC 16 AISP. 1 address in from VSOFDC 1 RFRQ 1 from V50FDC 18 KIL 1 clock in 79 80 81 ASTB 1 address strobe in frou YSOFOC 82 UBE 1 upper bank enable in 83 1OWR 1 1/0 write enable in from VSOFDC 84 MAR 1 memory write enable in from V50FDC 85 10RD 1 1/0 read enable in from VS0FDC 86 WRI 1 menory read enable in from V50FDC 87 IN 1 1M D_RAW mode select (low ->1M D_RAM) 88 TESI 1 TEST MODE 89 WE 0 —-DLRAM lower byte write enable 90 TES2 [| TEST NODE $1 UWE 0 —_D_RAM upper byte write enable 92 DRAG 0 —_D_RAM address out 93 DRAL 0 —-D_RAM address out 94 DRAZ 0 —D_RAN address out 95 DRA3. 0 —_D_RAM address out 96 DRAG 0 —D_RAM address out 97 DRAS, 0 —_DLRAM address out 98 DRAG. 0 —DLRAN address out 99 DRAT 0 DRAW address out 100 cast 0 column address strobe to D_RAN 28MB635107 (WS89) PIN ASSIGNMENT MB635107 (WS89) PIN FUNCTION PINNAME 1/0 FUNCTION AS~AO 1 CPU address in o7~00 1 CPU date in XWR 1 CPU write enable xcs I CPU chip select 1vD1I9~1DVO sound data bus from TG88 IVNG~1VNO 1 voice nusber from 1688 DEN 1 data enable from 1688 (O¥EF) RAIG~RAO =—-0—TABLE_ROM address RD7~RDO 1 TABLE_ROK data ARWE 0 S_RAM write enable for TABLE_RAN XROE © S_RAM output enable for TABLE_RAN OVDI9~0YD0 0 — sound data out to DF88 OVN4~OVNO 0 voice number out to DF88 OWEF 0 data enable to DFB8 NCK I master clock XRES I system reset TESTI, 2 0 TEST NODE Tr) +5 vss cn 29MB635107 (WS89) PIN /O NO._[1/0_[ PIN NAME [ NO. [1/0 [PIN WANE TNO. [170 [PIN NANE[ NO. [1/0 J PIN NANE 1_|--- [vss 26_|1/0_| Rb4 51_|-— [ss 76_|-——_| vo0 2 [1 [40 27_| 1/0_| R05 52 MCK. 77 [0 [RAS 3t7 [a 28_|1/0_| R06 53 Tvois__| 78 | 0 | RAIO a [1 Tre 23 {1/0 [R07 54, Tvo14 73 [0 | RAIL a 30_{_ 1 _| 1WNO 55 iors | 80_| 0 | Raz a 31_|-— [ys 56 ivois_[_1_|--— | vss 71 Tas 32] 1 [avr 87 W017 820 | RAIS 8 [-— [0c 33] 1 | iwz 58 W018 83 | O_| Rad 3 [7 _fawe 34 [1 [ws 59 1wois__[ e4 [0 | Ral 10 [1 [res 35_[ 1 [iva 60 voo {5 [0 [Rais | n_[== [vss 36_[_1_[1v0 61 VSS 86_| 0 | XRWE 1 [1 {00 37_[ [ivi ez_| 1 | 0EN e7_| 0 | ¥ROE 3 [1 {or 3a_[ 1 [ivoz 63_| 1 | xres 330 ower ut [oe 39_|_1_[ v3 64_[-—- [W.C. 89_[_1_| Testo ee a 40 [1 | ivoa 65_|—— [Wc 30_[1 [Test 16_|-—— | voo 41_|-— [ss “I 66_| 0 | RAO 31 VSS: ie a a2 105 e7_| 0 [RAI gz_| 0 | ovois rs ee 4B wos [6s [oraz 98 [0 [ovis ig | 1 [06 m WoT 63_[ 0 | RA3 4] 0 | ovoi7 20 [ft [07 & _[ vos 70_|0 [RA 9 | 0 | ovbie 21_{--- [vss 46 VoD 71_|--= [vss 360 | ovois 22_[ 170 [avo | 47 10g 72_{ 0 | RAS s7_|-0 | ovo1a 23 [1/0 [ROI 48 11d | 73 | 0 | Rae 96_[ 0 | ovois 24 {1/0 | Roz 49 Woit Th iz RAT 33 [0 Ext 25 [1/0 [R03 50 woz [75 [0 [Rae yoo [0 [ovoit PIN NAME | NO. [1/0 [ PIN NAME [ NO. [170 | PIN NAME [ NO. [170 [ PIN NAME VSS 106_[--- [von 1_[---_[ vss 1i6_| 0 | OWNS ovwin {107 | 0 {ove uz | 0 |ovw2 [117 | 0 [owe ‘ovo9 108_|_0_[ 0vD5 113_|_0 | ovol 1180 __| OVNI ‘ows 103 [0 [ovba i [0 _| ovoo T19_|-o_| ono ‘ovo7 110 {0 [ovos us [0 [ova 120 vob. 30(CHECK POINT FOR MB635107 1.0018~0D0 (93~114pin) 2.0019 (92pin) 2V/5uS div 2V/5uS div 4.0VN4~0 (115~119pin) we UU WLLL] U i owe [ LTT a _f NO T_ -_ duty cycle of 50% 2V/0.5uS div duty cycle of 50% 31(MB623147U (MAP25) PIN ASSIGNMENT ey "or IO Kors onze ro ~S (MB623147U (MAP25) PIN FUNCTION No. | 1/0 | PIN NAME] NO. | 1/0 | PIN NANE] NO. | 1/0 | PIN NAME} NO. | 1/0 | PIN NAME 1 oft pias ar fb | ine ai fo four et | o [oar at | as a2 fob far 42 Jo | one ez | 0 joss a fr fia 2 ft fie 43] 0 | ons 63 | 0 {on 4a dt fis aa ft fis 44 | 0 fone 64 | 0 |onis 6 fa | rats a | 1 |i 45 | 0 | ons 65 | a foals e ft fia 2 | 1 jis 4s | 0 | one ee | 0 | com 7 fr pias a fb | uae a7 | 0 fou 67 | 0 | 1050 8 | i/o | p07 2a | i [iat 43 | 0 | ono es | o | tos a | i/o | pos 2a | t {tao 43. {1/0 | 00 6s | 0 | 10s2 10 | 1/0 | Pos 30 | 1 | MREQ 80 i/o | or 70 | 0 | 1053 um | 1/0 | pod a1 | 1 | MOE 1 five | oz 71 | 0 | tose 12 |---| vss 32 |--- | vss se |—- | vss 72 |--- | ¥ss 13 | 1/0 | pos 33 |---| voD 53 | tvo | 03 73 |--- | voo 1 [io | 34 | 1 | tost 84 Jiyo | 04 74 | 0 | 1085 18 | 1/0 | por 35 ft LR 55 | 1/0 | 05 75 | a | Nsoo 1s | 1/0 | Poo 36 | 0 | MRD 56 | 1/0 | 08 76 | 0 | uso ww fer fia 37 | 0 | MRR 87 | t/o | 07 77 | 0 | wsoz wot fin 38 | 0. | 10RD 58 | 0 | cocs 78 | 0 | Nsos ig | 1 [imo 39 | 0 | 10m 53 | 0 | oato 79 | 0 | wso6 zo ft {is 40 | 0 | oa so | a |coro |so | a | xso7 32# PD70216L-10 (CPU) PIN ASSIGNMENT uPDTO2IGL. [-—- 1 SCU | —~ SRY }+-—— map [Ey srrss-airrso I Kea ba = ast — EFRG -—_| REFU}—+#PD70216L-10 (CPU) PIN FUNCTION PIN. NAME 1/0 ADI5-ADO 1/0 A19/PS3-A16/PSO 0 REFRQ 0 HLDRQ 1 HLDAK 1 RESET 1 RESOUT 9 READY 1 NMI 1 MRD 0 MAR 0 JORD 0 1OWR 0 ASTB 90 UBE 0 BUSLOCK 0 POLL 1 BUFR/W 0 BUFEN 0 X2-X1 1 CLKOUT 0 BS2-B850 0 QS1-0s0 0 TOUT2 0 TCTL2 I TCLK 1 INTP7-INTP1 I INTACK 0 TxD 0 RxD I DAACK2-DMAACKO 0 DKARQ2-DMARQO END/TC V vo GND Ic FUNCTION Address Bus/Data Bus Address / Processor Status Refresh Request Hold Request Hold Acknowledge Reset Reset Output Ready Non Maskable Interrupt Nenory Read Strobe Nenory Write Strobe 1/0 Read Strobe 1/0 Write Strobe Address Strobe Upper Byte Enable Bus Lock Poll Buffer Read/Write Buffer Enable Crystal IN Clock Output Bus Status Queue Status Timer Output 2 Tiner Control 2 Timer Clock Interrupt from Peripherals Interrupt Acknowledge Transmit Data Receive Data DMA Acknowledge 2-0 DMA Request 2-0 End/Terminal CountCHECK POINT FOR ». PD70216L-10 1, INTP3 (39pin) 2.CLKOUT (55pin) i CSN Wie aa i | 2v/20uS div 2V/0.2uS div 8.REFRQ (Spin) 4. UBE (51pin) 2v/20us div 5.10WR (S9pin) 2N/0.5uS div 2V/0.5uS div 2v/20uS div 35‘7.MWR (6Opin) : 8.MRD (62pin) 2V/2us div 2N/0.2uS div 36FOR HARNESSES 150 —HNS=1791_ ——_—_—_———>| CNIA cNIB PHR-6 Bs20-8 A 160 CN2A cN2B NC BLK WH BLK WH BLK WH BLK WH -Nusaavow PHR-3. shieidZ\ BS20-9 160 CN3A cCNsB + BRN PHR-10 BS20-10 37210 CN4A CN4B 1 2 - 2 1B PHR-12 PANTAL 51015-1200 230 CNSA cNSB BRN 1:GRY PHR-13 PANTAIL 51015-1300 200A, | CNBA cnsB $s [enn 2 hw EHR-5: EHR-5: 38500 3 —HNS=1797_ _ A CN7A 3: WH Shield 2: NC Vi BLK EHR-3 3: YLW 2: NC Ta BLK 5195-03 300 1S. —HNS-1799_ _—_—_ CN9SA 3: BLK FE] 2: NC Te BLK VHR-3N 190 —HNS-1800__ | et CN1OA JPIN MARKING CNI1OB j PEIN MARKING _ tre ———$ $$ “88 vv g 5320-20aT2 5360-20AT uu at8. PARTS LIST PART CODE PART NAME/SPECIFICATION P.C.BOARD NOTE q’Ty 001157600 P.C. BOARD ASSEMBLY KLM-1576 1576 1 001157700 P.C. BOARD ASSEMBLY KLM-1577/78/79 1577-78 1 002158000 POWER SUPPLY UNIT KLM-1580 CSA/JU K.PART TUS 1 W.PART 100JP 1 W. PART LI7EX 1 W. PART LI7eN 1 002158100 POWER SUPPLY UNIT KLM-1681 E W. PART 220GE 1 W.PART 240K 1 ¥. PART 230SC 1 W.PART 23096 1 W. PART 230SE 1 M.PART 230FR 1 M.PART 230GE 1 PART 240AF 1 |. PART 240AU 1 WM. PART 240GE 1 139010012 BLOCK R RGLD5X103J 10K 1576 1 139010013 BLOCK R RGLD8X103J 10K 1576 2 139010014 BLOCK R RGLD8X472J 1576 2 140010012 BLOCK CR CRDGO4 (100 OHM 300PF) 1576 4 184050222 FUSE R RF73B2ATD 22 OHM J 1576 8 219401400 EMI FILTER DST310-92D223S50 1576 3 264003456 PPC 100V S600PF J APSV 1576 4 304000070 TR 2SA812-T1 (N5~7) 1576 1 304020150 TR 2801623-T1B (L7) 1576 1 304020230 TR 2SC3661-TA/TB(3K) 1576 4 304030130 TR FAIA4N-TIB 1576 8 304030140 TR FNIA4M-T1B 1576 5 304060070 FET 2SK438-T12-1C 1576 4 912007800 LED GL3HD8 1577-79 12 912010800 LED GL3ED8 1577 1 813002400 314000300 DIODE 15-2473 1-77 1577 37 314001400 DIODE RLS-73 TE-11 1576 8 815000500 DOUBLE DIODE WC~2840-T12-1 1576 2 320001261 IC UPD71055GB-10-384 1576 PPI 1 320001283 — 1C UPD65016GF-058~3BA 1576 MAP260 1 320001383 1C UPD70216GF-10-388 1576 cruPART CODE PART NAME/SPECIFICATION P.C. BOARD NOTE Ty 820003202 IC TC511664BZ-10 1578 S_RAM 1 320011026 1 M5216L~600Y 1576 OP. ANP 1 820011141 1C MSN27C201K-15 1578 EP_ROW 1 320011152 IC M37450K4-616FP 1576 KsP 1 320012052 —1C MB87405PF (QFP120) 1576 MDE 1 320012086 IC MB81464-10PSZ (ZIP) 1576 D_RAM 5 320012072 1 MB623147PF (QFP80) 1576 WAP25 1 320012084 IC MB87726PF (QFP160) 1576 1688 1 920012085 IC MB87727PF (QFP120) 1576 DF88 1 320012092 1 MB635107PF-G-BND 1576 wss9 1 320012120 IC MBN27C1001-152-G 1576 EP_ROM 1 320036005 IC PCNSSHP. 1576 pac 1 324001008 IC UPD74NCUOAGS-E2 (sop) 1576 HC-KOS 1 324001018 IC UPD74HC4053GS-E2(SOP) 1576 He-KOS 3 324001034 IC UPD23CB001EGW-338-E2 1578 WAVE ROM 1 824001085 IC UPD23C8001EG#-333-E2 1578 WAVE ROM 1 324001037 IC UPD43256AGU-10/12L-E2 1576 S_RAN 3 324004004 1 HD74HC32FPER 1576 HC-KOS 1 324004012 IC HD74HCOBFPER 1576 HC-nOS 1 324004050 IC HO74HC138FPER 1876 HC-NOS 1 924004092 IC HD74HC245FPER 1576 4HC-MOS 1 324009004 IC NJM7BLOSUA 1578 REGULATOR = 1 924009005 IC NJN79LOSUA 1576 REGULATOR = 1 324009013 IC NJN2088MD-TE3 1578 OP. AMP 8 824011002 IC M5223FP-600C (8P SOP) 1578 OP. AMP 1 324011005 = IC M5238FP-600C (8PSOP) 1576 OP. AMP 3 924011006 IC M5218FP-600C (8PSOP) 1578 OP. AMP 1 924011013 — 1C M62021FP-600C 1576 RESET 1 324011015 —1¢ M74HCOSFP-31B (SOP) 1578 HC-MOS: 1 324012002 IC MB838000-20PF-G-4A7-EF 1578 WAVE ROM 1 324012003 1C MB838000-20PF-G~4A8-EF 1576 VE ROM 1 324012004 1 NB838000-20PF-G-4A9-EF 1576 WAVE ROM 1 324012005 1 MB838000-20PF-G-5A0-EF 1576 WAVE ROM 1 324018001 IC LHSS1APG 1576 WASK ROM 1 334000500 SB COIL SBT-0260 TF 1576 1 1577-79 15 334000800 PHOTO COUPLER PC-410K-TP 1576 1 335006000 CRYSTAL OSC. AT-49 20. 0ONHZ 1576 1 335006600 CRYSTAL OSC. AT-49 32MHZ 1576 1 350002347 SEMI FIXED VR RHO6I5SC S4 47K 1576 1 362005300 = VR RKO971220045A 10KBX2 1577-79 1 365009000 SLIDE VR RSSO111ACO19A 10KB(X-142) 1877-79 1 375006100 POWER SW SDDLBI M.PART 1 375010500 TOUCH SW EVQ-PACOSK-A 1577-78 37 aPART CODE PART NAME/SPECIFICATION P.C.BOARD NOTE QTy 400012500 INVERTER TRANSFORMER TA-042 1576 1 454008000 PHONE JACK YKB21-5138 1577-79 1 471060500 CONNECTOR TOP BSB-EH-A 1576 1 471070300 CONNECTOR TOP B3B-PH-K-S 1576 1 471070800 CONNECTOR TOP B8B-PH-K-S 1576 i 471070300 CONNECTOR TOP B9B-PH-K-S 1576 1 471071000 CONNECTOR TOP B10B-PH-K-S 1676 1 471071200 CONNECTOR TOP B12B-PH- 1576 1 471071300 CONNECTOR TOP B13B-PH-K-S 1576 1 474011300 CARD CONNECTOR HGCO338-01-010 1576 1 474014400 HEADER 20P 5332-2072 1576 1 474015400 CARD CONNECTOR FCN-565P068-G/C 1576 1 475001791 HARNESS HNS-1791 (BOARD IN) 1577-73 1 475001792 HARNESS HNS~1792 (BOARD IN) 1877-79 1 475001783 HARNESS HNS-1793 (BOARD IN) 1577-79 1 475001794 HARNESS HNS-1794 (BOARD IN) 1577-79 1 475001795 HARNESS HNS~1795 (BOARD IN) 1577-79 1 475001796 HARNESS HNS-1796 W.PART 1 475001797 HARNESS HNS-1797 M. PART 1 475001738 HARNESS HNS~1798 M.PART 1 475001799 HARNESS HNS-1799 W.PART 1 475001800 HARNESS HNS~1800 M.PART 1 480001324 IC SOCKET 32P DICF-82CS-E 1576 2 480010200 SP DIN JACK SOCKET YKF51-504 1577-79 1 00012900 —X-631 RUBBER SPACER M.PART. 1 500018300 RUBBER FOOT 3x22x3 M.PART 4 520001700 LITHIC BATTERY CR2032 1576 1 525000400 EMI FERRITE 2643-480102 W.PART 1 525000800 DATA LINE FILTER ESD-R-16 W.PART 1 540012800 INLET SOCKET PA-125-BS W.PART 240K i 540012400 INLET SOCKET PA~125-10 WM. PART 240GE 1 W. PART 220GE 1 M. PART 24040 1 WM. PART LITEX 1 M.PART 100JP 1 WM. PART 1170N 1 M.PART 230GE 1 M.PART 2404F 1 M. PART 230FR 1 M. PART 1170S 1 M.PART 230SC 1PART CODE PART NAME/SPECIFICATION P.C.BOARD NOTE ary 540012400 INLET SOCKET PA~125-CU MW. PART 23006 1 M.PART 280SE 1 575015000 LED SPACER LS-15-6.5 L= 1577-79 1 575015900 LED SPACER LS-15-8 1577-79 12 600003200 AC CORD UC-948-J02 M.PART LITEX 1 600003300 AC CORD UC-953-JO1 W.PART 117US 1 M.PART 1ITCN 1 600003500 AC CORD SC-321-JO1 M.PART. 240A 1 600003800 AC CORD DC-480-Jo1 M.PART 100JP 1 600004700 AC CORD EC-652-E03 M.PART 230FR 1 M.PART 230GE 1 M.PART 23086 1 MPART 240AF 1 M.PART 230SC 1 M.PART 240GE 1 M. PART 220GE 1 600004800 AC CORD EC-472-JO1 W. PART 230SE 1 600004900 AC CORD BH-322-JO1 M. PART 240UK 1 620022500 SLIDE VR KNOB W.PART 1 620023100 X-952 POWER SW KNOB W.PART 1 620023600 + X-943 VR KNOB M.PART 1 630017200 X-142 LCD WINDOW M.PART 1 640094800 X-631R UPPER CASE M.PART 1 X-052 VR SHIELD 1577-79 1 X-943 JACK PLATE W.PART 1 RACK MOUNT ADAPTER M.PART 2 X-142 FRONT PANEL ASSEMBLY X-142 FRONT CHASSIS X-142 LOWER CASE X-011/012 CARD GUIDE 646039500 X-011/012 CARD SLOT M. PART 1 649007400 BATTERY HOLDER 1576 1 43VAROITUS Paristo voi rjahtaa, jos se on virheellisesti asennettu. Vaihda paristo ainoastaan laitevalmistajan suosittelemaan tyyppiin. Havita kaytetty paristo valmistajan obj mukaisesti. ADVARSEL! Lithiumbatteri — Eksplosionsfare ved fejlagtig handtering, Uadskitning ma kun ske med batteri af samme fabrikat og type. Levér det brugte batter’ tilbage til leverand @ ren. ADVERSEL Lithiumbatteri ~ Eksplosjonsfare. Ved utskifting benyttes kun batteri som anbefalt av apparattabrikanten. Brukt batteri returneres apparatieverand @ ren. VARNING Explosionsfara vid felaktigt batteribyte. Anvand samma batterityp eller en ekvivalent typ som rekommenderas av apparattiliverkaren, Kassera anvaint batteri enligt fabrikantens instruktion. CAUTION Danger of explosion if battery is incorrectly replaced Replace only with the same or equivalent type recommended by the equipment manufacturer . Discard used batteries according to manufacturer 's instructions,KORG INC. 15-12, Shimotak Tokyo 168 © KORG INC. 1992 (0402 CEH. PRINTED INJAPAN © chome, Sugi