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Question Paper Code:

M.E. / M.Tech. DEGREE END- SEMESTER EXAMINATION, DEC. 2013 & JAN. 2014.
Third Semester
P13VDE01 – Testing of VLSI Circuits
(Regulation 2013)
Time: Three hours Maximum: 100 marks
PART – A
Answer ALL Questions (20 x 1 = 20 marks)
(Objective type with every wrong answer carrying ¼ Negative Mark)
1. The logic value at a point in a circuit to become opposite to the specified value called------
a) Non logical fault
b) Logical fault
c) Failure
d) Bridge default
2. Unintended shorts between the lines from a class of permanent faults are ------------
a) Stuck at 0
b) Stuck at 1
c) Bridging fault
d) Feedback bridging
3. Transient faults are usually caused by ----------
a) Loose connection
b) Power supply fluctuation
c) Poor design
d) Temperature variation

4. A combinational circuit that contains an undetectable stuck fault is said to be ---------

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 a) Irredundant
b) Redundant
c) Modular redundancy
d) Concurrency
5. Fault diagnosis includes ---------
a) Fault detection
b) Fault location
c) Both (a) and (b)
d) Fault coverage
6. To generate test for non redundancy combinational circuits are -----------
a) PODEM
b) FAN
c) D- algorithm
d) CAN
7. Which technique to reduce the no of back tracks that must be made during search process
---------
a) D-Algorithm
b) FAN
c) PODEM
d) RMD
8. RME technologies can be used to realize any arbitrary n-variable Boolean function using
---------
a) AND-OR
b) AND & EX-OR
c) Universal gate
d) AND -OR-NOT

9. LSSD stands for ---------

a) Level Scan Sensitive Design

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 b) Low Scan Synthesis Design
c) Level Sensitive Design
d) Low Sensitive Scan Design
10. The ability to determine the signal value at any node in a circuit by controlling the circuit
inputs called -----------
a) Observability
b) Controllability
c) Predictability
d) Testability
11. ---------- leads to synchronization problems similar to those caused by one shots.
a) Global clock
b) Free running oscillation
c) Asynchronous circuit
d) Monostable circuit
12. Classical scan design uses a -----------
a) D-FF
b) SR FF
c) Race less master – slave D FF
d) JK FF
13. BIST approach improves the -------------
a) Controllability
b) Observability
c) Both ( a ) & ( b)
d) Predictability

14. ATE stands for ------------

a) All Test Equipment
b) Automatic Test Equipment
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 c) Automatic Time Equipment
d) Automatic Tree Equipment
15. A modified form of exhaustive testing is -------------
a) Pseudo – exhaustive
b) Autonomous testing
c) Pseudo- random
d) Deterministic testing
16. In an LFSR, the outputs of a selected number of stages are fed back to the input of the
LFSR through -------------
a) AND – OR network
b) EX- OR network
c) UNIVERSAL network
d) NOR – OR network
17. Testing and diagnosis process maintained by -----------
a) COMET
b) COE
c) UUT
d) ATE
18. The faults can be automatically detected by a sub circuit called a ----------------
a) Detector
b) Self checking
c) System level checking
d) Parity checking

19. --------------- testing to detect the output errors immediately upon occurrence, thus
preventing possible corruption of data.
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 a) On-line
b) Off line
c) Self
d) Odd parity
20. ---------------- Diagnosis developed by PMC model.
a) System level
b) Logic level
c) Fault level
d) Self checking

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 PART – B

Answer ALL Questions (10 x 2 = 20 marks)

(Objective type with every wrong answer carrying ½ Negative Mark)
21. Two faults f and g are said to be functionally equivalent if -----------
a) Zf (t) equal to 0
b) Zf(x) equal to Zg(x)
c) Zf(t) not equal to Zg(t)
d) Zg(t) equal to 1
22. The condition for fault dominance is -----------
a) Tg equal to Tf
b) Tg is greater than or equal to Tf
c) Tg is lesser than or equal to Tf
d) Tg equal to 0
23. A collection of status of the machine to contain the present state is ---------
a) Uncertainty
b) Vector sequence
c) Homing sequence
d) Homing tree
24. ---------------- that allows to generate test for a group of faults .
a) Initial test
b) Synchronous simulator
c) Concurrent simulator
d) Sequence simulator
25. ----------- register contains all the original storage cells in the circuit.
a) Shift
b) Scan
c) Left shift
d) Universal

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26. The number of level tests are required to check the board level testing in identifying a
faculty board ---------
a) 10 to 30 times
b) 10 to 20 times
c) 40 to 50 times
d) 20 to 40 times
27. The syndrome of a Boolean function is -------------
a) S=1/2n
b) S= K/2n
c) S= 2n
d) S= K2.2n
28. In circular BIST---------- is the circuit under test without certain selected memory elements.
a) Logic module
b) Circular FF
c) Sync- module
d) Asynchronous-module
29. ----------- is to back trace an error from the binary output where it has been observed during
edge pin testing to physical fault.
a) Guided probe testing
b) Fault diagnosis
c) Fault dictionary
d) Unit under test
30. The independent checking process the no. of check bit is -------------
a) P= log2 m
b) P= 2 log m
c) P=1/log2m
d) P= log m

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 PART – C

Answer ALL Questions (6 x 10 = 60 marks)

31. a) Analyze the stuck at 0, stuck at 1 & bridge fault models in digital circuits.
a) (Or)

b) Explain the serial and parallel fault simulation algorithms.

32. a) Determine the tests for checking all single node faults F=x1’x2x3+ x1x2’x3.

(Or)

b) ) Derive the decision tree in PODEM algorithm.

33. a) How to improve the testability in Ad-hoc design rule?

(Or)

b) Explain the classical scan based design.

34. a) Explain the test pattern generation for Built In Self Test.

(Or)

b) Explain the Muxed-D Scan Cell, Clocked-Scan Cell & LSSD Scan Cells.
35. a) Design and test the Pseudo-Random Pattern generator.

(Or)

b) Explain the challenges in fault diagnosis for yield improvement.

36. a) Design a self checking circuit with one example.

(Or)

b) Analyze the scan chain Diagnosis flow model.

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