Course Name: TIA Basic with STEP7 1.1. CPU Block Diagram AccU1(32BITS) [ACCU 2(32 BITS) EW SaTS iory ‘Sub Modul (Flash Eprom) [MPI Port Analog] [Functior [Modules |Modules| [Al & AQ] P-bus: In $7-300/400 system main processor talks to the periphery (i.e. Dl, DO, Al, AQ and function modules) via the P-bus. This bus is serial in case of $7-300 and parallel for S7-400, Its also called as backplane bus. K-bus: The communication of CPU to outside devices is through K bus (MPI, S7 communication ete.). The P bus and K bus are handled by separate processors inside the CPU. ROM: The ROM consists of operating system of CPU (i.e. Step 7) or itis also called as firmware. It also consists of system functions and function blocks. This cannot erase by memory reset to the CPU. It does not required battery backup. User does not have any access to the ROM of CPU. Memory Sub module: To store user program there is a slot on CPU for flash memory module. This can be EEPROM for 7-300 and flash RAM or flash EEPROM for S7-400. Copying of data from memory card to CPU or CPU to memory card is possible. Registers: There are different registers inside the CPU for data handling and for control functions, The detail about all Registers and their structure will be discussed subsequently. Accumulator 1 and 2: There are two 32 bit registers inside the CPU for performing all logical and arithmetic operations, But itis always possible to load Byte Word and Dword data into them, They are called as accu’ and accu2. In $7-300 system has only two accumulators but $7-400 has four accumulators. After loading a data into them for any operation always goes as right justified means that LSB is to the right hand side and MSB to the left hand side. It is also possible to exchange the data among the accut & accu2 by instructions, The result of the instruction is always in accumulator 1 and can be a1 amedtoan 24 23 tion 1615 87 ° ACCUT-HH ACCUT-HL ACCUTLH ACCUTLL ‘ACCU 1-High Word ACCU 1-Low Word SITRAIN_INDIA Course flder, v1.0 wsCourse Name: TIA Basic with STEPT Address Register 1 and 2 (AR1 And AR2): These two registers are also 32 bit registers They can be used to define pointer in indirect addressing, The data stored in them is always with Byte number, Bit number format. DB Registers: When any DB (shared DB or Instance DB ) is open ,then open DB number gets loaded into these registers automatically by the CPU. They are also 32 bit registers. If you require knowing the number of open DB, you can access these registers by means of instruction, Status Word (STW) and Meaning of Bit Assignment] Value Meaning ° ix 20 First check bit 1 RLO 2 Result of logic operation 2 STA 2? Status 3 OR 2 Or 4 os 24 Stored overflow 5 ov 2 Overflow 6 cco 26 Condition code 7 cc 27 Condition code 8 BR 2 Binary result 15 Unassigned| 2° ..21° IFC - First Check Bit (Status Word, Bit 0): The /FC bit signal state controls a logic operation string. Each logic operation queries the /FC bit signal state and the addressed contact. If the /FC bit signal state equals "4," an instruction logically combines the result of its signal state check on its addressed contact with the RLO generated since the first check and stores the result in the RLO bit. If the /FC bit signal state equals “0,” the logic string begins with a first check RLO - Result of Logic Operation (Status Word, Bit 1): The RLO bit stores the result of a logic operation string or comparison instruction, The RLO bit is status word bit 1,The first instruction in a segment checks the contact signal state. The RLO is set to "1" ifthe check is executed. The second instruction also checks the contact signal state, This check result is now combined with the value stored in the RLO bit according to the Boolean algebra rules and stored in the RLO bit. This logic string ends after an assignment or a conditional jump. Depending on the RLO bit value, an assignment or a conditional jump is executed. STA. Status Bit (Status Word, Bit bit logic instruction that performs a read access to memory (A, AN, O, ON, X, or XN) is always the same as 2): The STA bit stores the value of an addressed bit. The status of a the value of the addressed bit. The status of a logic instruction that may perform a write access to the memory (R, S, oF =)is the same as the value of the written bit or, if writing is not performed, the same as the value of the addressed bit. The status bit has no significance for bit instructions that do not access the memory. These instructions set STA to 1. The status bit is not read by instructions, itis interpreted for you when viewing the online status of program variables. SSITRAIN-INDIA 1-2 Course folder, V1.0Course Name: TIA Basic with STEP7 OR - (Status Word, Bit 3): The OR bit is used for combining AND functions before OR functions. The OR bit s set if the RLO of the AND logic operation is 1. This anticipates the result of the OR logic operation, Every other bitprocessing instruction resets the OR bit OS - Overflow Stored (Status Word, Bit 4): The OS bit stores the OV bit if an error occurs during math instructions or comparison instructions with floating point numbers. The OS bitis set, together with the OV (Overfiow) bit, in the event of a fault. Itremains set after the fault has been eliminated. It thus stores the OV bit status and indicates whether or not a fault has occurred in one of the previously executed instructions. The following commands reset the OS bit: JOS (Jump if OS=1), Block call instructions, Block end instructions, OV - Overflow (Status Word, Bit 5): The OV bit displays errors for math instructions or comparison instructions with floating point numbers, Itis set by a math instruction with floating point numbers after a fault has occurred (overflow, illegal operation, comparison unordered). The OV bit is reset when the fault is eliminated, CC 1, CC 0 - Condition Codes (Status Word, CC 4 and CC 0 bits provide execution results for: its 6 and 7) + Bit Logic instructions + Comparison instructions + Math instructions + Shift and Rotate instructions + Word Logic instructions Note : CC 1 and CC 0 can also be read by conditional jump instructions. BR - Binary Result Bit (Status Word, Bit 8): The BR bit forms a link between the processing of bits and words. This bit enables your program to interpret the result of a word logic operation as a binary result and to integrate this result in a binary logic string. For example, the BR bit makes it possible for you to write a function block (FB) or a function (FC) in Statement List (STL) and then calls the FB or FC from Ladder Logic (LAD). When writing a function block or function in STL that you want to call from LAD, you have to store the result ofthe logic operation (RLO) in the BR bit in order to provide the enable output (ENO) for the Ladder box. You do this using the SAVE, JCB, JNB instructions. When you call a system function block (SFB) or a system function (SFC) in your program, the SFB or SFC indicates whether the CPU was able to ‘execute the function with or without errors by providing the following information in the binary result bit + Ian error occurred during execution, the BR bit is “0” + Ifthe function was executed with no error, the BR bitis "1". SITRAIN_INDIA Course flder, v1.0 13Course Name: TIA Basic with STEPT 1.2 CPU: Memory Areas cpu Pll and PIQ Timers RAM Counters OR ™ Bit Memory EEROM "| ot Local Stack Retontive Interrupt Stack Load Memory Block Stack Flash Memory Integrated Integrated Diagnostic Buffer tobe plugged. in Load Memory ‘Work Memory ‘System Memory CPU Load Memory: The load memory is used to store the user program without the symbol table and the comment (these remain in the memory of the programming device). Blocks that are not marked as required for startup will be stored only in the load memory. The load memory can either be RAM, ROM, or EPROM memory, depending on the programmable controller. The load memory can also have an integrated EEPROM part as well as an integrated RAM part (for example, CPU 312 IFM and CPU 314 IFM). In S7- 400, its imperative that you use a memory card (RAM or EEPROM) to extend the loadl memory CPU Work Memory: The work memory (integrated RAM) is used to store the parts of the user program required for program processing, CPU System Memory: 4. Plland PIQ: Process image memory areas are updated cyclically by the operating system. At the beginning of a cyclic scan, signal states are transferred from input modules (peripheral input - Pl area) to the process image input table (PII area); at the end of each program scan, signal states are transferred from the process image output table (PIQ area) to output modules (peripheral output - PQ area). This process image is buffered by /O hardware during each Statement List scan. l-area bits of the process image are therefore stable for every statement reference. Although area bits of the image may be assigned diferent states during a program scan, only the last signal state is actually sent to the output module. The normal way for your program to read from or Ute to YO modules isto use the process image (I and Q area addressing). Exceptions: ‘+ Direct /0 addressing in the peripheral area memory (P area) + Use of functions which immediately process 1/0 data 2, Timer / Counter Area: There are software timers and counters available in the system memory area, The size of each timer and counter is 16 bit (word). They need to access in user program by ‘means instruction. Their number depends on CPU 3. Bit Memory: Itis memory to store intermediate results. Itis abbreviated by M. The size is CPU specific. This is accessible to all the blocks. It can be used as Bit, Byte, Word or DWord SITRAIN-NDIA, 14 Course folder, V1.0Course Name: TIA Basic with STEP7 Example: A Moo, L MBO L Mwo, L mDo Retentive Memory: The retentive memory is a non-volatile RAM used for backing up bit memories, timers, counters and data blocks even if there is no backup battery. You specify the areas to be backed up when assigning the CPU parameters. Local Stack: This is also a part of system memory used to store intermediate results. But itis valid only for that block, Itis not a global like Bt memory .This can be used as Bit, Byte, Word or DWord. Example: A Loo LL LBo L wwo Luo Diagnostic Area: To store diagnostic data like ISTACK, BSTACK or Diagnostic Buffer CPU has space in system memory. This can be seen with the help of module Information. Dividing Up the User Program: To ensure fast execution of the user program and to avoid unnecessary load on the work memory that cannot be expanded, only the parts of the blocks relevant for program execution are loaded in the work memory. Parts of blocks that are not required for executing the program (for example, block headers) remain in the load memory. The following figure shows a program being loaded in the CPU memory. Load Memory Structure: The load memory can be expanded using memory cards. The load memory can also have an integrated EPROM part as well as an integrated RAM part in S7-300 CPUs, Areas in data blocks can be declared as retentive by assigning parameters in STEP 7 In $7-400 CPUs, its imperative that you use a memory card (RAM or EPROM) to expand the load memory. The integrated load memory is a RAM memory and is mainly used to reload and correct blocks. With the new S7-400 CPUs, additional work memory can also be plugged in Load Memory Behavior in RAM and EPROM Areas: Depending on whether you select a RAM or an EPROM memory card to expand the load memory, the load memory may react differently during downloading, reloading, or memory reset. SITRAIN_INDIA, Course flder, v1.0 18Course Name: TIA Basic with STEPT ‘The following table shows the various loading methods: jemory Type jethod of Loading [Type of Loading Downloading and deleting Ram IPG-CPU connection Individual blocks Downloading and deleting an fontire S7 program, IPG-CPU connection Reloading individual blocks |PG-CPU connection integrated (57-300 only) or Pownloading entire S7 IPG-CPU connection plug-in EPROM rograms Downloading entire S7 [Uploading the EPROM to the PG and inserting] Plug-in EPROM rograms the memory card in the CPU [Downloading the EPROM to the CPU Programs stored in RAM are lost when you reset the CPU memory (MRES) or if you remove the CPU or RAM memory card. Programs saved on EPROM memory cards are not erased by a CPU memory reset and are retained even without battery backup (transport, backup copies). Retentive Memory Areas on $7-300 CPUs: If a power outage occurs or the CPU memory is reset (MRES), the memory of the $7-300 CPU (dynamic load memory (RAM), work memory, and system memory) is reset and all the data previously contained in these areas is lost. With S7-300 CPUs, you can protect your program and its data in the following ways: + You can protect all the data in the load memory, work memory, and in parts of the system memory with battery backup. * You can store your program in the EPROM (either memory card or integrated on the CPU, refer to the "S7-300 Programmable Controller, Hardware and Installation” Manual), + You can store a certain amount of data depending on the CPU in an area of the NVRAM. Using the NVRAM: Your S7-300 CPU provides an area in the NVRAM (non-volatile RAM) (see figure below). Ifyou have stored your program in the EPROM of the load memory, you can save certain data (if there is a power outage or when the CPU changes from STOP to RUN) by configuring your CPU accordingly. Dynamic Configurable Load Memory Work Memory System Memory NVRAM Memory Static load Memory : To do this set the CPU so that the following data are saved in the nonvolatile RAM + Data contained in a DB (this is only useful if you have also stored your program in an EPROM of the load memory) + Values of timers and counters, SSITRAIN-INDIA 1-8 Course folder, V1.0Course Name: TIA Basic with STEP7 + Data saved in bit memory. (On every CPU, you can save a certain number of timers, counters, and memory bits. A specific number of bytes is also available in which the data contained in DBs can be saved ‘The MPI address of your CPU is stored in the NVRAM. This makes sure that your CPU is capable of communication following a power outage or memory reset. Using Battery Backup to Protect Data: By using a backup battery, the load memory and work memory are retentive during a power outage. If you configure your CPU so that timers, counters, and bit memory are saved in the NVRAM, this information is also retained regardless of whether you use a backup battery or not Configuring the Data of the NVRAM: When you configure your CPU with STEP 7, you can decide which memory areas will be retentive. The amount of memory that can be configured in the NVRAM depends on the CPU you are using. You cannot back up more data than specified for your CPU. Memory Management and Execution inside the CPU: The user memory comprises of: Integrated into the CPU Load memory Plug-in ‘execution relevant integrated RAM memory cord Car FBx Various capacitios Selectable High-Speed Work Memory on CPU Contains ONLY the Execution oBy Relevant sections of the Blocks in ae the Load Memory. Load memory Work memory SITRAIN_INDIA Course flder, v1.0 wrCourse Name: TIA Basic with STEPT ‘87-300 Storage Concept with CPUs 313,314,315,316 & 314IFM: Non-Volatile Memory Slot for Memory Card Main Memory “akBytes with 128KBytos CPU 314 ¢ Flas GPU S14 48/64 KB CPU 315, PRP CPU sts ren 724132 KB CPU 314 72 Bytes CPU 313, ‘12KBytes CPU 313 G care DB Marker Counter Timers MCc7- Code Seq-relevant code H@ =P} seq-relevant data soRow | ‘Ace A 192KBytes GPU 31 et System Memory per he 80/96 KB CPU 315 40/48 KB CPU 314 Output signals 20KBytes CPU 313 (\ mS Digital /O periphery l Bit Memory ‘SystemDataBlock Counters Code Blocks Data Blocks Timers Local Data RAM-Load Memory SSITRAIN-INDIA Course folder, V1.0