POWER OPTIMIZATION IN CA ADC DESIGN

Ovidiu Bajdechi, Johan H. Huijsing Georges Gielen

Delft University of Technology, Katholieke Universiteit Leuven,

Mekelweg 4, 2600GA Delft, Kasteelpark Arenberg 10,
The Netherlands B-3001 Leuven, Belgium

O.Bajdechi@ITS.TUDelft.NL

Abstract: A power optimization method for sigma-delta (EA) analog-to-digital converters (ADCs) is presented. System-
level considerations are taken into account to maximize the peak signal-to-(noise+distortion) ratio (SNDR) versus power
consumption. Both continuous-time (CT) and discrete-time (DT) loop filters are analyzed. The power consumption of
CT and DT integrators is calculated and the best combination of CT/DT integrators is used. This concept is applied in
designing a mixed CT/DT EA ADC for telephony applications. The ADC has a power consumption of only 1.7mW
while operating with a single supply voltage of 1.8V. A bandgap reference is integrated on-chip to reduce the number of
external connections.
1. INTRODUCTION no longer purely CT or DT, but a combination of the two
in order to make use of the low power consumption of CT
Among the architectures of analog-to-digital converters circuits and high SNDR achievable with DT systems.
(ADC), EA modulators are present in a large class of A EA ADC designed using this method is presented.
applications covering the frequency spectrum from low- The circuit has a power consumption of 1.7mW from a
frequency [13 and audio [2] to RF intermediate frequency 1.8V supply and can be used to directly convert electret
[3] and digital video [4]. The property of EA ADCs to microphone signals (i.e. no amplifier is required). Its
trade speed for accuracy makes them more attractive in topology includes a low-pass anti-aliasing filter charac-
the context of present CMOS technology evolution [5]. teristic, which is important when no other filters are avail-
able in front of the converter. No addi'tional components
The spread of EA designs and the absence of an accu-
are needed in order to generate a digital equivalent of the
rate analytical model for their non-linear behavior caused
audio signal. A bandgap reference is integrated on-chp
a rapid evolution of dedicated simulation software. Cir-
to reduce the number of external connections. The use
cuit level simulations are only practical once the archi-
of a CT first integrator in the EA ADC helps reducing
tecture level specifications are clearly defined. There-
the power in the voltage reference buffer by reducing the
fore, a number of simulators have evolved, some of them
dynamic performance required from it. The DT nature
as free software tool-boxes [6] and some available from
of the loop filter still offers high-DR performance. For
universities [7] [SI. Many designers or companies also
a signal bandwidth of 1lkHz, the ADC attains 80dB DR
write their own dedicated simulators. Usually, the behav-
and 62dB peak SNDR with a peak input signal amplitude
ioral simulation software is used to analyze a set of loop
archtectures in terms of dynamic range (DR) and peak of 125mV, centered on the ground voltage rail.
SNDR, then circuit simulations are performed to achieve Next section presents architecture-level considerations
the required performance for the operational amplifiers, for both CT and DT loop filters, comparing their attain-
digital-to-analog converters (DACs) and all the other ana- able peak DR and SNDR. Section 3 introduces the power
log sub-blocks. Reducing the amount of circuit-level sim- consumption models for each integrator type. Section 4
ulation time is critical for rapid time-to-market and can contains a detailed description of the EA ADC designed
only be attained by better analytical models of EA ADC for the telephony application and Section 5 presents the
building blocks. experimental results for the designed ADC. The conclu-
sions are presented in Section 6.
This paper presents complete analytical power con-
sumption models for the most used CT and DT integra-
tors, namely resistor-capacitor (RC) and switched capac- 2. ARCHITECTURE-LEVEL DESIGN
itor (SC) circuits. The models are derived by completely
constraining the design with performance requirements The architecture of a fourth order, single-loop, single-bit
which are used to calculate the power consumption of the EA ADC is shown in Fig. 1. The loop filter is defined by
operational amplifier present in such integrators. Prior the four integrators denoted by the blocks marked
to applying the models, the archtecture is chosen from a l / ( Z - l ) . . . a 4 / ( 2 - 1 ) along withthefeedbackcoeffi-
behavioral-level simulations of both CT and DT loop fil- cients f l . . j4 and the feed-forward coefficients bl . . . b3.
ters. Power consumption models are used on designed The only non-linear element in the architecture, the 1-bit
architectures to select the best option. The loop filter is comparator, is used to quantize the output of the loop fil-

0-7803-7503-3/02/$17.00 02002 IEEE DSP 2002 - 353

 Fig. 1. EA ADC archtecture used in this study
ter and thus generate a digital bit-stream which contains
both the input signal and the shaped quantization noise
introduced by the quantizer due to its coarse resolution
[9], in this case one bit.
When analyzing such a feedback architecture using
the linear approximation (i.e. neglecting the non-linear
effect of the quantizer), two transfer functions are cal-
culated: the noise transfer function (NTF) which shows
how quantization noise is filtered when passing from the
output of the loop back to the input of the quantizer, and
the signal transfer function (STF) whch shows the filter-
ing of the input signal from the ADC’s input to the input
of the quantizer. For a low-pass ADC, the NTF has a
high-pass filter characteristic while the STF has a low-
pass characteristic. In the architecture shown in Fig. 1,
the use of both feedback and feed-forward coefficients of-
fer a better control of both NTF and STF filtering charac-
teristics. Reducing the number of loop filter coefficients
could reduce system complexity and maybe even power
consumption, but would produce an STF characteristic
more or less dependent of the NTF [2].
2.1. Nonlinear Loop Effects
Linear analysis of EA ADC architectures helps defining
the target DR by good modeling of quantization noise fil-
tering through the NTF. The quantization noise can be
approximated by white noise when input signal ampli-
tude is extremely low. But at h g h input signal ampli-
tudes the approximation no longer holds, as the quantiza-
tion noise becomes correlated with the input signal. The
correlation is introduced by the quantizer non-linearity
and only time-domain simulations of the E A loop can
reveal it. Therefore, the linear approximation holds up
2
I I
1 .oo 1.20 1.50 2.00
INTFl max
Fig. 2. Performance of EA ADC with discrete-time loop
filter for a 4th order, 1-bit, single-loop architecture
DSP 2002 - 354
v I
1 .oo 120 1.50 2.00
INTF( max
Fig. 3. Performance comparison of the 4th order, I-bit,
single-loop archtecture with CT and DT loop filter
to an input which is at the overloading level (OVL), a
measure of EA loop’s stability. The overloading level
of the fourth order architecture with a DT loop filter is
shown in Fig. 2 as a function of the peak magnitude of
NTF. The peak SNDR for an oversampling ratio of 64
(signal bandwidth 128 times lower than the sampling fre-
quency) and the value of the first integrator coefficient al
are shown in the same graph. The data was generated us-
ing an automated design software (developed in-house)
and shows how the aggressivity of NTF filtering affects
loop stability. The figure clearly shows that only a certain
range (dependent on loop architecture) of peak NTF mag-
nitudes can be used. Outside this region the architecture
cannot be designed, as it is always unstable.
Inside this range, the hgher the NTF aggressivity (high
peak NTF magnitudes), the lower the OVL (loop more
unstable) but the hgher the peak SNDR due to increased
in-band rejection of quantization noise. Increasing the
NTF aggressivity causes an increase of first integrator co-
efficient because less quantization noise is re-cycled in-
side the loop. There is an upper peak NTF limit wherc
the integrator coefficient starts to fluctuate or drop. This
shows why highly-aggressive NTFs are rarely preferred:
any small change in one of the loop coefficients can pro-
duce large jumps in integrator outputs, thus reducing the
DR and SNDR.
2.2. Discrete- vs. Continuous-TimeLoop Filter
A comparison of the DT or CT nature of the loop filter is
shown in Fig. 3. The same architecture (Fig. 1) is used
in this case and two sets of loops are designed, one with a
DT loops filter and the other one with a CT equivalent [6].
The graph shows the first integrator coefficient a1 and
the OVL for both sets of designs. The DT variant shows
less non-linear effects and therefore can be designed for
a larger range of NTF magnitudes, extended upper than
the range where the CT variant can be designed. This re-
sult has also been generated by automatic design of the
two sets of ADCs, therefore it has the accuracy of time-
domain simulation. There is nothing in the linear model
to suggest such an effect, but these results support a set
of published designs [2] [3]. The graph in Fig. 3 clearly
 5
Fig. 4. Power consumption for SA4 as function of noise
power ratio R
shows that CT EA ADCs have hgher integrator coeffi-
cients (and therefore less power consumption) compared
to DT equivalents, but they cannot be designed to be as
aggressive as their DT counterparts. Next section shows
circuit-level reasons for the CT integrators to have lower
power consumption than the most used DT integrators,
the switched-capacitor (SC) ones.
3. POWER MODELS
3.1. Noise Power Ratio
The noise power of each integrator in a EA ADC should
be allocated based on exploration of effects of noise power
distribution across the converter. In the power model used
here, a part of the noise power of the previous integrator
is allocated to the next in the loop
(PTLIL
= R (PTt)i-l (1)
and the value of R is chosen to minimize total power con-
sumption. Fig. 4 illustrates the dependence of power con-
sumption of noise power allocation through the ratio R.
The curve shows the current consumption for a fourth-
order, one-bit single-loop EA ADC for audio applica-
tions (BW=20kHz). The supply current estimated in the
best case matches the design reported in [2]. It is worth
noting the SO% (approx. 100p A) power consumption
difference between the best design and the worst one.
3.2. Switched-Capacitor Integrator
For the power estimators, fully differential circuits are
considered, with independent paths for input and loop
digital-to-analog converter (DAC) signal integration, as
shown in Fig. 5. The charge in the sampling capacitor C,
and in the feedback capacitor C f , are both integrated on
the integration capacitor C, during half or the clock cycle
(integration phase).
The power consumption of such an integrator can be
expressed as a function of the amplifier's input stage trans-
conductance gm, whch is designed considering the set-
tling requirements for specific linearity performance [2]
[IO]. The capacitive load driven by gm is derived from
noise performance of each integrator.
DSP -3002 - 355
Vin-
Vfb-
vcmoG+ ~ v c m i 1 Ci
Vfb+ Q .& b - , L
Cfb
Fig. 5. Switched-capacitor integrator with separate signal
and feedback integration paths
For a one-stage amplifier, the total noise power re-
ferred at the input of the integrator is
with
where Ci is a fraction of the integration capacitor (para-
sitic capacitance of Ci) connected at the opamp's output.
The first part of the noise power in Eq. (2) is the noise of
the switch on-resistance and the second part is the noise
of the operational amplifier. This power is referred at the
input of the EA converter as
with i the order of the integrator in the EA converter.
The capacitors around the opamp are calculated from
the required noise power of each integrator and EA loop
coefficients. The gm is then calculated from the required
settling performance, considering a slewing followed by
settling model [2]
(5)
The voltage at the input of the opamp after the charge re-
distribution phase [2], v,,can be calculated in the worst-
case as
The number of needed time constants, N, in Eq. (S),is
given by the settling required for B bits linearity [lo]
N, = BZn(2) (7)
The required linearity of the integrator is determined by
allocating equal distortion power to each integrator and
considering the loop gains to input-refer individual dis-
tortion powers, with the sum of the distortion powers set
to 3dB (0.5 bit) below the target DR. Considering MOS
transistors operated in weak inversion are used for the in-
put stage of the opamp,

gm R5 20Io

a compact expression for gm, is obtained Rf

2))
Vfb-
0
2
TCK
Sm = --CLoad ( ( N , - 1) + 20Vout,maz (1 + Rf
Ci

(9) Vfb+

3.3. Continuous-TimeIntegrator Fig. 6. High-linearity continuous-time integrator

The circuit shown in Fig. 6 is the CT integrator offer-
ing the best linearity performance due to a highly linear This residue voltage is a non-linear function of the cur-
voltage-to-current conversion performed by the Ri resis- rent & and can be expressed as a Taylor series around the
tors for the input signal and by the R f resistors for the Vn(Ii= 0) value:
EA DAC signal. The operational amplifier has an input
stage with MOS devices, so all the resulting current is
integrated on the Cicapacitors.
The power consumption of this integrator can also
be expressed by the transconductance of the operational and replaced in the expression of the integrated current
amplifier calculated from noise and distortion considera-
tions. The generation of noise and distortion in this cir-
cuit is different however than the equivalent SC circuit.
The noise power at the input of the integrator can be writ-
The non-linear components can be calculated from
ten for the circuit in Fig. 6
the large-signal expressions of Vcs( I o )functions for MOS
transistors, VRbeing a difference of two VGSS. Because
differential signals are used, the even order derivatives of
VR(&)are zero. For MOS transistors in weak inversion
where BW is the input signal bandwidth. This is already the two important derivatives are given by
showing that a CT integrator has a smaller noise band-
width, therefore a smaller integration capacitor is needed avR - 2nQh - 1
here compared to the SC equivalent. The noise power in aIi IO SmW.1.
Eq. 10 is referred to the input of the EA ADC following
the formula given in Eq. 4 and after the noise power ratio
is calculated, the two equations can be used to calculate
the needed resistor and capacitor values. with V,, the thermal voltage (26mV at room temperature)
Distortion in the CT integrator appears as an effect and n the exponent non-ideality factor, with the differen-
of the non-linearity of operational amplifier's transcon- tial opamp input pair biased at IO tail current. For MOS
ductance. Considering a one-stage (gm only) operational transistors in strong inversion the derivatives are
amplifier, the current integrated on C, with finite and non-
linear amplifier gain is avR - v,t 1
81, IO SmS.1.

with VRdenoting the residue voltage at the input of the

amplifier. Because the integrator is used in a high-oversampling
with v,,
the gate overdrive voltage, vGs - vT,
Therefore, the third order distortion expressed
ADC and non-linearity is only calculated inside the sig-
as
nal bandwidth, an approximation can be made for the two 1 IiO
voltage signals HD3 = -- (19)
4 Ii3
Vf b = v i n (I2)
becomes, for transistors in weak inversion,
and with the equivalent input resistance

_1 - 1 1
R-R,+Ti;
and for transistors in strong inversion
Eq. 11 becomes

DSP 2002 - 356

The distortion in strong inversion can be lower than in
weak inversion because of the lower non-linearity of the
square low (S.I.) compared to the exponential (W.I.). Tran-
sistors in moderate inversion are the best option when a
single-stage operational amplifier is used. When a two
stage amplifier is used however, the equivalent gm should
be calculated, which is the voltage gain of the first stage
Vin vo-
multiplied by the gm of the second stage, and weak inver-
sion transistors become more attractive due to their high Gnd
voltage gain. -1 1 1 m
Fig. 7. Signal integration for single-ended input,
4. ELECTRET MICROPHONE ca differential-output CT integrator
The EA ADC designed for telephony applications fol-
lows the architecture shown in Fig. 1, clocked at 64 times If b- out of saturation while the circuit is in RTZ mode.
oversampling for 92dB quantization-noise DR over a sig- The differential current feedback keeps the input stage
nal bandwidth of 1lkHz. A mixed CT-DT architecture balanced and does not affect integration linearity.
has been chosen, mainly because the first integrator has
to connect directly to the high-impedance voltage gener-
ator which is the electret microphone. In the same time, 4.2. Higher Order Integrators
the better noise performance of a CT integrator is attrac- The integrators following the first one are all SC circuits
tive in an application targeting 84dB DR for a peak in- (Fig. 5). This design choice was made based on the good
put signal of only 12SmV. A fully-CT architecture has behavior of SC circuits when operating at low supply
been rejected as not being able to offer enough flexibility voltage and based on the considerations explained in Sec-
in terms of peak DR performance, as explained Section tion 2. In a SC integrator, two dfferent common-mode
2. This section presents the circuit design challenges and voltages can be set: for the input signal, during sampling
how they were surmounted. phase, Vcmi is about half V d d to maximize differential
output range of the previous integrator, while during the
4.1. First Integrator integrating phase Vcmo is used as common-mode volt-
age to correctly bias the input stage of the opamp.
The most important building block inside the converter is
Another advantage of SC integrators over CT ones is
the first integrator, because it must perform at full specs
the good control (as good as 0.1%) of the integration gain,
in terms of noise and linearity. The signal path for the first
whch in this case is given by CslCi. This allows the de-
integrator is shown in Fig. 7. The input where the elec-
sign of an aggressive EA loop, which pushes the output
tret microphone is attached is single-ended and connected
range of each SC integrator about 30% closer to the sup-
only to a MOS transistor gate. This makes the input for
ply rails compared to a CT one, while still keeping good
the ADC to be purely capacitive so its impedance is high
fabrication yield. Higher output range requires a smaller
at low frequencies. The PMOS input pair M1, M 2 of-
integrating capacitor, hence a lower power opamp.
fers an input voltage range between -200mV and 200mV,
completely accommodating the electret microphone sig-
nal. The input pair repeats the single-ended voltage signal 4.3. Adder and Comparator
of the microphone onto R S 1 and R S 2 , which convert the The adder in front of the comparator is an active circuit
signal to a current. The resulting differential current is in-
which follows the topology of the higher-order integra-
tegrated by the operational amplifier on the two Ci capac- tors (see Fig. 5) except the integration capacitor Ci is-re-
itors. The operational amplifier keeps the drain currents set on each sampling phase. The comparator is a dynamic
of the two input transistors equal, thus effectively boost-
circuit wluch is pre-loaded on each integrating phase and
ing the differential transimpedance of the MOS transis-
tors. This improves integration linearity, even at small
drain currents for A41 and M 2 .
The operational amplifier also supplies the needed cur-
rents to load the switched capacitors in the subsequent
1
integrators.

E
The feedback from the comparator (coefficient fi in
Fig. 1) is supplied differentially by Ifb+ and I f b - and
directly integrated by the Ci capacitors. The switching
is controlled by the two digital signals S12 and S34 con-
nected from the comparator. The current switches Msl
to Ms4 allow the two feedback currents to be connected
to the source nodes of M 1 and M 2 according to the pre-
vious decision of the comparator. A return-to-zero (RTZ) Fig. 8. Feedback integration for single-ended input,
clock is used to keep the two current sources I f b + and differential-output CT integrator

DSP 2002 - 357

allowed to switch at the end of the integrating phase. A
digital RS latch tracks the comparator output during sam- t I
pling phase and locks it during the next integrating phase,
when the comparator goes into pre-loading again.

5. EXPERIMENTAL RESULTS

The chip photograph is shown in Fig. 9. The EA modu-

lator occupies an area of 0.8 mm2while the reference and
biasing take another 0.4 mm2.The c h p was processed in
a 0.5pm double-poly double-metal CMOS process. The
layout includes test circuits which provide access to the
states of the integrator and allow forcing of all DC bias-
FrequencylHmI
ing signals, including references. Control of all intemal
clock lines is also possible.
Fig. 10. Measured FFT of output bitstream with an input
signal of -23 dBR

white-noise limited dynamic range value is not decreas-

Fig. 9. Chip micrograph
Measurements were done using a test board which
can drive all test signals. The test board contains a CPLD
programmed to generate delayed clocks from a single
master clock and to work as serial-to-parallel converter.
The bitstream is acquired either directly, as a 1.404MHz
1-bit signal or through the serial-to-parallel converter, as
8-bit words. A PC has been used to process the bitstream
in order to analyze spectral characteristics. The test sig-
nal was supplied by an 18-bit linearity and noise signal
ing with increasing input signal, which shows that quan-
tization noise leakage due to integrators non-linearity or
finite closed-loop pole is not significant until the input
signal reaches the overloading level. Measurement of dy-
namic range value when a large input signal is present is
more difficult though.
The DC value in the spectrum is caused by the offset
in the first integrator's input stage. The two transistors
in that stage are operated in strong inversion (hence their
large offset) to maximize their drain-to-source impedance,
thus increasing their voltage gain for better integration
linearity. The DC value is not a problem however, be-
cause speech processing only requires good conversion
performance in the bandwidth above 100Hz.
Fig. 11 shows the measured signal-to-noise and dis-
tortion vs. input signal level. A peak SNDR of 62 dB
(better than 10 bit) is achieved. The overloading level is
-23dBR RMS, which is 1dB better than the original re-
quirement. The curve in Fig. 11 shows good conversion
INL up to a -23dBR RMS input. then it flattens due to
increasing non-linear distortion. Power consumption is
1.7mW from 1.8V supply ( 9 5 0 p A supply current), with
70- , I , I , I I
, I , , , I ,

generator, so any non-ideality would have the cause in 60 -

the ADC under test.
An FFT of the,output digital stream is shown in Fig. 50 -
10. It was measured with an input sinusoidal signal of -
125mV amplitude, centered around the ground voltage, E 40

at a frequency of 2.75 kHz. The second harmonic distor- 5 30

-
tion is 73dB lower than the main spectral component. It is
caused by the disbalance in the input stage of the first in-
tegrator, which allows non-linear crosstalk from the input
common-mode signal (which is half of the single-ended
input signal) to the output of the integrator.
The dynamic range, limited by white noise gener- -90 -80 -70 -60 -50 -40 -30 -30 -10

ated in the first integrator, is 80dB when measured over VinldBR]

1OOHz to 1lkHz bandwidth. Measurements for dynamic

range were done using a very small input signal, so no Fig. 11. Measured SNDR vs input signal level for a chip
distortion would be present. It is worth noting that the using intemal clocks and references

DSP 2002 - 358

85% of it drawn by the first integrator. 171 K. Francken, M. Vogels, G. Gielen, Dedicated
For larger input signals the loop is overloaded, with System-kvel Simulation of CA Modulators, Pro-
integrator outputs reaching the supply rails and not al- ceedings of the IEEE CICC, May 2001.
lowing it to become unstable. Stability tests were run by
placing the modulator in overloading condition and then [SI V. Liberali, V.F. Dias, M. Ciapponi, E Maloberti,
TOSCA: a simulator for switched-capacitor noise-
switching the input signal to a value below the overload-
shaping A/D converters IEEE Transactions on
ing level. The modulator recovers to normal operation
Computer-Aided Design of Integrated Circuits and
within tens of clock cycles after the large signal disap-
Systems, Vol. 12, Sept. 1993.
pears.
[9] S.R. Norsworthy, R. Schreier, G.C. Temes, Delta-
6. CONCLUSIONS Sigma Data Converters, IEEE Press, 1997.
[lo] A. Marques, V. Piuri, M.S. Steyaert, W.M. Sansen,
The non-linear effects in a fourth order, single-bit EA
Optimal Parameters for EA Modulator Topologies,
ADC with both DT and CT loop filters have been ana-
IEEE Transactions on Circuits and Systems 11, Vol.
lyzed by complete architecture design at different peak
45, Sept. 1998.
NTF magnitudes (loop aggressivity). DT loops shown
better overloading levels and higher attainable DR than [l I ] B.Y. Kamath, R.G. Meyer, P.R. Gray, Relationship
their CT equivalents. A set of circuit-level power models Between Frequency Response and Settling Time of
have been developed for most representative CT and DT Operational AmpliJiers IEEE JSSC, Vol. SC-9, Dec.
integrators. The noise power ratio has been introduced 1974.
to further optimize power consumption of the EA ADC.
Based on the conclusions of the modeling, a EA ADC
with mixed CT-DT loop filter has been designed for tele-
phony applications. The circuit takes advantage of the
low power of CT integrators combined with the hgh-
aggressivity of DT loop filters to kee+ the power con-
sumption at i .7mW from a single supply of 1.SV, while
attaining 8OdB DR for IlkHz signal bandwidth. Peak
SNDR is 62dB, mainly limited by distortion introduced
by single-ended to differential conversion in the first in-
tegrator. The linearity with a differential input signal ex-
ceeds 84dB.

REFERENCES

[I] Y. Perelman, R. Ginosar, A low-light-level sensorfor

medical diagnostic applications, IEEE JSSC, Vol.
36, No. 10, Oct. 2001

[2] A.L. Coban, P.E. Allen, A 1 . W 1.0 mWAudio EA

Modulator with 98dB Dynamic Range, ISSCC 1999
Digest of Technical Papers.

[3] L. Breems, E.J. van der Swan, J.H. Huijsing, A 1.8-

mW CMOS EA Modulator with Integrated Mixer for
A/D Conversion of IF Signals, IEEE Joumal of Solid-
State Circuits, Vol. 35, Apr. 2000.

[4] K. Vleugels, S. Rabii, B.A. Wooley, A 2.5V Broad-

band Multi-Bit EA Modulator with 95dB Dynamic
Range, ISSCC 2001 Digest of Technical Papers, Feb.
2001.

[5] K. Bult, Analog Design in Deep Submicron CMOS,

Proceedings of European Solid-state Circuits Con-
ference, Sept. 2000.

[6] R. Schreier, Delta-Sigma Toolbox for Matlab,

www.mathworks.com/support/ftp/controlssv5.html

DSP 2002 - 359