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Ciena XCVR TDM2GE 4GE Data Sheet
Ciena XCVR TDM2GE 4GE Data Sheet
XCVR-TDM2GE, XCVR-TDM4GE
Transceivers
Mobile TDM
Infrastructure Core
Enterprise
Packet Switched Ethernet
Network Packet
Core
CEP Pseudowire or
EVC encapsulated
DS1/E1
Figure 1. Aggregation of T3 to SONET/SDH
Cost-effective yet reliable TDM migration To transport T1/E1 circuits through a packet-oriented
The XCVR-TDM4GE provides an T1 interface via a RJ45 network, the user payload is broken into fragments and a
100-Ohm balanced connector capable of up to 200m reach. SAToP encapsulation header is prepended to each fragment.
The XCVR-TDM2GE provides a E1 interface via RJ45 120-Ohm In this method of encapsulating TDM, only structure- agnostic
balanced connector capable of 100m reach. Both map their transport is addressed; that is, the protocol completely
client signals into pseudowire streams using RFC 4553 SAToP disregards any structure that may be imposed on these signals,
to be transported across an Ethernet network. in particular the structure imposed by standard TDM framing.
SAToP is used over packet-switched networks, where the
Provider Edge (PE) devices do not need to interpret TDM
Packet Switched Network and data or participate in the TDM signaling. TDM endpoints
Multiplexing Layer Headers
connect over TDM E1/T1 circuits, but the circuits physically
terminate at each packet device capable of SAToP. Ciena’s
SAToP Encao Header
(includes RTP header) device transports TDM frames across the PSN core via
pseudowires to the remote SAToP endpoint so the TDM
endpoints can communicate as if they were directly
connected by physical circuits.
TDM data (payload)
2
CEP CEP
TDM De- TDM
Network Packetizer PSN Network
Packetizer
Sender Receiver
SAToP sender and receiver functions • Decap the SAToP data blocks from the valid received packets
The device supports the following functions in the direction • Delay buffer management, packet sequencing, and clock
from T1/E1 to PSN (sender): recovery derived from RTP header along with the host SyncE
• Packetize T1/E1 payload into SAToP reference clock, or re-timing clock source.
• Encapsulate the data blocks with packet headers, RTP • Generate the T1/E1 bit stream using DCR or re-timing clock
header, and FCS recovery method
• Transmit packets via electrical GbE interface toward the PSN • Transport the T1/E1 on the RJ45 interface
Technical Information
Specifications XCVR-TDM2GE/4GE
Header formats MEF8 and MPLS frame header format with optional VLAN tag
Management and Support Management via Service Aware Operating System (SAOS)
Host device compatibility 3904*, 3905*, 3930, 3931*, 3932, 3938vi*, 5142, 5150*, 5160
Latency 1 ms
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