CENG324: Homework #2 Spring 2020

Digital System Design Due 25/2/2020

1. A BCD adder that adds four BCD digits and produces a sum digits in BCD is shown in the figure
below.
a) Write a Verilog model that describes this BCD adder in structural style using Verilog HDL
primitives.
b) Write a Verilog model that describes this BCD adder using Verilog HDL data flow
modeling
c) Write a test bench and use Modelsim to verify if the models in 1.a and 2.b work as four
BCD digits adder. (Test bench and simulation are required to verify the BCD adder
functionality)

2. A demultiplexer, also known as data distributor, takes in a single input and distributes over
several outputs. A demultiplexer of 2n outputs has n select lines.
a. Write a Verilog User Defined Primitive (UDP) to model a 1-to-4
demultiplexer.
b. Use the 1-to-4 demultiplexer designed in 2.a to design a 1-to-8
demultiplexer.
c. Write a Verilog model that describes a 1-to-8 demultiplexer using
Verilog HDL data flow modeling
d. Write a test bench and use Modelsim to verify the functionality of
the 1-to-8 demultiplexer models in 2.b and 2.c.
3. Using Verilog HDL data flow modeling, design a 16-bit arithemtic unit as shown in the figure
below. The unit has input control lines to select the required operation, two inputs (A and B)
each with size of 16-bit and an output Y with size of 16-bit.

Control Operation Description

Input
(Opcode)
0 Y = Avg (A, B) Average value of two
operands
1 Y = Min (A, B) Minimum value of two
operands
2 Y = Max (A, B) Maximum value of two
operands
3 Y= A mod B A modulo B

4. Write a test bench and use Modelsim to verify the functionality of the ALU in question 3.

5. Using Verilog HDL, design a binary adder using three NOT-MAJORITY gates and two inverters as
shown below. (Test bench and simulation are not required)