CMOS Logic Circuit Design

http://www.rcns.hiroshima-u.ac.jp
Link（リンク）: センター教官講義ノート の下 CMOS論理回路設計

Special-Purpose Digital Circuits

• Buffer Circuits
• Path-Selector Circuits
• Information-Storing Circuits
• Trigger Circuits
• Multi-Vibrator Circuits
• Voltage-Generator Circuits

Mattausch, CMOS Design, H20/5/2 1

Necessary Functions other than Logic Operations

1) Transmission of signals over long interconnection lines

or to many receivers
- Buffer (inverting, non-inverting, tri-state)
2) Selection of an interconnection for a Signal according to a condition
- Selector (multiplexer, demultiplexer)
3) Storing an information for some time
- Flip-flop, latch
4) Removing Noise from a Signal
- Trigger circuits
5) Generation of Synchronous or Asynchronous Control Signal
- Multi-vibrator circuits (a-stable, bi-stable, mono-stable)
6) Generation of other Voltages than VDD or VSS
- Voltage generator circuits

CMOS logic circuits do contain more than only logic gates.

Mattausch, CMOS Design, H20/5/2 2
Buffer Circuits
- Increasing the driving capability of a logic
signal for large load capacities
- Conventional non-inverting buffers
- Inverting buffers
- Tri-state buffers

Mattausch, CMOS Design, H20/5/2 3

 Reduction of Logic-Gate Fan-Out with a Buffer

NAND-gate with NAND-gate with

fan-out = k, fan-in = m fan-out = 1, fan-in = m

1 1
1 1
2 2
3 3
2 2
m-1 m-1
m m
3 3

Non-inverting
k Buffer k

Delay without buffer Delay with buffer

tdf , NAND = m⋅ (m⋅ t fin + k⋅ t fex ) tdf , NAND = m⋅ (m⋅ t fin + t fex ) + tbuffer
tdr , NAND = m⋅ trin + k⋅ trex tdr , NAND = m⋅ trin + trex + tbuffer

The delay of a circuit with large fan-out (i. e. large output

load) can be reduced with a buffer, if (k-1)·trex > tbuffer is valid.
Mattausch, CMOS Design, H20/5/2 4
 Construction of Non-Inverting CMOS Buffers

Vin Vout Optimum choice of A and N

Cload
VSS 1
C  2N
A ni − buffer =  load 
 Cin1 

 C 
W W W W N ni − buffer = int  12 ln load 
A0 p A1 p A 2N − 2 p A 2N −1 p
Wn Wn Wn Wn Vout  Cin1 
Vin
I1 I2 I2N-1 I2N Cload
(Cin1 is the input capacity of the 1st inverter)
VSS

Non-inverting buffers have even number of inverters. Each

stage has a factor Ani-buffer (Cload,Cin) larger driving capability.
Mattausch, CMOS Design, H20/5/2 5
 Construction of Inverting CMOS Buffers

Vin Vout Optimum Choice of A and N

Cload
VSS 1
C  2 N +1
A i − buffer =  load 
 Cin1 

 1  Cload  1 
N i −buffer = int  2 ln   − 2 
  in1  
0Wp W W 2N −1 Wp W C
A A p A2 p
1
A A 2N p
Wn Wn Wn Wn Wn Vout
Vin
I1 I2 I3 I2N I2N+1 Cload
(Cin1 is the input capacity of the 1st inverter)
VSS

Inverting buffers use an odd number of cascaded inverters.

Each stage has again Ai-buffer(Cload,Cin) larger driving capability.
Mattausch, CMOS Design, H20/5/2 6
 Tri-State Inverter

Symbol

En CMOS-Circuit Implementation
VDD
In Out

In Out
Truth Table
En In Out
VSS En
0 0 floating
0 1 floating
1 0 1
1 1 0

A tri-state inverter has an additional high-impedance or

floating output state selected with an enable signal. It can be
built with a conventional inverter and a transmission gate.
Mattausch, CMOS Design, H20/5/2 7
 Tri-State Buffers

non-inverting
tri-state buffer CMOS-Circuit Implementation
VDD
En

In Out

In Out
inverting I1 I2 IN-1 IN
tri-state buffer
En
VSS
In Out
En

A tri-state buffer combines high driving capability for a large

load capacity Cload and the possibility of a floating output.
Mattausch, CMOS Design, H20/5/2 8
Path-Selector Circuits
- Multiplexer- and Demultiplexer Principles
- Implementation with Transmission Gates
- Series Connection of Transmission Gates
- Implementation with Tri-State Inverters or
Tri-State Buffers

Mattausch, CMOS Design, H20/5/2 9

 Multiplexer and Demultiplexer Principles

between ln(N) and N between ln(N) and N

Control/Selector Lines Control/Selector Lines

1 1
2 2
N 3 One 3 N
One
Data Multiplexer Selected Demultiplexer Possible
Data
Input (MUX) Data (DEMUX) 0utput
Input
Lines Output Lines

N N

Conditional signal-path selection is performed with

multiplexer- or demultiplexer circuits.
Mattausch, CMOS Design, H20/5/2 10
 Multiplexer Realization with Transmission Gates
4-Input Multiplexer
Transmission Gates
Minimum Transmission Gates
Symbols En1 En2 En3 En4
En En
In1
In Out In Out In2
Out
In3
In4
Circuits
En En Minimum Select Signals
En1 En2
In1
In Out In Out
In2
Out
In3
In4

Path-selector realization is easiest by transmission gates.

Mattausch, CMOS Design, H20/5/2 11
 Series Connection of Transmission Gates

Series of N
transmission gates
driving a load

Delay model for a

series of N
transmission gates

Delay equation as a
t PS,hl ≈ t PS,lh ≈ (Rn || Rp )(Cload )⋅ N+ 0.35⋅ (Rn || Rp )(Cinn + Cinp )⋅ N
2
function of N
transmission gates

A series connection of N transmission gates represents an

RC-chain. Therefore, its delay time increases with N2.
Mattausch, CMOS Design, H20/5/2 12
 MUX/DEMUX Realization with Tri-State Buffers

Multiplexer Demultiplexer
En1 En2 En3 EnN EnN En3 En2 En1

In1 Out1

In2 Out2

In3 In Out3
Out

InN OutN

With tri-state buffers the delay problem of signal-path

selectors is solved at the cost of larger integration-area.
Mattausch, CMOS Design, H20/5/2 13
Information-Storing Circuits
- Stabilizing-Feedback Principle
- Set-Reset Flip-Flop
- Clocked Flip-Flops
• Level Sensitive Flip-Flops
• Edge-Triggered Flip-Flops
• Flip-Flop Timing

Mattausch, CMOS Design, H20/5/2 14

Stabilizing-Feedback Principle of Data Storage

Stabilizing inverter-
Resulting stable circuit states
feedback coupling

Stable States Q Q
“one” 1 0
Q Q
“zero” 0 1

By feeding back the identical signal to a circuit node, stable

circuit states result, which are usable for data storage.
Mattausch, CMOS Design, H20/5/2 15
 Set-Reset (SR) Flip-Flop

Circuit diagram Logic Symbol Truth table

(constructed with NAND gates)
S R Q Q
S
Q S Q 0 0 1 1
SR
Flip-Flop 1 0 1 0
R Q 0 1 0 1
Q
R 1 1 Q Q

Set-reset flip-flops extend the stabilizing feedback principle

by a method for external modification of the stored data.
Mattausch, CMOS Design, H20/5/2 16
 Level-Sensitive Data (D) Flip-Flop

Circuit diagram Logic Symbol

(constructed with NAND gates)

D
S Q D Q

SR D
CLK Flip-Flop Flip-Flop

R Q CLK Q

The level-sensitive data (D) flip-flop extends the SR flip-flop

with additional circuitry for clock-controlled writing of data.
Mattausch, CMOS Design, H20/5/2 17
Latch: Transmission-Gate Version of D Flip-Flop

Circuit diagram of a latch

(data flip-flop constructed with inverters and transmission gates)

CLK
Q

D Q

The simplest construction of level-sensitive data (D) flip-flops

has 2 inverters and 2 transmission gates and is called “latch”.
Mattausch, CMOS Design, H20/5/2 18
 Edge-Triggered data (D) Flip-Flop

Circuit diagram of a D flip-flop into which data is written at

the positive edge (low-high) change of the clock
(constructed with 2 latches)
CLK
Q

D Q

Master Latch Slave Latch

The edge-triggered D flip-flop has 2 latches. Data transfer to

the slave latch occurs only at transition edges of the clock.
Mattausch, CMOS Design, H20/5/2 19
 Timing of Flip-Flops for Safe Data Writing

Volt D
positive edge of the clock signal CLK
VDD

Set-up time ts hold time th

VSS
Time
Minimum stable data time ts+th

The safe operation of a flip-flop requires stable data signals

for a minimum time around the clock edge, which determines
data transfer into the storage part of the flip-flop.
Mattausch, CMOS Design, H20/5/2 20
Trigger Circuits
- Removal Possibilities of Signal Noise
- Schmitt-Trigger Circuit

Mattausch, CMOS Design, H20/5/2 21

 Signal Noise and Removal Possibilities
VDD Desired Switching-Point
Noise-Removal

High-Switching Point Characteristic of Circuit

Circuit Input

VSPH

Low-Switching Point VDD

VSPL

Output Voltage
VSS

Time
Noise-Removal
Circuit Output

VDD

VSS
Inverting Removal
VSPL VSPH
Circuit Assumed VSS VDD
VSS
Input Voltage
Time

Noise can be removed from a signal with a circuit who has

different switching points for low-high and high-low transition.
Mattausch, CMOS Design, H20/5/2 22
 Schmitt-Trigger Circuit

Design of n-MOS Transistors M1 and M2

Schmitt-Trigger
determines the High-Switching Point
Symbol
2
β1  VDD − VSPH 
≈ 
VDD β 2  VSS+ VSPH − VTH,n 
M5
M6

M4 VSS Design of p-MOS Transistors M5 and M6

CMOS determines the Low-Switching Point
In Out
Circuit 2
M3
β5  VSS+ VSPL 
VDD
≈
M2 β 6  VDD− VSPL − VTH, p 
M1

VSS

The CMOS inverter circuit can be easily modified to obtain an

inverting Schmitt-trigger circuit to reduce input-signal noise.
Mattausch, CMOS Design, H20/5/2 23
Multi-Vibrator Circuits
- Destabilizing-Feedback Principle
- A-Stable Multi-Vibrator or Oscillator
- Bi-Stable Multi-Vibrator or Flip-Flop
(see Part on Information-Storing Circuits)
- Mono-Stable Multi-Vibrator

Mattausch, CMOS Design, H20/5/2 24

 Destabilizing Feedback: Oscillator Circuits

Destabilizing inverter- Resulting unstable (oscillating)

feedback coupling signals at circuit nodes
Qi

VDD

Q1 Q2

VSS

Q3 Time

By feeding back the inverted signal to a circuit node, an

unstable state is occurs, which is used for oscillator circuits.
Mattausch, CMOS Design, H20/5/2 25
 Ring-Oscillator Circuit with N Stages

Ring-Oscillator constructed with Obtained oscillator

an odd number N of inverters frequency

1
fosc ≈
Vosc N⋅ (t IHL + t ILH )

CMOS oscillators can be constructed with an odd number of

inverters. The oscillator frequency fosc is determined by
inverter low-high/high-low transitions and inverter number.
Mattausch, CMOS Design, H20/5/2 26
 Mono-Stable Multi-Vibrator

Mono-stable multi-vibrator example Generation of long pulse with fixed

constructed with NOR and inverter length by short trigger pulse at input
VDD
Vout tpulse
R
Vin C Vout
V2
V1 V2

V1

VDD
t pulse ≈ RC⋅ ln Vin
VDD− VSP,I
Time

A mono-stable multi-vibrator is a circuit with delayed stable

feedback. Thus pulses with fixed length can be generated.
Mattausch, CMOS Design, H20/5/2 27
Voltage-Generator Circuits

Mattausch, CMOS Design, H20/5/2 28

 Simple Generator for Voltages >VDD and <VSS
High-voltage generator Transient output of the high
voltage generator
Vout ≈ 2VDD− 2VTH, n

Low-voltage generator

Vout ≈ − VDD+ 2VTH, n

Voltage-generator circuits are applied, if the circuits in the

CMOS chip need other supply voltages than VDD and VSS.
Mattausch, CMOS Design, H20/5/2 29