DESIGN AND IMPLEMENTATION OF LOW POWER

COLUMN BYPASS MULTIPLIER

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING
MOTILAL NEHRU NATIONAL INSTITUTE OF TECHNOLOGY
ALLAHABAD-211004, INDIA

PROJECT SUPERVISOR: Dr. Sanjeev Rai

Group No: 27
Srishti Shikhar (201645014)
Dhruv Kumar Kushwaha (20165065)
 Project Title- To design and implement Low Power Column Bypass Multiplier
using FPGA.

Motivation -
Multiplication forms an important fundamental function in arithmetic operations.
Multiplication-based operations are implemented in many Digital Signal Processing
(DSP) applications such as convolution, Fast Fourier Transform (FFT), filter design
and in microprocessors in its arithmetic and logic unit (ALU). Therefore, Multipliers
are key components of many high performance digital systems. It determines a
system’s performance as it is generally the slowest element in the system and often
consumes more area and power. It also affects the execution speed of the devices.
Hence, low-power multiplier design has been an important part in low-power VLSI
systems.
There are several algorithms proposed to perform multiplication, each of which
offers different advantages and has tradeoff in terms of speed, circuit hardware, and
area and power consumption. Through this project, we aim to design and implement
a Low Power Column Bypass Multiplier with reduced switching activity and compare
its results with other parallel array multipliers like the Braun multiplier and Row
bypassing multiplier.

Implementation –
Before proceeding with the design of the proposed Low power Column Bypass
multiplier we first study about the existing array multiplier architecture and calculate
their performance metrics. This will help in determining a fair estimation of the
current scenario practiced across the industrial and scientific community and will
also aid in charting out comparisons between the existing and proposed multiplier
in terms of design, hardware requirement, delay and power consumption.
In this project, we will study and compare 3 different multipliers. These are:
1) Braun Multiplier
2) Multiplier with Row bypassing
3) Multiplier with Column bypassing (proposed)

1) Braun Multiplier: Braun multiplier is a parallel array multiplier also called carry
save multiplier (CSM).This multiplier is used to perform the unsigned bit
multiplication. It is based on the shift and add algorithm. The Braun multiplier
structure is made up of an array of AND gates and full adders. To implement n x n
multiplier we require n-1 rows of Carry Save Adders each of which consists of n-1
Full Adders. The last stage is a ripple carry adder.
2) Multiplier with Row bypassing: This technique is based on number of zeros in
the multiplier bits. It involves the bypassing of rows of Full adders whenever the
multiplier bit is zero. This is done to reduce switching activity and hence save power
dissipation. However, in doing so some extra correction circuit is also needed.
3) Multiplier with Column bypassing (proposed design): Column bypassing
technique is based on number of zeros in the multiplicand bits. In this operation, the
columns of adders corresponding to the multiplicand bit zero is disabled during
operation to save power. More the number of zeros in the multiplicand, greater will
be the reduction in switching activity and lesser will be the power dissipation.
Salient Features of the Proposed Column Bypass Multiplier:
 The proposed design does not require any extra correction circuitry unlike
Row bypass multiplier.
 The full adder used for performing multiplication is modified to reduce
switching, in the event the multiplicand bit is zero.
 The design is much simpler and with less components compared to Row
bypass multiplier.
 Booth recoding unit has been used.
The described multipliers will be implemented on FPGA kit with their multiplication
algorithm programmed and simulated in Verilog. Based on the performance
metrics obtained from the simulation of all 3 multipliers, an analysis will be done
that will help in determining the efficiency and feasibility of the proposed design.
Architectural Flow –

Tools Required –
 Software – 1) Xilinx ISE Design Suite
2) Cadence Virtuoso

 Hardware – Artix 7 FPGA Kit

Design Structure–

Fig.1 4×4 Column Bypass Multiplier

Fig.2 Modified Full Adder Cell

Workflow Plan–

 Getting acquainted with and understanding the problem statement

and its different aspects.

 Study of the existing and the proposed multipliers in detail.

 Implementing the existing design for comparison with the

proposed design.

 Designing the proposed Column Bypass multiplier using the logic

structure.

 Simulation of the different multipliers in Verilog and obtaining their

performance metrics.

 Implementation on an FPGA kit.

 Designing of the proposed multiplier in Cadence Virtuoso tool and

obtaining different parameters like average power and delay.

 Analysis and comparison of the two implementation methods of

multiplier design.