Comparison of Multiple Fin Heights for

Increasing Drain Current in N-FinFET

Vimal Kumar Mishra Dr. R.K. Chauhan
Department of Electronics and Communication Department of Electronics and Communication
Engineering Engineering
Madan Mohan Malaviya Engineering College, Madan Mohan Malaviya Engineering College,
Gorakhpur, India Gorakhpur, India
vimal.mishra34@gmail.com rkchauhan27@gmail.com

Abstract- The FinFET has emerged as one of the the delay in the device at the cost of leakage power.
promising devices to extend CMOS technology beyond Also an adverse phenomenon takes place known as
the scaling limit of conventional CMOS technology. short channel effects. The name is given because
FinFET has better scalability and better short channel
these effects are seen in devices having channel
effect. In order to increase drain current for device
length (below lOOnm) and hence short channel. The
22nm with multiple-fln-height FinFETs to improve
major features are lack of pinch off and saturation
drain current of 60% and decrease area without
(due to large drain conductance) and large leakage
increasing number of flns and the dielectric is replaced
with High-k dielectric material (Hfo2). Tri gate
current (a shift in threshold voltage, and therefore VT

FinFET is developing using VISUAL TCAD and its dependence on drain voltage, due to drain induced
performance analyzed for I-V characteristics at barrier lowering (DIBL), and hot carrier effect [2].
different Fin heights. These effects because of short channel effect.
Threshold voltage roll off is the decrease in the
Keywords: FinFET; Trigate; Fin-Height; Electric Field.
threshold voltage of the device with the decrease in
channel length. DIBL is the reduction in the threshold
I. INTRODUCTION
voltage due to the electric field from the drain

The invention of CMOS has provided a revolution in towards the source region.

VLSI industry. It has become a fundamental building To minimize the short channel effects many

block in electronic industry. Its ever increasing use in structures have been proposed till now. The

electronics items (mobile, computer, etc.) has not conventional MOSFET with one gate at the top was
only boomed the growth of electronic industry but replaced by dual gate i.e. two gate terminals to

has also gained the attention of researchers to control the proper operation of channel but with the

develop more and more compact size devices with decrease in channel length it was found that double

better performance. Hence the microelectronics gate MOSFET was also not able to control the

industry has significantly invested in new and better operation and changes in width or length changed the
technologies aiming at the fabrication of devices with threshold voltage considerably [14]. So a better

extremely reduced dimensions. This has led to the device with trigate FinFET i.e. gate on the three sides

design of different types of MOSFET with the aim to of channel have been used to minimize the short

improve the characteristics of the device [1-3]. channel effect with the decrease in channel length.

Over the past four decades the main concern of VLSI In this paper, a systematic method to optimize
has been to combine the increasing number of FinFET in terms of multiple-fin-height and electrical

devices in a single chip without degrading the performance is described in detail. The study

performance and results. This increase in number has includes darin current, band gap, electric field,

been possible due to scaling down or shrinking of potential variation in fmfet device by varying

device dimension. This leads to higher packing multiple Fin Heights using VISUAL TCAD device
density and also the manufacturing price lowers simulator.

down. With the scaling of dimensions the gate oxide

thickness and channel length reduces. This reduces
 II. DEVICE STRUCTRURE AND
SPECIFICAnON

FinFET structures are illustrated in Fig. 2. VISUAL

TCAD device simulations using advanced physical
models are performed for the following n-channel
FinFET nominal designs are shown in Table I.

Table I. Important Device Parameters

Channel length 22nm

Height of fin 40nm-IOOnm

Depth of sn trench is 0.2um

Thickness of gate oxide (Hf02) 2nm

In p-type substrate doping lel6

Figure (I): N-FinFET Layout
Well doping concentration (acceptor) lel7
for nMOS

Rmin of well doping for nMOS (um) 0.25um

SID doping concentration (donor) for le-20

nMOS

Supply Voltage Vdd l.0 V

Drain to source voltage is VDS 0.05

Thickness of the buried oxide (urn) 0.02

Thickness of the poly-silicon gate 0.002

(urn)

Thickness of the ILD dielectric (urn) 0.008

Figure (2): N-FinFET model corresponding to the Layout.

SID doping concentration (donor) for 3e20
n-FinFET (cm"-3) III. FinFET Device Theory

Lateral characteristic length of SID 0.004

A. Drift and Diffusion Current Equation
doping for n-FinFET (urn)

The current densities jn and jp are expressed in

Vertical characteristic length of SID 0.003
doping for n-FinFET (urn) terms of the level I drift diffusion model here

(1)
 (2) The temperature dependencies of effective
density of states and the bandgap in FinFET fairly
simple is expressed as follows:
Where Jin and Jip are the electron and hole mobilities.

Dn = (khT/q) Jin and Dp = (khT/q) JiP are the Nc (T) = Nc (300 K) (T/300 Kl5 (7)
electron and hole diffusivities, according to Einstein
relationship. Nv (T) = Nv (300 K) (T/300 K)15 (8)

B. Effective Electric Field Eg(T) = Eg(O) - (aT2/(T + fJ)) (9)

"Hg. J, En and Ep are the effective driving electric

"
The bandgap narrowing is attributed half to the

field to electrons and holes, which related to local conduction band and another half to the valence band
as default [12]:
band diagram. The band structures of hetero junction
'
have been taken into account here [10]. E e = Ee- 1/21::.Eg (10)

E v= Ev + 1/21::.Eg (11)
3/2
En = 1/q VEe - kbT /q V (In(Ne) - In(T )) (3)
3/2
Ep = 1/qVEv +kbT /q V (In(Nv) - In(T )) (4)
The lattice temperature keeps uniform throughout
FinFET device.

Figure (4): Effective Band gap of N- FinFet device.

Figure (3): Effective Electric Field of electron current for

FinFET device.

C. Effective Density a/States

"Hg. 4 & 5," The band structure parameters,

including bandgap Eg, effective density of states in
the conduction band Nc and valence band Nv, and
intrinsic carrier concentration nie, are the most
important and fundamental physical parameters for
semiconductor material [11].Effective density of
states in the conduction and valence band are defined
as follows:

Nc == 2(mn*khT/2rrh2 )3/2 (5)

Figure (5): Electron Quasi Fermi level for N-FinFET
Nv == 2(mp*khT/2rrh2 )312 (6) device.
 IV. Results and Discussion saturated current is increased I.Oe-05A to 1.50e-05A,
which is increased by 50%.

A. Jd vs Vds curve for FinFET with multiple fin

heights
1.60E-Ol

"Fig. 6, .. Aiming to compare the output lAOE05 VdFO.05V

characteristics of the multiple fin heights of trigate N­
1.20':'05
FinFET. The transfer characteristics, the drain current
(Ids) as a function of the drain voltage (Vds) is vary
from (OV to 1.2V), for constant input voltage is
8.00E-06
Vgs=0.3V at room temperature. The saturated current Id -- H_fin=41.1nm
of Ids at H fin=40nm is 5.25 e-05A and H fm=60nm 6.00E-06
-- H fin-CiOnm
is 6.00e-05A, which is increased by 75%. Hence
4.UUl!:-UO
-- H fin=8Onm
increasing fin-heights from H-fin=40nm to H­
fin=lOOnm the saturated drain currents have 2.00E-06
-- Hjin=10Onm
increased from 5.25e-05A to 7.26e-05A.

O.OO�OO 2.00E-Ol 4.00E-Ol 6.00E-Ol 8.00E-Ol l.oo�OO

Vg
III ,"s VII
8.00E-05
Figure (7): Drain current as a function of the gate voltage
Vgs�O.3V
1.00E-05 for a tri-gate n-FinFET at room temperature and different
Fin Heights.
6.00E-05

5.00E-05
V. CONCLUSION

4.00E-05 The optimization of a multiple-fin height N-FinFET,

1(1 -- H fin=4Onm
between FinFET performance parameters, i.e., I V
3.00E-05
-- H fin=6l1nm curve for input and output characteristics. Careful
:.l.UU.l!i-U)
--H fin=8Onm optimization of variation of fin height reduce leakage
current and increase drain saturation current by 60%
1.OOE-05 -- H fin-100nm
of when fin height increased by 20nm. It is therefore,

O.OOE+OO
concluded that additional fin is not desired in
O.OOE�OO ::!.OOE-Ol 4.00E-Ol 6.00E-Ol 8.00E-Ol 1.OOE�OO 1.::!OE�OO designing the FinFET, hence area is reduced. Careful
VII optimization of Fin Heights for FinFET device can
help in improving the performance of digital and
analog circuits such as Inverter, NAND, NOR and
Figure (6): Drain current as a function of the drain voltage SRAM.
for a triple-gate n-FinFET at room temperature and
different Fin Heights. VI. ACKNOWLEDGEMENT

B. ld vs Vgs curve for FinFET with multiple fin Author, which is thanks to AICTE, sponsored
heights research supported by AICTE under the research
promotion scheme (RPS-160) for developing FinFET
"Hg. 2," The structure has the n- channel FinFET in VLSI LAB of ECE department MMMEC
built on a p-type substrate. As the gate voltage is Gorakhpur.
increased the midgap energy level at the surface is
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