Unit 3

MAHALAKSHMI
ENGINEERING COLLEGE
TIRUCHIRAPALLI-621213.
QUESTION BANK
DEPARTMENT: EEE YR/ SEM:III/ VI
SUB CODE: EE2324 SUB NAME: MICROPROCESSORS &

MICROCONTROLLERS
UNIT 3- PHERIPHERAL INTERFACING
PART A (2 Marks)
1. What are the applications of D/A converter interfacing with 8255? (AUC MAY 2012)
Temperature control
Traffic light control
Industrial applications like motor speed & direction control
2. What is keyboard interfacing?(AUC MAY 2012)
Interfacing a keyboard with microprocessor using keyboard display controller IC is

keyboard interfacing. Keyboard interfacing requires two ports, one input port & one
output port& rows are connected to output port & columns are connected to input port
3. Draw the mode word format of 8251 USART.(AUC NOV 2011)
EE2324/ Microprocessors & Microcontrollers Department of EEE 1

4. State the use of ISR & PR registers in 8259 PIC. (AUC NOV 2011)
INTERRUPT REQUEST REGISTER (IRR) AND IN-SERVICE REGISTER (ISR)
The interrupts at the IR input lines are handled by two registers in cascade, the
Interrupt Request Register (IRR) and the In-Service (ISR). The IRR is used to store
all the interrupt levels which are requesting service; and the ISR is used to store all
the interrupt levels which are being serviced.
PRIORITY RESOLVER
This logic block determines the priorites of the bits set in the IRR. The highest priority
is selected and strobed into the corresponding bit of the ISR during INTA pulse.
5. What are the different ways to end the interrupt execution in 8259 programmable
interrupt controller? (AUC MAY 2011)
EOI – End of Interrupt signal is used.
AEOI – Automatic End of Interrupt
6. What is the function of scan section in 8279 programmable keyboard/ display

controller? (AUC MAY 2011)
Scan section:
The scan section has a scan counter and four scan lines, SL0 to SL3. In decoded
scan mode, the output of scan lines will be similar to a 2-to-4 decoder. In encoded
scan mode, the output of scan lines will be binary count, and so an external decoder
should be used to convert the binary count to decoded output. The scan lines are
common for keyboard and display. The scan lines are used to form the rows of a
matrix keyboard and also connected to digit drivers of a multiplexed display, to turn
ON/OFF.
PART B (8, 16Marks)
1. Describe the comparison of I/O mapped I/O and memory mapped I/O (AUC MAY
2012)

2. Explain with neat diagram the interfacing of 8251(USART) to 8085 microprocessor
(AUC MAY 2012, MAY 2011)
UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER

TRANSMITTER (USART) (8251)
The 8251 is a USART (Universal Synchronous Asynchronous Receiver
Transmitter) for serial data communication. As a peripheral device of a
microcomputer system, the 8251 receives parallel data from the CPU and
transmits serial data after conversion. This device also receives serial data from
the outside and transmits parallel data to the CPU after conversion.
The 8251 functional configuration is programmed by software. Operation
between the 8251 and a CPU is executed by program control. Table 1 shows the
operation between a CPU and the device.
Control Words
There are two types of control word.
1. Mode instruction (setting of function)
2. Command (setting of operation)

1) Mode Instruction
Mode instruction is used for setting the function of the 8251. Mode instruction will be
in "wait for write" at either internal reset or external reset. That is, the writing of a
control word after resetting will be recognized as a "mode instruction."
Items set by mode instruction are as follows:
• Synchronous/asynchronous mode
• Stop bit length (asynchronous mode)
• Character length

• Parity bit
• Baud rate factor (asynchronous mode)
• Internal/external synchronization (synchronous mode)
• Number of synchronous characters (Synchronous mode)
The bit configuration of mode instruction is shown in Figures 2 and 3. In the case of
synchronous mode, it is necessary to write one-or two byte sync characters. If sync
characters were written, a function will be set because the writing of sync
characters constitutes part of mode instruction.

2) Command
Command is used for setting the operation of the 8251. It is possible to write a
command whenever necessary after writing a mode instruction and sync characters.
Items to be set by command are as follows:
• Transmit Enable/Disable
• Receive Enable/Disable
• DTR, RTS Output of data.
• Resetting of error flag.
• Sending to break characters
• Internal resetting
• Hunt mode (synchronous mode)

Status Word
It is possible to see the internal status of the 8251 by reading a status word. The bit
configuration of status word is shown in Fig. 5.

Pin Configuration:
D 0 to D 7 (l/O terminal)
This is bidirectional data bus which receive control words and transmits data from the
CPU and sends status words and received data to CPU.
RESET (Input terminal)

A "High" on this input forces the 8251 into "reset status." The device waits for the
writing of "mode instruction." The min. reset width is six clock inputs during the
operating status of CLK.
CLK (Input terminal)
CLK signal is used to generate internal device timing. CLK signal is independent of
RXC or TXC. However, the frequency of CLK must be greater than 30 times the RXC
and TXC at Synchronous mode and Asynchronous "x1" mode, and must be greater
than 5 times at Asynchronous "x16" and "x64" mode.
WR (Input terminal)
This is the "active low" input terminal which receives a signal for writing transmit data
and control words from the CPU into the 8251.
RD (Input terminal)
This is the "active low" input terminal which receives a signal for reading receive data
and status words from the 8251.
C/D (Input terminal)
This is an input terminal which receives a signal for selecting data or command words
and status words when the 8251 is accessed by the CPU. If C/D = low, data will be
accessed. If C/D = high, command word or status word will be accessed.
CS (Input terminal)
This is the "active low" input terminal which selects the 8251 at low level when the
CPU accesses. Note: The device won’t be in "standby status"; only setting CS = High.
TXD (output terminal)
This is an output terminal for transmitting data from which serial-converted data is
sent out. The device is in "mark status" (high level) after resetting or during a status
when transmit is disabled. It is also possible to set the device in "break status" (low
level) by a command.
TXRDY (output terminal)
This is an output terminal which indicates that the 8251is ready to accept a transmitted
data character. But the terminal is always at low level if CTS = high or the device was
set in "TX disable status" by a command. Note: TXRDY status word indicates that
transmit data character is receivable, regardless of CTS or command. If the CPU
writes a data character, TXRDY will be reset by the leading edge or WR signal.

TXEMPTY (Output terminal)
This is an output terminal which indicates that the 8251 has transmitted all the
characters and had no data character. In "synchronous mode," the terminal is at high
level, if transmit data characters are no longer remaining and sync characters are
automatically transmitted. If the CPU writes a data character, TXEMPTY will be reset
by the leading edge of WR signal. Note : As the transmitter is disabled by setting CTS
"High" or command, data written before disable will be sent out. Then TXD and
TXEMPTY will be "High". Even if a data is written after disable, that data is not sent
out and TXE will be "High".After the transmitter is enabled, it sent out. (Refer to
Timing Chart of Transmitter Control and Flag Timing)
TXC (Input terminal)
This is a clock input signal which determines the transfer speed of transmitted data. In
"synchronous mode," the baud rate will be the same as the frequency of TXC. In
"asynchronous mode", it is possible to select the baud rate factor by mode instruction.
It can be 1, 1/16 or 1/64 the TXC. The falling edge of TXC sifts the serial data out of
the 8251.
RXD (input terminal)
This is a terminal which receives serial data.
RXRDY (Output terminal)
This is a terminal which indicates that the 8251 contains a character that is ready to
READ. If the CPU reads a data character, RXRDY will be reset by the leading edge of
RD signal. Unless the CPU reads a data character before the next one is received
completely, the preceding data will be lost. In such a case, an overrun error flag status
word will be set.
RXC (Input terminal)
This is a clock input signal which determines the transfer speed of received data. In
"synchronous mode," the baud rate is the same as the frequency of RXC. In
"asynchronous mode," it is possible to select the baud rate factor by mode instruction.
It can be 1, 1/16, 1/64 the RXC.
SYNDET/BD (Input or output terminal)
This is a terminal whose function changes according to mode. In "internal
synchronous mode." this terminal is at high level, if sync characters are received and

synchronized. If a status word is read, the terminal will be reset. In "external
synchronous mode, "this is an input terminal. A "High" on this input forces the 8251
to start receiving data characters. In "asynchronous mode," this is an output terminal
which generates "high level"output upon the detection of a "break" character if
receiver data contains a "low-level" space between the stop bits of two continuous
characters. The terminal will be reset, if RXD is at high level. After Reset is active, the
terminal will be output at low level.
DSR (Input terminal)
This is an input port for MODEM interface. The input status of the terminal can be
recognized by the CPU reading status words.
DTR (Output terminal)
This is an output port for MODEM interface. It is possible to set the status of DTR by
a command.
CTS (Input terminal)
This is an input terminal for MODEM interface which is used for controlling a
transmit circuit. The terminal controls data transmission if the device is set in "TX
Enable" status by a command. Data is transmitable if the terminal is at low level.
RTS (Output terminal)
This is an output port for MODEM interface. It is possible to set the status RTS by a
command.

3. Draw & explain the functional block diagram of 8259 – programmable interrupt
controller. (AUC MAY 2012)
Programmable Interrupt Controller(8259)
Features
 8 levels of interrupts.
 Can be cascaded in master-slave configuration to handle 64 levels of interrupts.
 Internal priority resolver.
 Fixed priority mode and rotating priority mode.
 Individually maskable interrupts.
 Modes and masks can be changed dynamically.
 Accepts IRQ, determines priority, checks whether incoming priority > current level
being
 serviced, issues interrupt signal.
 In 8085 mode, provides 3 byte CALL instruction. In 8086 mode, provides 8 bit vector
 number.
 Polled and vectored mode.
 Starting address of ISR or vector number is programmable.
 No clock required.
The Intel 8259A Programmable Interrupt Controller handles up to eight vectored

priority interrupts for the CPU. It is cascadable for up to 64 vectored priority interrupts
without additional circuitry. It is packaged in a 28-pin DIP, uses NMOS technology
and requires a single a5V supply. Circuitry is static, requiring no clock input. The
8259A is designed to minimize the software and real time overhead in handling multi-
level priority interrupts. It has several modes, permitting optimization for a variety of
system requirements. The 8259A is fully upward compatible with the Intel 8259.

Software originally written for the 8259 will operate the 8259A in all 8259 equivalent
modes (MCS-80/85, Non-Buffered, Edge Triggered).
Pin Configuration:

Block Diagram:
The 8259A is a device specifically designed for use in real time, interrupt driven
microcomputer systems. It manages eight levels or requests and has built-in features
for expandability to other 8259A's (up to 64 levels). It is programmed by the system's
software as an I/O peripheral. A selection of priority modes is available to the
programmer so that the manner in which the requests are processed by the 8259A
can be configured to match his system requirements. The priority modes can be
changed or reconfigured dynamically at any time during the main program. This
means that the complete interrupt structure can be defined as required, based on the
total system environment.
INTERRUPT REQUEST REGISTER (IRR) AND IN-SERVICE REGISTER (ISR)
The interrupts at the IR input lines are handled by two registers in cascade, the
Interrupt Request Register (IRR) and the In-Service (ISR). The IRR is used to store
all the interrupt levels which are requesting service; and the ISR is used to store all
the interrupt levels which are being serviced.
PRIORITY RESOLVER
This logic block determines the priorites of the bits set in the IRR. The highest priority
is selected and strobed into the corresponding bit of the ISR during INTA pulse.
INTERRUPT MASK REGISTER (IMR)

The IMR stores the bits which mask the interrupt lines to be masked. The IMR
operates on the IRR. Masking of a higher priority input will not affect the interrupt
request lines of lower quality.
INT (INTERRUPT)
This output goes directly to the CPU interrupt input. The VOH level on this line is
designed to be fully compatible with the 8080A, 8085A and 8086 input levels.
INTA (INTERRUPT ACKNOWLEDGE)
INTA pulses will cause the 8259A to release vectoring information onto the data bus.
The format of this data depends on the system mode (mPM) of the 8259A.
DATA BUS BUFFER
This 3-state, bidirectional 8-bit buffer is used to interface the 8259A to the system
Data Bus. Control words and status information are transferred through the Data Bus
Buffer.
READ/WRITE CONTROL LOGIC
The function of this block is to accept OUTput commands from the CPU. It contains
the Initialization Command Word (ICW) registers and Operation Command Word
(OCW) registers which store the various control formats for device operation. This
function block also allows the status of the 8259A to be transferred onto the Data
Bus.
Command Word (ICW) registers and Operation
Command Word (OCW) registers which store the various control formats for device
operation. This function block also allows the status of the 8259A to be transferred
onto the Data Bus.
CS (CHIP SELECT)
A LOW on this input enables the 8259A. No reading or writing of the chip will occur
unless the device is selected.
WR (WRITE)

A LOW on this input enables the CPU to write control words (ICWs and OCWs) to
the 8259A.
RD (READ)
A LOW on this input enables the 8259A to send the status of the Interrupt Request
Register (IRR), In Service Register (ISR), the Interrupt Mask Register (IMR), or the
Interrupt level onto the Data Bus.
A0
This input signal is used in conjunction with WR and RD signals to write commands
into the various command registers, as well as reading the various status registers of
the chip. This line can be tied directly to one of the address lines.
THE CASCADE BUFFER/COMPARATOR
This function block stores and compares the IDs of all 8259A's used in the system.
The associated three I/O pins (CAS0-2) are outputs when the 8259A is used as a
master and are inputs when the 8259A is used as a slave. As a master, the 8259A
sends the ID of the interrupting slave device onto the CAS0±2 lines. The slave thus
selected will send its preprogrammed subroutine address onto the Data Bus during
the next one or two consecutive INTA pulses. (See section ``Cascading the 8259A''.)
INTERRUPT SEQUENCE
The powerful features of the 8259A in a microcomputer system are its

programmability and the interrupt routine addressing capability. The latter allows
direct or indirect jumping to the specific interrupt routine requested without any
polling of the interrupting devices. The normal sequence of events during an interrupt
depends on the type of CPU being used.
The events occur as follows in an MCS-80/85 system:
1. One or more of the INTERRUPT REQUEST lines (IR7±0) are raised high, setting
the corresponding IRR bit(s).
2. The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate.
3. The CPU acknowledges the INT and responds with an INTA pulse.

4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set, and
the corresponding IRR bit is reset. The 8259A will also release a CALL instruction
code (11001101) onto the 8-bit Data Bus through its D7±0 pins.
5. This CALL instruction will initiate two more INTA pulses to be sent to the 8259A
from the CPU group.
6. These two INTA pulses allow the 8259A to release its preprogrammed subroutine
address onto the Data Bus. The lower 8-bit address is released at the first INTA
pulse and the higher 8-bit address is released at the second INTA pulse.
7. This completes the 3-byte CALL instruction released by the 8259A. In the AEOI
mode the ISR bit is reset at the end of the third INTA pulse. Otherwise, the ISR bit
remains set until an appropriate EOI command is issued at the end of the interrupt
sequence. The events occuring in an 8086 system are the same until step 4.
4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set and
the corresponding IRR bit is reset. The 8259A does not drive the Data Bus during
this cycle.
5. The 8086 will initiate a second INTA pulse. During this pulse, the 8259A releases
an 8-bit pointer onto the Data Bus where it is read by the CPU.
6. This completes the interrupt cycle. In the AEOI mode the ISR bit is reset at the end
of the second INTA pulse. Otherwise, the ISR bit remains set until an appropriate
EOI command is issued at the end of the interrupt subroutine. If no interrupt request
is present at step 4 of either sequence (i.e., the request was too short in duration) the
8259A will issue an interrupt level
7. Both the vectoring bytes and the CAS lines will look like an interrupt level 7 was
requested. When the 8259A PIC receives an interrupt, INT becomes active and an
interrupt acknowledge cycle is started. If a higher priority interrupt occurs between
the two INTA pulses, the INT line goes inactive immediately after the second INTA
pulse. After an unspecified amount of time the INT line is activated again to signify
the higher priority interrupt waiting for service. This inactive time is not specified and

can vary between parts. The designer should be aware of this consideration when
designing a system which uses the 8259A. It is recommended that proper
asynchronous design techniques be followed.
INTERRUPT SEQUENCE OUTPUTS
MCS-80, MCS-85
This sequence is timed by three INTA pulses. During the first INTA pulse the CALL
opcode is enabled onto the data bus.
During the second INTA pulse the lower address of the appropriate service routine is
enabled onto the data bus. When Interval e 4 bits A5±A7 are programmed, while
A0±A4 are automatically inserted by the 8259A. When Interval e 8 only A6 and A7
are programmed, while A0±A5 are automatically inserted

8086, 8088
8086 mode is similar to MCS-80 mode except that only two Interrupt Acknowledge
cycles are issued by the processor and no CALL opcode is sent to the processor.
The first interrupt acknowledge cycle is similar to that of MCS-80, 85 systems in that
the 8259A uses it to internally freeze the state of the interrupts for priority resolution

and as a master it issues the interrupt code on the cascade lines at the end of the
INTA pulse. On this first cycle it does not issue any data to the processor and leaves
its data bus buffers disabled. On the second interrupt acknowledge cycle in 8086
mode the master (or slave if so programmed) will send a byte of data to the
processor with the acknowledged interrupt code composed as follows (note the state
of the ADI mode control is ignored and A5±A11 are unused in 8086 mode):
PROGRAMMING THE 8259A
The 8259A accepts two types of command words generated by the CPU:
1. Initialization Command Words (ICWs): Before normal operation can begin, each
8259A in the system must be brought to a starting point by a sequence of 2 to 4
bytes timed by WR pulses.
2. Operation Command Words (OCWs): These are the command words which
command the 8259A to operate in various interrupt modes. These modes are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode
The OCWs can be written into the 8259A anytime after initialization.

INITIALIZATION COMMAND WORDS
(ICWS)
General
Whenever a command is issued with A0 e 0 and D4 e 1, this is interpreted as

Initialization Command Word 1 (ICW1). ICW1 starts the initialization sequence during
which the following automatically occur.
a. The edge sense circuit is reset, which means that following initialization, an
interrupt request (IR) input must make a low-to-high transistion to generate an
interrupt.
b. The Interrupt Mask Register is cleared.
c. IR7 input is assigned priority 7.
d. The slave mode address is set to 7.
e. Special Mask Mode is cleared and Status Read is set to IRR.
f. If IC4 e 0, then all functions selected in ICW4 are set to zero. (Non-Buffered mode*,
no Auto- EOI, MCS-80, 85 system).
*NOTE: Master/Slave in ICW4 is only used in the buffered mode.
Initialization Command Words 1 and 2 (ICW1, ICW2)
A5 - A15: Page starting address of service routines . In an MCS 80/85 system, the 8
request levels will generate CALLs to 8 locations equally spaced in memory. These
can be programmed to be spaced at intervals of 4 or 8 memory locations, thus the 8
routines will occupy a page of 32 or 64 bytes, respectively. The address format is 2
bytes long (A0-A15). When the routine interval is 4, A0-A4 are automatically inserted
by the 8259A, while A5-A15 are programmed externally. When the routine interval is
8, A0-A5 are automatically inserted by the 8259A, while A6-A15 are programmed
externally. The 8-byte interval will maintain compatibility with current software, while
the 4-byte interval is best for a compact jump table.

In an 8086 system A15-A11 are inserted in the five most significant bits of the
vectoring byte and the 8259A sets the three least significant bits according to the
interrupt level. A10±A5 are ignored and ADI (Address interval) has no effect.
LTIM: If LTIM e 1, then the 8259A will operate in the level interrupt mode. Edge
detect logic on the interrupt inputs will be disabled.
ADI: CALL address interval. ADI e 1 then interval e 4; ADI e 0 then interval e 8.
SNGL: Single. Means that this is the only 8259A in the system. If SNGL e 1 no ICW3
will be issued.
IC4: If this bit is setÐICW4 has to be read. If
ICW4 is not needed, set IC4 e 0.
Initialization Command Word 3 (ICW3)
This word is read only when there is more than one 8259A in the system and
cascading is used, in which case SNGL e 0. It will load the 8-bit slave register.
The functions of this register are:
a. In the master mode (either when SP e 1, or in buffered mode when M/S e 1 in

ICW4) a ``1'' is set for each slave in the system. The master then will release byte 1
of the call sequence (for MCS- 80/85 system) and will enable the corresponding
slave to release bytes 2 and 3 (for 8086 only byte 2) through the cascade lines.
b. In the slave mode (either when SP e 0, or if BUF e 1 and M/S e 0 in ICW4) bits
2±0 identify the slave. The slave compares its cascade input with these bits and, if
they are equal, bytes 2 and 3 of the call sequence (or just byte 2 for 8086) are
released by it on the Data Bus.

Initialization Command Word 4 (ICW4)
SFNM: If SFNM e 1 the special fully nested mode is programmed.
BUF: If BUF e 1 the buffered mode is programmed. In buffered mode SP/EN

becomes an enable output and the master/ slave determination is by M/S.
M/S: If buffered mode is selected: M/S e 1 means the 8259A is programmed to be a

master, M/S e 0 means the 8259A is programmed to be a slave. If BUF e 0, M/S has
no function.
AEOI: If AEOI e 1 the automatic end of interrupt mode is programmed.
µPM: Microprocessor mode: mPM e 0 sets the 8259A for MCS-80, 85 system
operation, µPM e 1 sets the 8259A for 8086 system operation.

OPERATION COMMAND WORDS (OCWS)
After the Initialization Command Words (ICWs) are programmed into the 8259A, the
chip is ready to accept interrupt requests at its input lines. However, during the
8259A operation, a selection of algorithms can command the 8259A to operate in
various modes through the Operation Command Words (OCWs)

Operation Control Word 3 (OCW3)
ESMMÐEnable Special Mask Mode. When this bit is set to 1 it enables the SMM bit
to set or reset the Special Mask Mode. When ESMM e 0 the SMM bit becomes a
``don't care''. SMMÐSpecial Mask Mode. If ESMM e 1 and SMM e 1 the 8259A will
enter Special Mask Mode. If ESMM e 1 and SMM e 0 the 8259A will revert to normal
mask mode. When ESMM e 0, SMM has no effect.
Fully Nested Mode
This mode is entered after initialization unless another mode is programmed. The
interrupt requests are ordered in priority from 0 through 7 (0 highest). When an
interrupt is acknowledged the highest priority request is determined and its vector
placed on the bus. Additionally, a bit of the Interrupt Service register (ISO-7) is set.
This bit remains set until the microprocessor issues an End of Interrupt (EOI)
command immediately before returning from the service routine, or if AEOI

(Automatic End of Interrupt) bit is set, until the trailing edge of the last INTA. While
the IS bit is set, all further interrupts of the same or lower priority are inhibited, while
higher levels will generate an interrupt (which will be acknowledged only if the
microprocessor internal Interupt enable flip-flop has been re-enabled through
software). After the initialization sequence, IR0 has the highest prioirity and IR7 the
lowest. Priorities can be changed, as will be explained, in the rotating priority mode.
End of Interrupt (EOI)
The In Service (IS) bit can be reset either automatically following the trailing edge of
the last in sequence INTA pulse (when AEOI bit in ICW1 is set) or by a command
word that must be issued to the 8259A before returning from a service routine (EOI
command). An EOI command must be issued twice if in the Cascade mode, once for
the master and once for the corresponding slave.
There are two forms of EOI command: Specific and Non-Specific. When the 8259A is
operated in modes which perserve the fully nested structure, it can determine which
IS bit to reset on EOI. When a Non- Specific EOI command is issued the 8259A will
automatically reset the highest IS bit of those that are set, since in the fully nested
mode the highest IS level was necessarily the last level acknowledged and serviced.
A non-specific EOI can be issued with OCW2 (EOI -1, SL - 0, R -0).
When a mode is used which may disturb the fully nested structure, the 8259A may
no longer be able to determine the last level acknowledged. In this case a Specific
End of Interrupt must be issued which includes as part of the command the IS level
to be reset. A specific EOI can be issued with OCW2 (EOI - 1, SL - 1, R- 0, and L0-
L2 is the binary level of the IS bit to be reset). It should be noted that an IS bit that is
masked by an IMR bit will not be cleared by a non-specific EOI if the 8259A is in the
Special Mask Mode.
Automatic End of Interrupt (AEOI) Mode
If AEOI - 1 in ICW4, then the 8259A will operate in AEOI mode continuously until
reprogrammed by ICW4. in this mode the 8259A will automatically perform a non-
specific EOI operation at the trailing edge of the last interrupt acknowledge pulse
(third pulse in MCS-80/85, second in 8086). Note that from a system standpoint, this
mode should be used only when a nested multilevel interrupt structure is not required

within a single 8259A. The AEOI mode can only be used in a master 8259A and not
a slave. 8259As with a copyright date of 1985 or later will operate in the AEOI mode
as a master or a slave.
Automatic Rotation (Equal Priority Devices)
In some applications there are a number of interrupting devices of equal priority. In

this mode a device, after being serviced, receives the lowest priority, so a device
requesting an interrupt will have to wait, in the worst case until each of 7 other
devices are serviced at most once . For example, if the priority and ``in service''
status is:
Before Rotate (IR4 the highest prioirity requiring service)
There are two ways to accomplish Automatic Rotation using OCW2, the Rotation on
Non-Specific EOI Command (R - 1, SL- 0, EO-I 1) and the Rotate in Automatic EOI
Mode which is set by (R- 1, SL - 0, EOI - 0) and cleared by (R - 0, SL -0, EOI - 0).

Specific Rotation (Specific Priority)
The programmer can change priorities by programming the bottom priority and thus
fixing all other priorities; i.e., if IR5 is programmed as the bottom priority device, then
IR6 will have the highest one. The Set Priority command is issued in OCW2 where: R
- 1, SL - 1, L0-L2 is the binary priority level code of the bottom priority device.
Observe that in this mode internal status is updated by software control during
OCW2. However, it is independent of the End of Interrupt (EOI) command (also
executed by OCW2). Priority changes can be executed during an EOI command by
using the Rotate on Specific EOI command in OCW2 (R - 1, SL - 1, EOI - 1 and LO-
L2 - IR level to receive bottom priority).
Interrupt Masks
Each Interrupt Request input can be masked individually by the Interrupt Mask
Register (IMR) programmed through OCW1. Each bit in the IMR masks one interrupt
channel if it is set (1). Bit 0 masks IR0, Bit 1 masks IR1 and so forth. Masking an IR
channel does not affect the other channels operation.
Special Mask Mode
Some applications may require an interrupt service routine to dynamically alter the
system priority structure during its execution under software control. For example, the
routine may wish to inhibit lower priority requests for a portion of its execution but
enable some of them for another portion. The difficulty here is that if an Interrupt
Request is acknowledged and an End of Interrupt command did not reset its IS bit
(i.e., while executing a service routine), the 8259A would have inhibited all lower
priority requests with no easy way for the routine to enable them.
That is where the Special Mask Mode comes in. In the special Mask Mode, when a
mask bit is set in OCW1, it inhibits further interrupts at that level and enables
interrupts from all other levels (lower as well as higher) that are not masked. Thus,
any interrupts may be selectively enabled by loading the mask register.
The special Mask Mode is set by OWC3 where: SSMM = 1, SMM = 1, and cleared
where SSMM = 1, SMM = 0.

Poll Command
In Poll mode the INT output functions as it normally does. The microprocessor should
ignore this output. This can be accomplished either by not connecting the INT output
or by masking interrupts within the microprocessor, thereby disabling its interrupt
input. Service to devices is achieved by software using a Poll command.
The Poll command is issued by setting P = `1'' in OCW3. The 8259A treats the next
RD pulse to the 8259A (i.e., RD = 0, CS = 0) as an interrupt acknowledge, sets the
appropriate IS bit if there is a request, and reads the priority level. Interrupt is frozen
from WR to RD.
Reading the 8259A Status
The input status of several internal registers can be read to update the user
information on the system. The following registers can be read via OCW3 (IRR and
ISR or OCW1 [IMR]). Interrupt Request Register (IRR): 8-bit register which contains
the levels requesting an interrupt to be acknowledged. The highest request level is
reset from the IRR when an interrupt is acknowledged. (Not affected by IMR.)
In-Service Register (ISR): 8-bit register which contains the priority levels that are
being serviced. The ISR is updated when an End of Interrupt Command is issued.
Interrupt Mask Register: 8-bit register which contains the interrupt request lines which
are masked. The IRR can be read when, prior to the RD pulse, a Read Register
Command is issued with OCW3 (RR = 1, RIS = 0.) The ISR can be read, when, prior
to the RD pulse, a Read Register Command is issued with OCW3 (RR = 1, RIS = 1).

There is no need to write an OCW3 before every status read operation, as long as
the status read corresponds with the previous one; i.e., the 8259A ``remembers''
whether the IRR or ISR has been previously selected by the OCW3. This is not true
when poll is used.
After initialization the 8259A is set to IRR.
For reading the IMR, no OCW3 is needed. The output data bus will contain the IMR
whenever RD is active and A0 = 1 (OCW1). Polling overrides status read when P - 1,
RR – 1 in OCW3.
Edge and Level Triggered Modes
This mode is programmed using bit 3 in ICW1. If LTIM - `0', an interrupt request will
be recognized by a low to high transition on an IR input. The IR input can remain high
without generating another interrupt.

If LTIM = `1', an interrupt request will be recognized by a `high' level on IR Input, and
there is no need for an edge detection. The interrupt request must be removed
before the EOI command is issued or the CPU interrupts is enabled to prevent a
second interrupt from occurring. The priority cell diagram shows a conceptual circuit
of the level sensitive and edge sensitive input circuitry of the 8259A. Be sure to note
that the request latch is a transparent D type latch. In both the edge and level
triggered modes the IR inputs must remain high until after the falling edge of the first
INTA. If the IR input goes low before this time a DEFAULT IR7 will occur when the
CPU acknowledges the interrupt. This can be a useful safeguard for detecting
interrupts caused by spurious noise glitches on the IR inputs. To implement this
feature the IR7 routine is used for ``clean up'' simply executing a return instruction,
thus ignoring the interrupt. If IR7 is needed for other purposes a default IR7 can still
be detected by reading the ISR. A normal IR7 interrupt will set the corresponding ISR
bit, a default IR7 won't. If a default IR7 routine occurs during a normal IR7 routine,
however, the ISR will remain set. In this case it is necessary to keep track of whether
or not the IR7 routine was previously entered. If another IR7 occurs it is a default.
The Special Fully Nest Mode
This mode will be used in the case of a big system where cascading is used, and the
priority has to be conserved within each slave. In this case the fully nested mode will
be programmed to the master (using ICW4). This mode is similar to the normal
nested mode with the following exceptions:

a. When an interrupt request from a certain slave is in service this slave is not locked
out from the master's priority logic and further interrupt requests from higher priority
IR's within the slave will be recognized by the master and will initiate interrupts to the
processor. (In the normal nested mode a slave is masked out when its request is in
service and no higher requests from the same slave can be serviced.)
b. When exiting the Interrupt Service routine the software has to check whether the
interrupt serviced was the only one from that slave. This is done by sending a non-
specific End of Interrupt (EOI) command to the slave and then reading its In-Service
register and checking for zero. If it is empty, a non-specific EOI can be sent to the
master too. If not, no EOI should be sent.
Buffered Mode
When the 8259A is used in a large system where bus driving buffers are required on
the data bus and the cascading mode is used, there exists the problem of enabling
buffers. The buffered mode will structure the 8259A to send an enable signal on
SP/EN to enable the buffers. In this mode, whenever the 8259A's data bus outputs
are enabled, the SP/EN output becomes active. This modification forces the use of
software programming to determine whether the 8259A is a master or a slave. Bit 3
in ICW4 programs the buffered mode, and bit 2 in ICW4 determines whether it is a
master or a slave.
CASCADE MODE
The 8259A can be easily interconnected in a system of one master with up to eight
slaves to handle up to 64 priority levels. The master controls the slaves through the 3
line cascade bus. The cascade bus acts like chip selects to the slaves during the
INTA sequence. In a cascade configuration, the slave interrupt outputs are
connected to the master interrupt request inputs. When a slave request line is
activated and afterwards acknowledged, the master will enable the corresponding
slave to release the device routine address during bytes 2 and 3 of INTA. (Byte 2
only for 8086/8088).
The cascade bus lines are normally low and will contain the slave address code from
the trailing edge of the first INTA pulse to the trailing edge of the third pulse. Each
8259A in the system must follow a separate initialization sequence and can be

programmed to work in a different mode. An EOI command must be issued twice:
once for the master and once for the corresponding slave. An address decoder is
required to activate the Chip Select (CS) input of each 8259A. The cascade lines of
the Master 8259A are activated only for slave inputs, non-slave inputs leave the
cascade line inactive (low).
4. Draw & describe the interfacing of A/D and D/A converter interfacing to 8085
microprocessor. (AUC MAY 2012)
5. Explain the operation modes of 8255 programmable peripheral interface.(AUC NOV

2011)
PARALLEL COMMUNICATION INTERFACE
The Intel 8255 (or i8255) Programmable Peripheral Interface chip is a peripheral
chip originally developed for the Intel 8085 microprocessor, and as such is a
member of a large array of such chips, known as the MCS-85 Family.This chip was
later also used with the Intel 8086 and its descendants. It was later made (cloned)
by many other manufacturers. It is made in DIP 40 and PLCC 44 pins encapsulated

versions.
This chip is used to give the CPU access to programmable parallel I/O, and is similar
to other such chips like the Motorola 6520 PIA (Peripheral Interface Adapter) the
MOS Technology 6522 (Versatile Interface Adapter) and the MOS Technology CIA
(Complex Interface Adapter) all developed for the 6502 family. Other such chips are
the 2655 Programmable Peripheral Interface from the Signetics 2650 family of
microprocessors, the 6820 PIO (Peripheral Input/ Output) from the Motorola 6800
family, the Western Design Center WDC 65C21, an enhanced 6520, and many
others. The 8255 is widely used not only in many microcomputer/microcontroller
systems especially Z-80 based, home computers such as SV-328 and all MSX, but
also in the system board of the best known original IBM-PC, PC/XT, PC/jr, etc. and
clones. However, most often the functionality the 8255 offered is now not
implemented with the 8255 chip itself anymore, but is embedded in a larger VLSI
chip as a sub function. The 8255 chip itself is still made, and is sometimes used
together with a micro controller to expand its I/O capabilities.
Functional Block diagram:
The 8255 has 24 input/output pins in all. These are divided into three 8-bit ports. Port
A and port B can be used as 8-bit input/output ports. Port C can be used as an 8-bit
input/output port or as two 4-bit input/ouput ports or to produce handshake signals for
ports A and B.
The three ports are further grouped as follows:
1) Group A consisting of port A and upper part of port C.
2) Group B consisting of port B and lower part of port C.
Eight data lines (D0 - D7) are available (with an 8-bit data buffer) to read/write data
into the ports or control register under the status of the " RD" (pin 5) and WR" (pin
36), which are active low signals for read and write operations respectively. The
address lines A1 and A0 allow to successively access any one of the ports or the
control register as listed below:

A1 A0 Function
0 0 port A
0 1 port B
1 0 port C
1 1 control register
The control signal "' CS" (pin 6) is used to enable the 8255 chip. It is an active
low signal, ie, when CS = '0, the 8255 is enabled. The RESET input (pin 35) is
connected to a system (like 8085, 8086, etc. ) reset line so that when the system is
reset, all the ports are initialised as input lines. This is done to prevent 8255 and/or
any peripheral connected to it, from being destroyed due to mismatch of ports. This is
explained as follows. Suppose an input device is connected to 8255 at port A. If from
the previous operation, port A is initialised as an output port and if 8255 is not reset
before using the current configuration, then there is a possibility of damage of either
the input device connected or 8255 or both since both 8255 and the device
connected will be sending out data.
The control register or the control logic or the command word register is an 8-bit
register used to select the modes of operation and input/output designation of the
ports.
Pin Configuration:

D0 - D7 These are the data input/output lines for the device. All information read from
and written to the 8255 occurs via these 8 data lines.
CS (Chip Select Input). If this line is a logical 0, the microprocessor can read and
write to the 8255.
RD (Read Input) Whenever this input line is a logical 0 and the RD input is a logical
0, he 8255 data outputs are enabled onto the system data bus.
WR (Write Input) Whenever this input line is a logical 0 and the CS input is a logical
0, data is written to the 8255 from the system data bus
A0 - A1 (Address Inputs) The logical combination of these two input lines determines
which internal register of the 8255 data is written to or read from.
RESET The 8255 is placed into its reset state if this input line is a logical 1. All
peripheral ports are set to the input mode.
PA0 - PA7, PB0 - PB7, PC0 - PC7 These signal lines are used as 8-bit I/O ports.
They can be connected to peripheral devices. The 8255 has three 8 bit I/O ports and
each one can be connected to the physical lines of an external device. These lines
are labeled PA0-PA7, PB0-PB7, and PC0-PC7. The groups of the signals are divided
into three different I/O ports labeled port A (PA), port B (PB), and port C (PC).
Operational Modes of 8255
There are two main operational modes of 8255:

1. Input/output mode 2. Bit set/reset mode
Input/Output Mode
There are three types of the input/output mode. They are as follows:
Mode 0
In this mode, the ports can be used for simple input/output operations without
handshaking. If both port A and B are initialized in mode 0, the two halves of port C
can be either used together as an additional 8-bit port, or they can be used as
individual 4-bit ports. Since the two halves of port C are independent, they may be
used such that one-half is initialized as an input port while the other half is initialized
as an output port. The input output features in mode 0 are as follows: 1. O/p are
latched. 2. I/p are buffered not latched. 3. Port do not have handshake or interrupt
capability.
Mode 1
When we wish to use port A or port B for handshake (strobed) input or output
operation, we initialise that port in mode 1 (port A and port B can be initilalised to
operate in different modes,ie, for eg, port A can operate in mode 0 and port B in
mode 1). Some of the pins of port C function as handshake lines. For port B in this
mode (irrespective of whether is acting as an input port or output port), PC0, PC1
and PC2 pins function as handshake lines. If port A is initialised as mode 1 input port,
then, PC3, PC4 and PC5 function as handshake signals. Pins PC6 and PC7 are
available for use as input/output lines. The mode 1 which supports handshaking has
following features: 1. Two ports i.e. port A and B can be use as 8-bit i/o port. 2. Each
port uses three lines of port c as handshake signal and remaining two signals can be
function as i/o port. 3. interrupt logic is supported. 4. Input and Output data are
latched.
Mode 2
Only group A can be initialised in this mode. Port A can be used for bidirectional
handshake data transfer. This means that data can be input or output on the same
eight lines (PA0 - PA7). Pins PC3 - PC7 are used as handshake lines for port A. The
remaining pins of port C (PC0 - PC2) can be used as input/output lines if group B is
initialised in mode 0. In this mode, the 8255 may be used to extend the system bus to
a slave microprocessor or to transfer data bytes to and from a floppy disk controller.
Bit Set/Reset (BSR) mode

In this mode only port b can be used (as an output port). Each line of port C (PC0 -
PC7) can be set/reset by suitably loading the command word register. no effect
occurs in input-output mode. The individual bits of port c can be set or reset by
sending the signal OUT instruction to the control register.
Control Word format in nput/output mode

The figure shows the control word format in the input/output mode. This mode is
selected by making D7 = '1' .
D0, D1, D3, D4 are for lower port C, port B, upper port C and port A respectively.
When D0 or D1 or D3 or D4 are "SET", the corresponding ports act as input ports.
For eg, if D0 = D4 = '1', then lower port C and port A act as input ports. If these bits
are "RESET", then the corresponding ports act as output ports. For eg, if D1 = D3 =
'0', then port B and upper port C act as output ports.
D2 is used for mode selection for group B (Port B and Lower Port C). When D2 = '0',
mode 0 is selected and when D2 = '1', mode 1 is selected.
D5, D6 are used for mode selection for group A (Upper Port C and Port A). The

format is as follows:
D6 D5 mode
00 0
01 1
1x 2
BSR mode format
File:8255ctrlformat bsr.gif
Control Word format in BSR mode
The figure shows the control word format in BSR mode. This mode is selected by
making
D7='0'.
D0 is used for bit set/reset. When D0= '1', the port C bit selected (selection of a port
C bit is shown in the next point) is SET, when D0 = '0', the port C bit is RESET.
D1, D2, D3 are used to select a particular port C bit whose value may be altered
using D0 bit as mentioned above. The selection of the port C bits are done as
follows:
D3 D2 D1 bit/pin of port C selected

0 0 0 PC0
0 0 1 PC1
0 1 0 PC2
0 1 1 PC3
1 0 0 PC4
1 0 1 PC5
1 1 0 PC6
1 1 1 PC7
D4, D5, D6 are not used.
Example: If the 5th bit (PC5) of port C has to be "SET", then what is the control word?
1. Since it is BSR mode, D7 = '0'.

2. Since D4, D5, D6 are not used, assume them to be '0'.
3. PC5 has to be selected, hence, D3 = '1', D2 = '0', D1 = 1'. o

4. PC5 has to be set, hence, D0 = '1'.
Applying the above values to the format for BSR mode, we get the control word as
"0B (hex)".

6. Draw the logical block diagram of 8279 keyboard display controller & explain.(AUC
NOV 2011)
Programmable Keyboard/Display Interface – 8279
A programmable keyboard and display interfacing chip. Scans and encodes up to a

64-key keyboard Controls up to a 16-digit numerical display. Keyboard section has a
built-in FIFO 8 character buffer. The display is controlled from an internal 16x8 RAM
tha stores the coded display information.
Display section:
The display section has eight output lines divided into two groups A0-A3 and B0-B3.
The output lines can be used either as a single group of eight lines or as two groups
of four lines, in conjunction with the scan lines for a multiplexed display. The output
lines are connected to the anodes through driver transistor in case of common
cathode 7-segment LEDs. The cathodes are connected to scan lines through driver
transistors. The display can be blanked by BD (low) line. The display section consists
of 16 x 8 display RAM. The CPU can read from or write into any location of the

display RAM.
Keyboard Section:
This section has eight lines (RL0 – RL7) that can be connected to eight columns of a
keyboard, plus two additional lines: Shift and CNTL/ STB (control/ strobe). The status
of the shift key and the control key can be stored along with a key closure. The keys
are automatically debounced, and the keyboard can operate in two modes: two key
lock out or N – key rollover. In the two key lock out mode, if the two keys are pressed
almost simultaneously, only the first key is recognized. In the N – key rollover
method, simultaneous keys are recognized and their codes are stored in the internal
buffer, it can also be set up so that no key is recognized until one key remains
pressed.
The keyboard section also includes 8x8 FIFO RAM. The FIFO RAM consists of eight
registers that can store eight keyboard entries; each is then read in the order of
entries. The status logic keeps track of the number of entries and provides an IRQ
(interrupt request) signal when the FIFO is not empty.
Scan section:
The scan section has a scan counter and four scan lines, SL0 to SL3. In decoded
scan mode, the output of scan lines will be similar to a 2-to-4 decoder. In encoded
scan mode, the output of scan lines will be binary count, and so an external decoder
should be used to convert the binary count to decoded output. The scan lines are
common for keyboard and display. The scan lines are used to form the rows of a
matrix keyboard and also connected to digit drivers of a multiplexed display, to turn
ON/OFF.
CPU interface section:
The CPU interface section takes care of data transfer between 8279 and the
processor. This section has eight bidirectional data lines DB0 to DB7 for data transfer
between 8279 and CPU. It requires two internal address A =0 for selecting data
buffer and A = 1 for selecting control register of8279. The control signals WR (low),
RD (low), CS (low) and A0 are used for read/write to 8279. It has an interrupt request
line IRQ, for interrupt driven data transfer with processor. The 8279 require an
internal clock frequency of 100 kHz. This can be obtained by dividing the input clock
by an internal prescaler. The RESET signal sets the 8279 in 16-character display
with two -key lockout keyboard modes.

Pin Configuration:

7. Draw the control word of 8253 timer/ counter & explain the operation modes of 8253.
(AUC NOV 2011)
Timer IC General
The Intel 8253 is a programmable counter / timer chip designed for use as an
Intel microcomputer peripheral. It uses nMOS technology with a single +5V
supply and is packaged in a 24-pin plastic DIP.
It is organized as 3 independent 16-bit counters, each with a counter rate up to 2
MHz. All modes of operation are software programmable.
The 82C54 is pin compatible with the HMOS 8254, and is a superset of the 8253.
Six programmable timer modes allow the 82C54 / 8253 to be used as an event
counter, elapsed time indicator, programmable one-shot, and in many other
applications.
4.4.1 Block diagram
The timer has three independent, programmable counters and they are all
identical. The block labeled data bus buffer contains the logic to buffer the data
bus to / from the microprocessor, and to the internal registers. The block labeled
read / write logic controls the reading and the writing of the counter registers. The
final block, the control word register, contains the programmed information that is
sent to the device from the microprocessor. In effect this register defines how the
8253 logically works.
Data bus buffer:
The tri state 8 bit, bidirectional buffer is connected to the data bus of
microprocessor.
Control Logic:
The control section has five signals read, write, chip select, and address lines A0
& A1. In the peripheral I/O mode, read & write signals are connected to IOR &
IOW active low signals respectively. In memory mapped I/O, these signals are
connected to MEMR & MEMW active low signals. Address lines A0 & A1 of the
processor usually connects to lines A0 & A1 of 8254 and CS is tied to decoded
address.
The control word register & counters are selected according to the signals on
lines A0 & A1 as shown below.
A0 A1 selection
0 0 Counter 0

0 1 Counter 1
1 0 Counter 2
1 1 Control register
PIN configuration
The following picture shows the pin configuration of the 8253 and a general
definition of the lines follows:
Clock This is the clock input for the counter. The counter is 16 bits. The
maximum clock frequency is 1 / 380 nanoseconds or 2.6 megahertz. The
minimum clock frequency is DC or static operation.
Out This single output line is the signal that is the final programmed output of the
device. Actual operation of the outline depends on how the device has been
programmed.
Gate This input can act as a gate for the clock input line, or it can act as a start
pulse, depending on the programmed mode of the counter.

Control Word register
This register is accessed when lines A0 and A1 are at logic 1. It is used to write a
command word which specifies the counter to be used, its mode and either a
Read or Write operation. The control word format is shown in the figure.
Mode:
8254/ 8253 can operate is six modes.
MODE 0: Interrupt on terminal count:
In this mode, initially the OUT is low. Once a count is loaded in the register, the
counter is decremented every cycle, and when the count reaches zero, the OUT
goes high. This can be used as an interrupt. The OUT remains high until a new
count or a command word is loaded. In the figure, it is shown that the counting
(m=5) is temporarily stopped when the gate is disabled(G=0) and continued again
when the gate is at logic 1.

MODE 1: Hardware- Retriggerable one – shot
In this mode, the OUT is initially high. When the gate is triggered, the OUT goes low,
and at the end of the count, the OUT goes high again, thus generating a one – shot
pulse.
MODE2: Rate Generator
This mode is used to generate a pulse equal to the clock period at a given interval.
When a count is loaded, the OUT stays high until the count reaches 1, and then the
OUT goes low for one period. The count is reloaded automatically, and the pulse is
generated continuously. The count = 1 is illegal in this mode.
MODE3: Square Wave Generator
In this mode, when a count is loaded, the OUT is high. The count is decremented by
two at every clock cycle, and when it reaches zero, the OUT goes low, and the count
is reloaded again. This is repeated continuously ; thus a continuous square wave
with period equal to the count is generated. In other words, the frequency of the

square wave is equal to the frequency of the clock divided by the count. If the count
N is odd, the pulse stays high for (N+1)/2 clock cycle & stays low for (N-1)/2 clock.
MODE4: Software triggered strobe
In this mode, the UOT is initially high; it goes low for one clock period at the end of
the count. The count must be reloaded for subsequent outputs.
MODE 5: Hardware triggered strobe
This mode is similar to Mode4, except that it is triggered by the rising pulse at the
gate. Initially, the OUT is low & when the gate pulse is triggered from low to high, the
count begins. At the end of the count, the OUT goes low for one clock period.

READ – BACK COMMAND:
The Read- Back command in the 8254 allows the user to read the count and the
status of the counter; this command is not available in the 8253. The format of the
command is not available in the 8253. The format of the command is shown.
The command is written in the control register, and the count of the specified counter
can be latched if COUNT (bit D5) is 0. A counter or a combination of counters is
specified by keeping the respective CNT bits (D1, D2, D3) high. For example, the
control. Word 110101110 (D6H) written in the control register will latch the counts of
counter 0 & counter1 and these counts can be obtained by reading respective
counter port address. The latched counts are held until they are read or the counters

are reprogrammed. The Read- Back command eliminates the need of writing
separate counter latch commands for different counters.
The status of the counter (S) can be read if STATUS (active low) bit D4 of the Read-
Back command is low. The figure shows the format of the status byte.

8. Why do we need A/D & D/A converter? Draw the block diagram to interface 8085
microprocessor with A/D converter & D/A converter. (AUC NOV 2011) same as Q10
9. Explain the operation of 8255 PPI port A programmed as input & output in mode 1
with necessary handshake signals.(AUC MAY 2011) Same as Q5
10. Show & explain ADC interfacing with 8085 microprocessor. (AUC MAY 2011)
Digital to Analog Converter (DAC):
The figure includes an 8 input NAND gate and a NOR gate (negative AND)as
the address decoding logic, the 74LS373 as a latch, and an industry – standard
1408D/A converter. The address lines A 7 – A0 are decoded using the 8 input NAND
gate and the output of the NAND gate is combined with the control signal LOW.
When the microprocessor sends the address FFH, the output of the negative AND
gate enables the latch, and the data bits are placed on the input lines of the converter
for conversion.
The 1408 is an 8 bit D/A converter compatible with TTL and CMOS logic, with
the settling time around 300 ns. It has eight input data lines A 1 (MSB) through A8
(LSB); the convention of labeling MSB to LSB is opposite to that of what is normally
used for the data bus in the microprocessor. It requires 2 mA reference current for full
scale input and two power supplies V CC = +5V and VEE = -15 V (VEE can range from -
5V to -15V).
The total reference current source is determined by the resistor R 14 and the
voltage VREF. the resistor R15 is generally equal to R14 to match the input impedance
of the reference sources. The output IO is calculated as follows:
Where input A1 through A8 = 0 or 1.
This formula is an application of the generalized formula for the current I O. for
full scale input (D7 through D0 = 1),

= 2mA (255 / 256)
= 1.992 mA.
The output is 1 LSB less than the full scale reference source of 2 mA. The output
voltage VO for the full scale input is
VO = 2 mA (255 / 256) X 5k
= 9.961 V.
Program:
To generate a continuous waveform, the instructions are as follows:
MVI A, : Load accumulator with the

00H first input
DTOA OUT FFH : Output to DAC
MVI B, : Set up register B for delay

COUNT
DCR B
DELAY
JNZ
DELAY
INR A : Next input
JMP : Go back to output

DTOA
Program description:
This program outputs 00 to FF continuously to the D/A converter. The analog

output of the DAC starts at 0 and increases upto 10 V (approximately) as a ramp.
When the accumulator contents go to 0, the next cycle begins; thus the ramp signal
is generated continuously. The ramp output of the DAC can be observed on an
oscilloscope with an external sync.
The delay in the program is necessary for two reasons:
1. The time needed for a microprocessor to execute an output loop is likely to be less
than the settling time of the DAC.
2. The slope of the ramp can be varied by changing the delay.
Operating the D/A converter in a bipolar range:
The 1408 in the figure is calibrated for the bipolar range from -5V to +5V by
adding the resistor RB (5.0 k) between the reference voltage V REF and the output pin
4. The resistor RB supplies 1 mA (VREF / RB) current to the output in the opposite
direction of the current generated by the input signal. Therefore, the output current
for the bipolar operation IO’ is
When the input signal is equal to zero, the output VO is

(IO = 0 for input =0)
= -5V
When the input = 1000 0000, output V O is
(A2 – A8 = 0)
= (1 mA – 1 mA) 5k = 0V.
Microprocessor compatible D/A converters:
In response to the growing need for interfacing data converters with the
microprocessor, specially designed microprocessor- compatible D/A converters are
now available. These D/A converters generally include a latch on the chip, thus
eliminating the need for an external latch.
The block diagram of Analog devices AD558, includes a latch and an output
op-amp internal to the chip. It can be operated with one power supply voltage
between + 4.5 V to 16.5 V. to interface the AD558 with the microprocessor, two
signals are required. Chip select (CS) and Chip enable (CE).
The figure shows an example o interfacing the AD558 with the 8085. The
address line A7 through an inverter is used for the Chip select, which assigns the port
address 80H (assuming all other address lines are at logic 0) to the DAC port. The
control signal LOW is used for the chip enable. The program can be used to generate
ramp waveforms.
When both signals CS and CE are at logic 0, the latch is transparent,

meaning the input is transferred to the DAC section. When either CS and CE goes to

logic 1, the input is latched in the register and held until both control signals go to
logic 0.
Analog to Digital Converter:
Interfacing 8 bit A/D converters:
As an integrated circuit, the A/D converter includes all three elements – SAR,
DAC and comparator – on a chip. In addition, it has a tri-state output buffer. Typically,
it has two control lines, START (or CONVERT) and DATA READY (or BUSY); they
are TTL – compatible and can be active low or high depending upon the design.
A pulse to the START pin begins the conversion process and disables the tri-
state output buffer. At the end of the conversion period, DATA READY becomes
active and the digital output is made available at the output buffer. To interface an
A/D converter with the microprocessor, the microprocessor should
1. Send a pulse to the START pin. This can be derived from a control signal such as
Write (WR).
2. Wait until the end of the conversion. The end of the conversion period can be verified
either by status checking (polling) or by using the interrupt.
3. Read the digital signal at an input port.
Interfacing an 8 bit A/D converter using status check:

The A/D converter has one input line for analog signal and eight output lines
for converted digital signals. Typically, the analog signal can range from 0 to 10 V, or
±5 V. In addition, the converter shows two lines START and DR (Data ready), both
active low (the active logic level of these lines can be either low or high depending
upon the design of a particular converter). When an active low pulse is sent to the
START pin, the DA goes high and the output lines go into the high impedance state.
The rising edge of the START pulse initiates the conversion. When the conversion is
complete, the DR goes low and the data are made available on the output lines that
can be read by the microprocessor. To interface this converter, we need one output
port to send a START pulse and two input ports: one to check the status of the DR
line and the other to read the output of the converter.
From the figure, the address decoding is performed by using the 1 to 8

decoder (74LS138), the 4 input NAND gate and inverters. Three output lines of the
decoder are combined with appropriate control signals (IOW and IOR) to assign
three port addresses from 80H to 82H. the output port 82HG is used to send a
START pulse by wiring the OUT instruction; in this case, we are interested in getting
a pulse from the microprocessor and the contents of the accumulator are irrelevant to
start the conversion. However, for some converters the IOW pulse from the
microprocessor may not be long enough to start the conversion. When the
conversion begins, the DR (Data ready) goes high and stays high until the
conversion is completed. The status of the DR line is monitored by connecting the
line to bit D0 of the data bus through a tri-state buffer with the input port address 80H.
the processor will continue to read port 80H until bit D0 goes low. When the DR goes
active, the data are available on the output lines of the converter and the processor
can access that data by reading the input port 81H. the subroutine instructions, to
initiate the conversion and to read output data.
Interfacing an 8 bit A/D converter using the interrupt:
Problem statement
1. Interface the National Semiconductor ADC0801 converter with the 8085 MPU using
memory-mapped I/O and the interrupt RST 6.5.

2. Write an interrupt routine to read the output data of the converter, store it in memory,
and continue to collect data for the specified number of times.
Hardware description:
The ADC0801 is a CMOS 8 bit successive approximation A/D converter

housed in a 20 pin DIP package. The input voltage can range from 0 to 5 V and
operates with a single power supply of +5 V. It has two inputs V IN(+) and VIN(-) for the
differential analog signal. When the analog signal is single ended positive, V IN(+) is
used as the input and the VIN (-) pin is grounded; when the signal is single ended
negative, VIN (-) is used as the input and the V IN (+) pin is grounded. The converter
requires a clock at CLK IN; the frequency range can be from 100 kHz to 800 kHz.
The user has two options: either to connect an external clock at CLK IN or to use the
built-in internal clock by connecting a resistor and a capacitor externally at pins 19
and 4, respectively. The frequency is calculated by using the formula f = 1 / 1.1 (RC).
Typically, the clock frequency is designed for 640 kHz to provide 100 µs of
conversion time.
The ADC0801 is designed to be microprocessor compatible. To start

conversion, the CS and WR signals are asserted low. When WR goes low, the
internal SAR (Successive Approximation Register) is reset, and the output lines go
into the high impedance state. When WR makes the transition from low to high, the
conversion begins. When the conversion is completed, the INTR is asserted low and
the data are placed on the output lines. The INTR signal can be used to interrupt the
processor. When the processor reads the data by asserting RD, the INTR is reset.
When is VCC is +5V, the input voltage can range from 0 V to 5 V and the
corresponding output will be from 00 to FFH. However, the full scale output can be
restricted to the lower range of inputs by using pin 9 (V REF/2). For example, if we
connect a 0.5 V dc source at pin 9, we can obtain full scale output FFH for a 1 V
input signal (this is twice the voltage of pin 9).
The ADC0801 van be operated in a continuous mode by connecting WR to INTR and

grounding CS and RD. however, our focus here is to use the interrupts RST 6.5 to
collect data from the converter.

Interfacing circuit:
The figure shows the interfacing of the ADC0801 MPU, using the interrupt.
Address line A15 with an inverter is used for Chip select (CS), and the control signals
MEMR and MEMW are connected to RD and WR signals, respectively. This ia a
memory mapped port with the address 8000H.
The conversion is initiated when the CS and WR signals go low. At the end of
the conversion, the INTR signal goes low and is used to interrupt causes the INTR to
go high. The chip includes the control logic to set INTR at the end of a conversion
and to reset it when data are read; by including this logic on the converter chip, extra
components necessary for interfacing are eliminated.
To implement data transfer using the interrupt, the main program should
initialize the stack, enable the microprocessor interrupts (EI), unmask the RST 6.5
(SIM), and initialize a conversion by writing to port 8000H. in addition, the main
program should include the initialization of the memory pointer for sorting data and
the counter to count the readings. At the end of the conversion, the microprocessor is
interrupted by using RST 6.5, which transfers the program control to location 0034H
and then to the service routine.
Service routine:
LDA : Read data

8000H
MOV : Store data in memory

M, A
INX H : Next memory location

DCR : Next count
B
STA : Start next conversion

8000H
EI : Enable interrupt again
RNZ : Go back to main if

counter ≠ 0
HLT : End
The service routine reads the output data by using the instruction
LDA, stores the byte in memory, and updates the memory pointer and the counter.
The routine assumes that the information concerning the memory pointer (HL) and
the counter (B) is supplied by the main program. The memory pointer specifies the
location where the data should be stored, and the counter specifies the number of
bytes to be collected. The STA instruction starts the next conversion by asserting the
MEMW signal; this instruction should not be interpreted to mean that it is storing the
contents of the accumulator in the converter. Then the service routine sets the
interrupt flip-flop for subsequent interrupts and returns to the main program if the
counter is not zero. When the counter goes to zero, the program completes the data
collection.

Unit 3

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Unit 3

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MAHALAKSHMI

DEPARTMENT: EEE YR/ SEM:III/ VI

SUB CODE: EE2324 SUB NAME: MICROPROCESSORS &

UNIT 3- PHERIPHERAL INTERFACING

Traffic light control

Industrial applications like motor speed & direction control

2. What is keyboard interfacing?(AUC MAY 2012)

Interfacing a keyboard with microprocessor using keyboard display controller IC is

3. Draw the mode word format of 8251 USART.(AUC NOV 2011)

EE2324/ Microprocessors & Microcontrollers Department of EEE 1

INTERRUPT REQUEST REGISTER (IRR) AND IN-SERVICE REGISTER (ISR)

EOI – End of Interrupt signal is used.

AEOI – Automatic End of Interrupt

6. What is the function of scan section in 8279 programmable keyboard/ display

PART B (8, 16Marks)

EE2324/ Microprocessors & Microcontrollers Department of EEE 2

UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER

EE2324/ Microprocessors & Microcontrollers Department of EEE 3

Items set by mode instruction are as follows:

EE2324/ Microprocessors & Microcontrollers Department of EEE 4

EE2324/ Microprocessors & Microcontrollers Department of EEE 5

Items to be set by command are as follows:

EE2324/ Microprocessors & Microcontrollers Department of EEE 6

EE2324/ Microprocessors & Microcontrollers Department of EEE 7

EE2324/ Microprocessors & Microcontrollers Department of EEE 8

EE2324/ Microprocessors & Microcontrollers Department of EEE 9

EE2324/ Microprocessors & Microcontrollers Department of EEE 10

EE2324/ Microprocessors & Microcontrollers Department of EEE 11

Programmable Interrupt Controller(8259)

 Can be cascaded in master-slave configuration to handle 64 levels of interrupts.

 Internal priority resolver.

 Fixed priority mode and rotating priority mode.

 Individually maskable interrupts.

 Modes and masks can be changed dynamically.

 serviced, issues interrupt signal.

 Polled and vectored mode.

 Starting address of ISR or vector number is programmable.

The Intel 8259A Programmable Interrupt Controller handles up to eight vectored

EE2324/ Microprocessors & Microcontrollers Department of EEE 12

EE2324/ Microprocessors & Microcontrollers Department of EEE 13

INTERRUPT REQUEST REGISTER (IRR) AND IN-SERVICE REGISTER (ISR)

INTERRUPT MASK REGISTER (IMR)

EE2324/ Microprocessors & Microcontrollers Department of EEE 14

INTA (INTERRUPT ACKNOWLEDGE)

DATA BUS BUFFER

READ/WRITE CONTROL LOGIC

Command Word (ICW) registers and Operation

EE2324/ Microprocessors & Microcontrollers Department of EEE 15

THE CASCADE BUFFER/COMPARATOR

The powerful features of the 8259A in a microcomputer system are its

The events occur as follows in an MCS-80/85 system:

EE2324/ Microprocessors & Microcontrollers Department of EEE 16

EE2324/ Microprocessors & Microcontrollers Department of EEE 17

INTERRUPT SEQUENCE OUTPUTS

EE2324/ Microprocessors & Microcontrollers Department of EEE 18

EE2324/ Microprocessors & Microcontrollers Department of EEE 19

PROGRAMMING THE 8259A

a. Fully nested mode

b. Rotating priority mode

c. Special mask mode

EE2324/ Microprocessors & Microcontrollers Department of EEE 20

Whenever a command is issued with A0 e 0 and D4 e 1, this is interpreted as

b. The Interrupt Mask Register is cleared.