Semiconductor Device and Its Manufacture

2/7/2020 JPH07122519A - Semiconductor device and its manufacture - Google Patents
Patents JP3688727B2
Semiconductor device and its manufacture
Abstract
JPH07122519A
PURPOSE:To reduce the contact resistance between an electrode part and a semiconductor
Japan
layer by continuously forming one-layer metal layer and a semiconductor layer on one part
of a semiconductor surface without exposing to atmosphere, causing the metal layer to
react with the semiconductor, and forming the compound of the metal layer and the Find Prior Art Similar
semiconductor. CONSTITUTION:An opening 104 is provided at SiO2 102 which is formed on
the surface of a wafer 101 and Ta layer 105 and Si layer 106 are formed on it but the Ta layer Other languages: Japanese
105 and Si layer 106 are formed continuously without exposing to atmosphere using a thin-
Inventor: Tadahiro Omi, Keiichi Yamada, 忠弘大見, 圭一山
lm forming device for a high vacuum. Then, after an impurity ion which is of the same type
田
as a high-density layer 103, heat treatment is performed and silicide layer 107 is formed and
an ion implantation layer is recrystallized. Further, Ta layer 108 is formed on the silicide layer
107, the Ta layer 108 and the silicide layer 107 are subjected to patterning, and then an Worldwide applications
extraction electrode is formed, thus forming a metal electrode with an extremely low contact
1993 JP 1994 WO EP
resistance.
Application JP29078693A events

Classi cations
1993-08-20 Priority to JP20674193
H01L21/76889 Modifying permanently or temporarily the pattern or the conductivity of
1993-11-19 Application led by Tadahiro Omi, 忠弘大見
conductive members, e.g. formation of alloys, reduction of contact resistances by forming
silicides of refractory metals 1995-05-12 Publication of JPH07122519A
View 2 more classi cations 2005-08-31 Application granted
2005-08-31 Publication of JP3688727B2
2013-11-19 Anticipated expiration
2020-02-07 Application status is Expired - Fee Related
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Info: Patent citations (4), Cited by (2), Legal events, Similar

documents, Priority and Related Applications
External links: Espacenet, Global Dossier, Discuss
Claims (23) Hide Dependent

translated from Japanese
[The claims]
1. To claim 1 wherein at least a portion of the semiconductor surface, after the at least one layer of the metal layer and the semiconductor layer formed
in succession without exposure to the atmosphere, and the metal is reacted with the semiconductor and the metal layer is heat treated the method
of manufacturing a semiconductor device characterized by forming a compound with the semiconductor.
2. To wherein prior to the heat treatment method of manufacturing a semiconductor device according to claim 1, a predetermined impurity atoms or an
impurity molecules through the semiconductor layer and the metal layer on the semiconductor, characterized in that the ion implantation .
3. Wherein the ions are produced in the semiconductor device according to claim 2, characterized in that the element or the semiconductor in
constituting the semiconductor is a molecule that contains an atom or a atom generating electrons or holes Method.
4. 4. As the impurity concentration in the interface in the in the semiconductor of the semiconductor and the compound is maximized, production of a
semiconductor device according to claim 3, characterized in that the impurity ion implantation of the semiconductor Method.
5. Injection volume wherein said ions, 1x10 13 to 4

The method of manufacturing a semiconductor device according to any one of claims 2-4, characterized in that the x10 18 cm -2.
6. Wherein said semiconductor is a method of manufacturing a semiconductor device according to claim 1, characterized in that the silicon (Si)
semiconductor.
7. Wherein said metal layer is a refractory metal, a semiconductor device according to claim 1 which is a compound of an alloy or a refractory metal,
including a refractory metal Production method.
8. Wherein said metal layer is, Ta, Ti, W, Co,

Mo, Hf, Ni, Zr, Cr, V, method of manufacturing a semiconductor device according to claim 7, characterized in that it comprises at least one of Pd and
Pt.
9. The thickness of wherein said metal layer is a method of manufacturing a semiconductor device according to any one of claims 1-8, characterized in
that a 1 to 50 nm.
https://patents.google.com/patent/JPH07122519A/en?oq=JP3688727B2 1/14
10. The method according to claim 10, wherein the semiconductor layer, the impurity concentration 1x1
The method of manufacturing a semiconductor device according to any one of claims 1 to 9, characterized in that 0 18 cm -3 or less.
11. 11. The thickness of the semiconductor layer, any one of claims 1 to 10, characterized in that a 0.3nm or more
The method of manufacturing a semiconductor device according to claim.
12. The thickness of 12. The semiconductor layer as above thickness of the metal layer, a method of manufacturing a semiconductor device according
to claim 11, characterized in that a shallow interface between the semiconductor and the compound.
13. Or 13. Half of the thickness of the compound formed after the heat treatment, a method of manufacturing a semiconductor device according to
claim 11 or 12, characterized in that located on the semiconductor layer side.
14. 14. The semiconductor layer manufacturing method of a semiconductor device according to any one of claims 1 to 13, characterized in that it
consists of silicon (Si) semiconductor.
15. 15. after the heat treatment, when there are no remaining semiconductor layer Unreacted subsequently according to any one of claims 1 to 14,
characterized in that to form the second metal layer the method of manufacturing a semiconductor device.
16. 16. After the heat treatment, to remove the semiconductor layer of unreacted method of manufacturing a semiconductor device according to any one
of claims 1 to 14, characterized in that to form the second metal layer .
17. 17. After the heat treatment, and heat treatment after forming the second metal layer on the semiconductor layer of unreacted to form the compound
of the metal into the semiconductor layer and the second metal layer unreacted the method of manufacturing a semiconductor device according to
any one of claims 1 to 14, characterized in that.
18. Metal layer 18. on a substrate, after forming a semiconductor layer continuously without being exposed to the atmosphere, and patterning the
semiconductor layer into a predetermined shape, followed by thermal treatment to react the semiconductor layer and the metal layer by forming a
compound of a metal and a semiconductor, then the unreacted metal layer removed by etching, a method of manufacturing a semiconductor device,
which comprises forming a compound of a metal and a semiconductor in a predetermined shape.
19. 19. A semiconductor device manufactured by the manufacturing method of a semiconductor device according to any one of claims 1 to 18.
20. The contact portion between 20. semiconductor and the electrode, in the semiconductor device to which the compound is formed between the
semiconductor and the metal, the depth of the interface between the semiconductor and the compound 22nm
Wherein a was shallower.
semiconductor and the metal, the depth of the interface between the semiconductor and the compound 12nm
The semiconductor device according to claim 20, characterized in that it has the following.
semiconductor and the metal, more than half of the thickness of said compound, is positioned on the upper side than the semiconductor surface
wherein a.
23. In a semiconductor device having a 23. The multilayer metal interconnect structure, the semiconductor device characterized by having a thin silicide
layer on a contact portion connecting the upper and lower metal interconnect.
Description translated from Japanese
DETAILED DESCRIPTION OF THE INVENTION
[0001]
BACKGROUND OF THE INVENTION This invention relates to a method of manufacturing a semiconductor device, and more particularly, ultra-high density
integrated circuits (ULS
A semiconductor device and a manufacturing method thereof adapted to I).
[0002]
[Related Art Currently, ULSI degree of integration has continued to increase at dramatic pace, 0.1 [mu] m as the size of the device,
Furthermore, are actively research and development is being promoted also the realization of the elements of the ultra- ne size that surpasses even that.
[0003] by the high integration of the device, complex and multi-layered wiring structure is further progress. Along with this, the number of contact portions
for connection between the connection and the metal wiring and semiconductor interconnects the upper have been explosively increasing, more ultra ne
have been promoted regarding its dimensions. UL
High reliability and high performance of a variety of contact present in the SI is one of the important development items that are key for achieving high
reliability and high performance of ULSI.
[0004] To the accomplishment of the reliability and performance of the contact portion between the metal and the semiconductor is a low contact
resistance is essential, in order to realize the required form of ultra-clean contact interface It is essential. The reason is that the presence of the insulator
layer such that interfere with the electrical conductivity in the contact interface (e.g., oxide lm or the like) is because lead to variations in the gain and the
contact resistance of the contact resistance.
However, whether in the case of a contact for connecting metal wires to each other, whether in the case of contact between a metal and a semiconductor
for forming the electrode of ohmic contact of the semiconductor device, to obtain a super-clean contact interface it is very di cult. The reason is that in
order to form the contacts, such as surface impurities on the metal surface or the semiconductor is added in a high concentration, it is necessary to form an
electrode material for a very easily oxidizable material of the surface, forming It has been at the interface because the easily rest oxide lm. For example, if
the metal surface, only to oxide lm 2~5nm only exposing a few seconds to the atmosphere is formed, if n + -Si surface, washed in a conventional ultrapure
water, 0.5 1 nm SiO 2 is formed of. Therefore, in the contact structure formed of a semiconductor element, possible to stably achieve a nonexistent contact
surface of the oxide lm is either a Ikagani di cult techniques can be easily understood. Accordingly, in the ULSI fabrication techniques, the role
establishment plays forming techniques contact interface between the ultra-clean metal and semiconductor are those with enthusiastic.
Conventionally, in the contact formation, contamination present in the interface, such as previously described, in particular as a solution to the growth of the
oxide lm, heat treatment after the contact electrode material formed is performed. In bonding of a metal and silicon,
Technique of reducing the formation and contact resistance of the silicide of a refractory metal has been developed. The refractory metal lm subjected to
heat treatment after formation on silicon, by forming a silicide compound, is brought to the deeper point than the position of the interface immediately after
interfacial contact formation between the silicide and the silicon, clean silicide and Si it is possible to obtain an interface with. Further, since a stable silicide
formation or the purpose of lowering the silicidation temperature, it has also been developed silicide formation technique using an ion beam mixing. After
depositing the refractory metal on silicon, ion implantation thereon, a technique of forming a silicide by performing subsequent thermal processing.
However, the contact method of forming a metal and a semiconductor according to these silicide formation, some problems to be solved is present.
[0008] Here, taking the case of forming a Ta silicide electrode on n + -Si example will be described with reference to Figures 10-12 the problems related to
the prior art. Figure 10 is a sectional view showing the step of forming the Ta silicide electrode onto n + -Si. In FIG. 10 (a), 1001 is a p-type silicon wafer, the
resistivity is 0.3~1.0Ω · cm.
The surface of the wafer and SiO 2 1002 is formed having a thickness of about 500nm approximately as an insulating lm. On the surface of the wafer,
The impurity concentration of the n-type part is the 2 × 10 20 cm -3 n +

And the high concentration layer 1003 is formed, the high-concentration layer 10
Some areas within 03 opening 1004 in SiO 2 1002 as an external electrically conductive can take is provided at least one place. Its On, Ta layer 1005 is
formed to a thickness of about of about 10 nm. The wafer having this structure, the silicide layer followed by heat treatment (TaSi 2)
1006 to form (see Figure 10 (b)). The method of heat treatment using an electric furnace, 2l / mi Ar gas ow rate
And n, 900 ° C., an annealing treatment was performed for 1 hour. As lead wiring material thereon, after forming a thickness of about 500nm the Ta layer
1007 was patterned (see FIG. 10 (c)).
[0009] FIG. 11 shows the measurement results of the contact resistance of TaSi 2 / n + -Si contact formed by the fabrication process. The width of both the
dispersion of the resistance value and its value does not constitute a value su cient for high performance ULSI implementation. Contact resistance of the
emitter of the metal semiconductor source or a bipolar transistor of the MOS transistor is required to be thoroughly low. If the resistance Rs of the source
and the emitter is large, it can not increase the current I owing transistor, because a high-speed operation of the LSI can no longer be realized. When the
source or emitter resistor Rs are present, the voltage Vgi applied to the intrinsic transistor, Vgi = Vg-RSI
Next, it becomes smaller by RsI from the control voltage Vg applied from the outside. If the transconductance of the transistor and gm, from I = gm (Vg-RsI),
I=
gmVg / (1 + gmRs) next, in the denominator and Rs is large is increased, the current I becomes extremely small. For example, the area of the contact hole
0.1X0.1Myuemu 2
(= 10 -10 cm 2) when a conventional contact resistance Rc = 1x
In 10 -7 Ωcm 2, it becomes only one contact and contact resistance of 1K ohm. Normally, in the case of a CMOS structure,
Because so that a minimum of four contact enters between the power source and ground, Rc is essential to the 1x10 -9 [Omega] cm 2 or less.
[0010] FIG. 12 shows the result of measurement by the above TaSi 2 / n + impurity concentration distribution in the depth direction of the -Si junction formed
by the production process of the secondary ion mass spectroscopy (SIMS). In the above technique, although cleaning of the interface between the silicide
and Si to some extent realized, oxygen was present in the initial interface will be incorporated into the silicide layer,
It was found to be a factor that leads to an increase in resistance. Moreover, before the heat treatment, if it is an oxide lm is formed on the metal surface,
the oxygen becomes to be mixed in the silicide layer during the heat treatment, the resistance of the formed silicide layer is con rmed to be increased.
Furthermore, a serious problem in the electrode forming process using silicidation prior art, there is a problem that bite of the silicide layer on the silicon
substrate.
[0012] In the silicidation reaction between the refractory metal and silicon, since the silicide layer is gradually deeply enters into the silicon layer, it is very
di cult to achieve a pole shallowing of the junction between the silicide and the silicon .
[0013] as an example the formation of a tantalum silicide (TaSi 2) by reaction of Ta and silicon, is shown in Figure 13 the results of examining whether
silicide layer bites into how the silicon substrate. When the thickness of 10nm of Ta is reacted with the silicon substrate subjected to deposition heat
treatment on a silicon substrate, a tantalum silicide layer having a thickness of about 24nm on a silicon substrate surface. Taking the initial Ta and silicon
interface standards, silicide layer bites to a position of a depth 22 nm. Formed silicide, it is understood that more truly 90% of the lm thickness is in the
form of sunk in a silicon substrate. Therefore, a large strain due to the difference in lattice spacing of Si and silicide is causing locally generated, defects,
metastases. Accordingly, the electrode forming method using a silicidation prior art, for use in electrode formation of a semiconductor device having ultra-
thin-ultra-shallow junction will be accompanied by restrictions on the element structure.
[0014] With the progress of the ULSI ultra ne and ultra high integration, junction in the semiconductor, for example, the emitter or the like of the source and
drain or bipolar transistors MOSFET,
Proceed more and more very shallowing, it has reached to about 10~50nm. If the step of forming the ohmic contact electrode to the semiconductor layer
having such a very shallow Do junction depths used silicidation process of the metal thin lm and silicon, in the prior art forming method, a silicide layer
source and drain there is a possibility that penetration of and ultrathin layer of the emitter and the like.
[0015] Judging from these facts, the conventional silicide formation technique, not be said perfect solution for thorough reduction of the contact resistance,
resulting a problem to the more junction pole shallowing of ULSI high performance of, the achievement of high reliability have to say is very di cult.
[0016]
[0008] The present invention is directed to a realization of two important requirement items are essential in the electrode and wiring formation step in a
semiconductor device for high performance and high reliability ULSI primary purpose. One in order to reduce the contact resistance between the electrode
portion and the semiconductor layer, eliminate the primary and the contamination layer oxide lm, i.e., the impurity concentration of the metal layer and the
semiconductor layer semiconductor layer near the interface 1nm about regions, electronic is to form a contact structure with high quality metal and
semiconductors to maximize hole density and one contact between a metal and a semiconductor for a semiconductor device having ultra-shallow-very thin
layer structure it is to form a.
[0017]
The method of manufacturing a semiconductor device of the problem-solving means for the invention, at least a portion of the semiconductor surface, after
the at least one layer of the metal layer and the semiconductor layer was formed continuously without being exposed to the atmosphere, the heat treatment
to and forming a compound of a metal and a semiconductor is reacted with the semiconductor and the metal layer.
Furthermore, prior to the heat treatment, it is preferable to the semiconductor layer and the metal layer ion implanted predetermined impurity atoms or an
impurity molecules through the semiconductor, as implanted ions, elements constituting the semiconductor or wherein it is preferred molecules containing
atoms or its atoms generating electrons or holes in a semiconductor, injection volume, 1x
Preferably 10 13 ~4x10 18 cm -2.
Furthermore, the metal layer, Ta, Ti, W, C

o, Mo, Hf, Ni, Zr, Cr, V, Pd and Pt
Comprising at least one high melting point metal is preferably a compound of an alloy or a refractory metal, including a refractory metal of, its thickness, 1
to 50 nm is preferable.
Further, the semiconductor layer, the impurity concentration 1x

10 18 cm -3 or less, be washed with ultrapure water or exposed to the atmosphere, it is preferable that the concentration at which the surface is not oxidized
immediately. The lm thickness is preferably 0.3nm or more. Further, preferably greater than the thickness of the metal layer a thickness of the
semiconductor layer.
[0021] Furthermore, the semiconductor and the semiconductor layer is preferably a silicon semiconductor.
[0022] In the present invention, after the heat treatment, further second
When forming the metal layer, if the semiconductor layer of unreacted exists, to remove the semiconductor layer of the unreacted form a second metal layer,
or a second metal layer on the semiconductor layer of unreacted and heat-treated after formation of the said semiconductor layer and unreacted second
To form a compound with the metal of the metal layer.
[0023] In the method of the present invention,

Metal layer on the substrate, after forming a semiconductor layer continuously without being exposed to the atmosphere, followed by reacting the
semiconductor layer and the metal layer to form a compound of a metal and a semiconductor is heat treated, subsequently unreacted the metal layer was
removed by etching, and forming a compound of a metal and a semiconductor in a predetermined shape. The semiconductor device of the present
invention is characterized in that it is manufactured by the above manufacturing method.
Further, the contact portion between the semiconductor and the electrode,
In the semiconductor device compound of the semiconductor and the metal is formed, 22n the depth of the interface between the semiconductor and the
compound
Characterized by being shallower than m. Furthermore, the semiconductor device of the present invention, the contact portion between the semiconductor
and the electrode, in the semiconductor device to which the compound of the semiconductor and the metal is formed,
More than half of the thickness of said compound, and being located on the upper side than the semiconductor surface.
[0025] Furthermore, the semiconductor device of the present invention is to provide a semiconductor device having a metal wiring structure of the
multilayer, characterized by having a thin silicide layer on a contact portion connecting the upper and lower metal interconnect.
[0026]
According to the present invention, in the bonding of metal wires each other or the electrode material and the semiconductor, for a very easily oxidizable
metal ultra clean surface, covered covers the semiconductor layer to prevent contamination of the growth or the like of the oxide lm , subjected to a heat
treatment, to form a compound of a metal and a semiconductor. Thus, it is possible to form the electrode layer bonding, and impurities such as oxygen are
very low resistance and nonexistent electrode and the semiconductor oxide lm. At the same time, by reacting a metal and a semiconductor in a form
sandwiching the upper and lower metal layer in the semiconductor, the semiconductor needed for the reaction it is possible to supply from both above and
below the metal. Of Thereby, when reacted with whole metal layer,
It is possible to shallow the biting depth into the semiconductor compound layer between the metal and the semiconductor. In particular, the thickness of
the semiconductor layer by the above thickness of the metal layer, can be further shallow more the bite. In the present invention, the semiconductor layer is
a material of the semiconductor and the same type are preferred, the effect even different materials is obtained.
Furthermore, before the heat treatment, by transmitting metal layer and the semiconductor layer by performing ion implantation in the vicinity of the
interface between the metal layer and the semiconductor is also effective for improving characteristics such as the contact resistance reducing. By ion
implantation, it becomes possible to reduce the heat treatment temperature and the treatment time for the metal and the semiconductor are mixed
compound formed. The implanted ion species, more reduction in contact resistance, from the viewpoint of re-crystallization of a semiconductor, a
semiconductor dopant, the semiconductor elements constituting the metal layer constituting elements and the like are preferably used. In particular, by
using ions of a semiconductor dopant, the nal surface of the compound layer and the semiconductor of metal and semiconductor, by controlling the
manufacturing process conditions as the dopant concentration is greatest, metal and semiconductor it is possible to reduce the contact resistance
between. Ion dose and ion energy are implanted ion species, heat treatment conditions, the lm thickness of the semiconductor layer and the metal layer is
suitably determined by constituent elements or the like, reduction of more of the contact resistance, in view of the semiconductor recrystallization , each
1x10 13 ~4x1
0 18 cm -2, 16~200KeV are preferred. Also, injection volume 1x10 15 ~1x10 17 cm -2 are more preferred.
[0028] In the production method of the present invention, a semiconductor and Si as a semiconductor layer, Ge or the like, the metal layer is Ta, T
i, W, Co, Mo, Hf, Ni, Zr, Cr, V, P
d, Pt or the like is preferably used. In particular, Si as a semiconductor material, Ta as the metal material, Ti, W, is suitably applied to a case of selecting a
refractory metal such as Pt, as a very production methods to enable more higher performance of LSI become a promising method for manufacturing.
The thickness of the semiconductor layer and the metal layer, the ion implantation conditions, heat treatment conditions, and by its intended use, it is
determined in relation to each other. Suitable thickness of the semiconductor layer is 0.3n
It is greater than or equal to m. The metal layer, 1 to 50 nm is preferable. With 1nm or more, more is more compounds of the uniform metal and
semiconductor is formed and it is possible to suppress the generation of crystal defects during the compounds formed by the 50nm or less.
Further, in the present invention, the impurity concentration of the semiconductor layer 1x1
It is preferable to be 0 18 cm -3 or less, the resistance of the compound produced in this range can be made smaller. When the impurity concentration of the
semiconductor layer is increased more, because easily surface is oxidized when exposed to air.
The heat treatment of the present invention is preferably at least 100 ° C., more preferably 300 to 500 ° C.. In this range, the compounds of the small metal-
semiconductor contact resistance at low resistance can be formed.
[0031] In the present invention, the metal layer on the substrate, after forming a semiconductor layer continuously without being exposed to the air, followed
metal the semiconductor layer and the metal layer is heat treated by reacting with the semiconductor compound to form, removing then by etching the
metal layer unreacted, by forming a compound of a metal and a semiconductor in a predetermined shape, a refractory metal or its compound formed is
di cult for the conventional ne pattern it is possible to accurately nely patterned (silicide) and the like.
[0032]
EXAMPLES Hereinafter, Examples illustrate the invention in more detail.
[0033] (Example 1) Hereinafter, a rst embodiment of the present invention will be described with reference to Figure 1. Figure 1 (a) ~ (c) are
of Ta silicide on n + -Si is a cross-sectional view showing a step of forming an ohmic contact electrode. 101 is a p-type silicon wafer for example, resistivity,
for example 0.
Is a 3~1.0Ω · cm. n the wafer depending on the purpose
You may be using a mold. It is formed about 500nm for example SiO 2 102 thick as an insulating lm on the surface of the wafer. On the surface of the
wafer, part of which is the n-type impurity concentration is, for example, 1~2 × 10 20 cm -3 n + high concentration layer 103
There is formed an opening 104 is provided a partial area of the high-concentration layer 103 is a SiO 2 102 as an external electrically conductive can take.
On its electrode material layer 105 (e.g., Ta layers) is formed about a thickness of about 5 to 50 nm. Further on the Ta layer 105 is extremely low
0.01~10kΩ · cm (1x10 12 ~1x10 15
concentration of impurities of approximately resistivity e.g. cm -3) Si layer 106 having a thickness of about 2~30nm about
including the It is formed. Ta
Layer and Si layer using a high vacuum compatible lm forming apparatus, are formed continuously without any exposure to the air. Why should be formed
successively, the metal is because the surface immediately upon exposure to the atmosphere is 2~5nm oxidized. With particular deposited undoped Si on
ta, 1 hour or so be exposed to the atmosphere is not oxidized. Of course, depending on the purpose and conditions, may be a metal other than Ta, it is
needless to say that can be selected also free the thickness of the layer. Regard Si layer, it is possible to choose freely even thickness of the layer depending
on the purpose and conditions (up to here, see Figure 1 (a)). Ta is, n-Si,
For p-Si Schottky barrier height 0.56
+
eV, since almost equal to 0.58eV, n -Si, p +
Very low contact resistance is realized respectively -Si. T
i also metal with similar properties.
[0034] the wafer having the structure was subjected to ion implantation. Impurity serving as the high-concentration layer 103 of the same type on the wafer
as the ion species to be implanted, for example, implanting As ions. This is good may be the P even Sb, it is desirable that the impurity of the same elements
in consideration of the high concentration layer 103 the integrity of the crystal structure. The implantation dose, for example as a 2 × 10 15 cm -2, as the
acceleration energy of the ions was set to for example 75 keV.
[0035] In this embodiment, although using As ions to further reduce the maximum and then the contact resistance of the impurity concentration in the
silicide and Si-semiconductor interface, in the case of interest it is simply possible to ion mixing, other ions ( for example Ta, it may be used Si, etc.).
The ion implantation is performed after the heat treatment was conducted recrystallization of the silicide layer (TaSi 2) 107 formed and the ion implanted
layer. The method of heat treatment using an electric furnace, A
While the r gas ow 2l / min, 900 ℃, an annealing treatment was performed for 1 hour. Heat treatment method may be a lamp heating, may be in other
ways. Temperature is not limited to 900 ° C., it is su ciently possible at 400 to 500 ° C.. With regard gas is not limited to Ar, H 2 depending on the purpose
and conditions, N 2, H
e, gas etc., or to may be used a mixed gas thereof, even beyond the conditions are also shown herein with respect to ow rate,
If the cleanliness of the gas is guaranteed not to be a problem. Alternatively there more effective if also be subjected to heat treatment in a vacuum in view
of the consistency of the process. Even over temperature and processing time, the objective, of course, may be used optimal conditions depending on the
conditions. Thereafter, high purity inert gas atmosphere inside, for example, in an N 2 atmosphere, the Si layer of the unreacted remaining on the outermost
surface is removed by an etchant (for example, a mixed aqueous solution of hydro uoric acid and nitric acid), to expose the silicide layer It was. Si removal
may generate Cl radicals under a Cl 2 gas atmosphere. This is a process performed in order to remove completely the worry of the residual Si layer, if, when
the Si layer is All are silicided, wherein the etching process is not necessarily performed, such as described (here up to FIG. 1 (b)
reference).
Furthermore, a silicide layer exposed to the surface and carried in an N 2 atmosphere of ultra-high purity to form an electrode material using an ultra-high
vacuum sputtering apparatus. In the present embodiment, for example, it was formed to a thickness of about 500nm the Ta layer 108. Subjecting the
patterned Ta layer 108 and the silicide layer 107, to form an extraction electrode. Needless to say, to as the extraction electrode may be used an electrode
material other than Ta, may at all in other than referred to herein also thickness thickness (see FIG. 1 (c)).
[0038] Figure 2 shows the results of measurement of the contact resistance of TaSi 2 / n + -Si contact formed by the production process of the present
invention. Compared to the conventional example (FIG. 11), we can see that this is reduced to the width of both the resistance value and the variation. FIG 3,
T formed by the fabrication process of this embodiment
aSi about 2 / n + -Si junction, shows the results of measurement by the impurity concentration distribution of secondary ion mass spectrometry in the depth
direction (SIMS). With respect to oxygen, is not more than the measurement limit value is other than the surface. Is the oxygen has been con rmed on the
surface, it is by the oxide lm formed on the surface until starting the measurement is carried into SIMS apparatus.
[0039] This result, by the method of the present invention, it becomes possible to prevent a thorough mixing of oxygen at the electrode and the joint
formation of a semiconductor, the reduction of contamination of such contaminants, the electrode forming a semiconductor device in step, it can be easily
understood that the decrease of the resistance value is very effective.
Further, apparent that the concentration of As is a high value in the silicide near the interface from FIG.
[0041] In this embodiment, although the example with respect to the electrode formation on the n-type high-concentration Si layer, the same applies with
respect to the electrode formed on the p-type high-concentration Si layer. However, in that case, high-concentration layer 103, the high concentration
impurity layer of p-type are formed. The impurity to be high-concentration layer 103 of the same type on the wafer as the ion species to be implanted (e.g., B
+ ions or BF + ions) are implanted. For example, in the case of using B ions, the energy of the ions 16~25Ke
2
The V. Alternatively, other ions (e.g., Si,
If there is also a good example, Ta).
[0042] By using such the present invention, for example, further reduction of the contact resistance between the electrode material layer and the
semiconductor can be achieved in a semiconductor device. As a result, it becomes possible to push further the ULSI of high performance.
[0043] A second embodiment (Embodiment 2) The present invention FIG. 4

It will be described with reference to. In this embodiment, by by transmitting semiconductor layer formed on the metal layer implanting ions, ion
implantation is performed for the ion implantation and the semiconductor high concentration layer formed for ion mixing at the same time. FIG. 4 (a),
The wafer of Example 1, except that the high-concentration layer 103 is not formed, satis es the same conditions.
[0044] the wafer having the structure of FIG. 4 (a), was subjected to ion implantation. As the ion species to be injected, n
And implanting As ions of the dopant types. this is,
It may be the P may be Sb. The implantation dose, for example as a 2 × 10 15 cm -2, as the acceleration energy of the ions was set to for example 75 keV.
[0045] After the ion implantation, it was recrystallized silicide layer by heat treatment (TaSi 2) 407 formed and the ion implanted layer. In the heat treatment
method, using an electric furnace, an Ar gas owing 2l / min, 500 ° C., an annealing treatment was performed for 1 hour (see Figure 4 (b)). The same
conditions as in Example 1 with respect to the heat treatment method and conditions.
Thereafter, high purity inert gas atmosphere inside, for example, in Ar atmosphere, the unreacted remaining on the outermost surface S
The i-layer is removed by etching solution such as mixed aqueous solution of hydro uoric acid and nitric acid, to expose the silicide layer. Further, without
being exposed to the atmosphere, as an electrode material thereon, such as Ta layer 4
08 was a thickness of about 500nm formation. Subjected to patterning with respect to Ta layer 408 and the silicide layer 407 was formed an extraction
electrode (see FIG. 4 (c)). Needless to say, we may be used an electrode material other than Ta, or a thickness other than the lm thickness are also shown
here.
[0047] Figure 5, the current of the pn diode having n + Si / pSi structure having TaSi 2 as the electrode formed by the above manufacturing process - shows
the measurement result of the voltage characteristic. As shown in FIG. 5, it can be seen that good diode characteristics are obtained. Consequently, as
stated in Embodiment 1, mixing of contaminants, such as oxygen at the time of bonding are due to being thoroughly reduced, it is due to the effect of the
bonding method according to the invention .
[0048] In this embodiment, although the embodiments relating to the formation and the electrode forming the n-type high-concentration Si layer, p-type high
concentration Si
The same applies to the formation of the layer and the electrode formation. However, that case, the ion species implanted, using a p-type dopant ions (e.g.,
B ions).
[0049] Using (Example 3) FIG. 6, illustrating a third embodiment of the present invention relates to silicide silicon bonding with a very shallow junction.
[0050] 601 is a p-type silicon of the wafer surface. Si layer 601 may be a silicon layer formed on the wafer may be a silicon wafer itself. In addition, S
The surface of the i layer 601 is several places may be covered with an insulating layer and a metal layer, diffusion layer impurities several places of the Si
layer 601 is added may be formed. The resistivity of the Si layer is, for example 0.3~1.0Ω · cm. Si layer 601 may be an n-type depending on the purpose.
Also,
The resistivity depending on the purpose and conditions, may even not limited to the range referred to here. On the Si layer 601, SiO 2 602, for example, as an
insulating lm is about 500nm about formation thickness. Opening 603 is provided at least one place on the SiO 2 602. On its approximately metals react to
produce silicide with silicon, for example Ta layer 604 thickness 10
It is nm about formation. For the thickness, but may be thicker thinner than this value, it is uniformly formed a silicide layer, or considering that as much as
possible prevent the defect due to the volume change during silicide formation, 10 nm of about lm it is best to to the thickness. Its On, the Si layer 605
resistivity containing very low concentration impurities of, for example, about 0.01~10kΩ · cm is about 30nm about formation thickness further. The
thickness of the Si layer 605, may even not limited to 30 nm, completely Si layer surface of the Ta layer 604 6
And covering 05, considering that to fully silicide the entire Ta layer 604, no problem as long as not less than about 25 nm (see FIG. 6 (a)).
[0051] subjected to a heat treatment, silicide layer (TaSi

It was formed 2) 606. The method of heat treatment using an electric furnace, an Ar gas ow 2l / min, 700 ° C.,
An annealing treatment for 1 hour was carried out. Heat treatment method may be a lamp heating, may be in other ways. For the gas is not limited to Ar, H 2
depending on the purpose and conditions, N 2, H
e, other gases such as equal or, to may be used a mixed gas thereof, even beyond the conditions referred to herein with regard ow, no problem if cleaning
of the gas is ensured. Also, or performing heat treatment in a vacuum is a more effective case. Also with respect to temperature and processing time,
Purpose, it is needless to say that may be used optimal conditions depending on the conditions.
[0052] After the silicide formation was 12nm was measured the depth x j of the joint relative to the outermost surface of the initial silicon before the
reaction of the silicide layer (see Figure 6 (b)). Incidentally, it was subjected to the same measurements with respect to the silicide layer formed in the
conventional way to do without forming the Si layer 605,
The junction depth was 22 nm.
[0053] From this result, as compared with the conventional method by using the silicide formation process of the present invention, it is seen that
succeeded in shallow junction depth to a value of about 50%. For the production of high performance and high integration semiconductor device, it is
essential thorough ultra-shallow of bonding. To this request, the silicide electrode forming method according to the present invention is very effective, it is
clear from this example.
[0054] (Embodiment 4) FIG. 7 is a sectional view showing a manufacturing process for a multilayer wiring structure formed according to a fourth
embodiment of the present invention.
[0055] 701 is a semiconductor wafer surface. Here, a p-type silicon layer as an example. Si layer 701
It may be a silicon layer formed on the wafer may be a silicon wafer itself. The surface of the Si layer 701 to several places may be covered with an
insulating layer and a metal layer,
Diffusion layer in which impurities are added to several places of the Si layer 701 may be formed. The resistivity of the Si layer is, for example 0.3~1.0Ω · cm.
It may be used n-type depending on the purpose. Further, the resistivity depending on the purpose and conditions may even not limited to the range referred
to here. On the Si layer 701 is a dielectric layer such as SiO 2 layer 702 is formed, the openings 703 for some of the SiO 2 layer 702 to expose the Si layer 701
is formed at least one place or more . Metal layer so as to cover the opening 703 704 (Ti layer for example in this case) is formed of approximately 10nm
thickness. For the thickness, but may be thicker thinner than this value, it is uniformly formed a silicide layer, or considering the utmost to prevent the
generation of crystal defects during silicide formation, the thickness of about 10nm it is best to. Further thereon, 0.01 resistivity e.g.
Si containing very low concentration impurities of about 10 k.OMEGA · cm
The layer 705 is formed about a thickness of about 18 nm. The thickness of the Si layer 705 may or may not limited to 18nm, but and covering completely Si
layer 705 to the surface of the Ti layer 704, after heat treatment, at least one atomic layer or more Si layer of metal and the unreacted leaving, and it may be
determined in consideration of the fact that not too thick much the thickness of the Si layer unreacted. Here, T
And, for example, 18nm approximately as a thick than the i-layer 704. Thereafter, the Ti layer 704 and the Si layer 705 was subjected to patterning into a
suitable shape (far FIGS. 7 (a)
See).
[0056] then, it was subjected to a heat treatment. The method of heat treatment using an electric furnace, an Ar gas ow 2l / min,
700 ° C., an annealing treatment was performed for 1 hour. Heat treatment method may be a lamp heating, may be in other ways. For the gas is not limited
to Ar, H 2 depending on the purpose and conditions, N 2, the He, other gases such as equal or, to may be used a mixed gas thereof, beyond the conditions
referred to herein with regard ow But not a problem. Also, or performing heat treatment in a vacuum is a more effective case. Even over temperature and
processing time, the objective, of course, may be used optimal conditions depending on the conditions. Ti and Si react by the heat treatment of titanium
silicide (T
i Si 2) 706 is formed to a thickness of about 25 nm.
The junction depth of the titanium silicide layer to the Si layer 701 is about 12.5 nm, joining the pole shallowing is achieved. The thickness of the Si layer 705
unreacted was about 5.5 nm (refer to FIG. 7 (b) so far).
Next, the SiO 2 layer 707, for example, as an interlayer insulating layer for electrical insulation between the wiring using chemical vapor deposition (CVD)
method to form a thickness of about 500 nm to 1 [mu] m. Provided at least one or more places by a reactive ion etching of the interlayer insulating lm
opening 708 after the photolithography process for the part of the interlayer insulating layer 707 to expose the Si layer 705 of unreacted silicide layer 706
(refer to FIG. 7 (c) so far).
Next, after the ozone washing thoroughly the opening 708 with ultrapure water containing a few ppm was subjected to removal of the oxide lm on the Si
layer 705 surface using a 0.5-1% diluted hydro uoric acid aqueous solution . Subsequently, the metal layer 709 to cover the opening 708,
For example it was formed to a thickness of about 500nm of Ti layer. Metal layer 7
09, silicon and may be other metals if the metal Ta, Pt or the like to form a stable reacted silicide compound. Further, S which are exposed in the opening
708 with respect to its thickness
Completely reacted with the i layer 705, it may be the thickness as a contact portion of the metal layer 709 and the silicide layer 706 is silicided throughout.
Cleaning method, opening 708
Cleaning effect has enough, it is exposed and Si layer exposed in the opening 708 may not would provide an completely disappeared, without leaving any
passivation lm and the Si layer surface to the opening 708 for to maintain the Si surface super clean state, you need not be limited to the method used in
this embodiment meet the condition. (See FIG. 7 (d)).
[0059] Then, heat treatment is performed to form a new silicide layer 710. The method of heat treatment are the same as previously noted the conditions in
the present embodiment. Finally, Ti layer 7
Against 11, to prepare a wiring structure and patterned into a desired shape at least one or more places (see FIG. 7 (e)).
[0060] The multilayer interconnection structure forming method of this embodiment,

Even in a contact portion formed of the metal wirings, to prevent oxidation of the metal surface by obscuring the metal surface with silicon, we were able to
thoroughly suppress the incorporation of oxygen at the interface of the metal layer. Further, in the cleaning of the openings of the metal wiring formed
immediately prior to the contact portion, by using the method of covering the metal surface with Si, it can not be used for the contact opening has a metal
surface is exposed it is possible to wash with an acid solution, it succeeded in achieving ultra cleaning of the contact surface, and can improve a reliability
of the contact portions of the metal wirings. Furthermore, conventional interlayer insulating lm in the form of direct contact with the metal surface, mainly
SiO
Since that formed the 2, there was electric characteristics problems deterioration such as electrical resistance and electromigration resistance, or metal and
the like adhesion poor problems with oxide lm by oxidation of the metal surface, the present embodiment in the method, the metal surface to form an
insulating lm while leaving a silicon layer on the silicide layer is not oxidized, in addition, since forming the SiO 2 in the silicon layer which rmly remain on
the silicide adhesiveness was improved. In this example, the purpose of reducing the contact resistance between the multilayer metal wirings. Figure 7
So although the metal layer 709 is formed on the Si layer 705 describes an example of forming the and the entire surface by Ti, the surface selection
deposition of tungsten (W) using WF 6 and SiH 4 gas for the purpose of planarization performed only on the Si layer of the opening 708, it is very effective by
forming the WSi 2 in the reaction with the Si layer 705.
[0061] In ultrafast microprocessor or the like, the metal of the multilayer wiring is often used. Metal surface oxide lm of about 2~5nm the oxidized surface
instantaneously upon exposure to the atmosphere is formed. Therefore, the contact resistance of the metal-metal or degrade the high-speed characteristics
of the microprocessor inevitably necessarily large, resulting in smaller logic amplitude. To prevent oxidation of the metal surface, the step shown in FIG 14
is effective.
Here, WF 6, S selectively lling the contact hole
Examples will be described using the W selective growth using iH 4.
[0062] The rst layer of Al metal interconnection on the interlayer insulating lm 1401 (about 0.5 to 1 [mu] m) 1402, non-doped S
A continuously formed i-layer (about 5~10nm) 1403. Interlayer insulating lm 1404 is desirably better to continuously formed by the cluster tool, after the
non-doped Si1403 is hydrogen terminated the surface since it is not easily oxidized, it may be formed by conveying the atmosphere. According to a
predetermined pattern by the subsequent photolithography step, the drilled hole in the interlayer insulating lm 1404. At this time, although at present is
exposed to the air, Al alloy surface is not oxidized by the presence of non-doped Si.
[0063] the non-doped Si only, by WF 6 + SiH 4 based selection CVD (about 180 ° C.), to form the selectively contact hole portion W1405, WSi is reacted with
all the non-doped Si1403 W by heat treatment at 400 to 450 ° C. change to 2. In this way, in the form of WSi 2 is interposed within the W and Al alloy, the
contact of W and Al alloys not interposed any oxide lm is achieved.
[0064] Furthermore, by preventing even exist oxide lm for contact with the Al alloy 1406 on W1405, in all of the contact portion in the multilayer wiring
structure, it is possible to realize a contact oxide lm is not interposed. If that allows the Al alloy thin lm 1406 formed without being exposed to the
atmosphere using a cluster tool or the like, by forming the directly Al alloy lm 1406, the formation was W1405 surface as shown in FIG. 14, incorporation of
oxygen interface with little can be formed. Here, W, instead of Al alloy, may Ta, Ti, Cu, Al, be a metal or alloys such as Ag. Further, this approach may be used
in any layer of a multilayer wiring structure.
[0065] Even when not using the device, such as a cluster tool, by forming a non-doped Si layer 1408 on W1405 as shown in Figure 15, it can be realized
nonexistent multilayer wiring structure of the interface oxide lm. That is, by forming an Al alloy thin lm 1406 conveys the non-doped Si formed after the
atmosphere, since the non-doped Si is less likely to be oxidized, can be fabricated free interface oxide lm between the wirings. Further, in order to raise the
oxidation resistance, a non-doped Si formed after the surface may be terminated with hydrogen.
[0066] The formation of non-doped Si1408 may be performed continuously using, for example, W1405 forming CVD apparatus. That is, by using the WF 6
and SiH 4 gas W14
05 is formed, may be formed a non-doped Si1408 using only subsequently stopped WF 6 gas SiH 4 gas. A
After processing the l alloy thin lm 1406, a non-doped Si remaining on the insulating lm 1404 is normally removed, some cases need not be removed for
high resistance. On the other hand, the non-doped Si
1408 is the formation of only the W1405 possible also selectively perform it, in this case, is structured as in Figure 16 after processing the Al alloy thin lm
1406, the insulating lm 1404
Doped Si is not formed thereon. Also in this case, as described above, a non-doped Si1408 and W14
The formation of 05 can be performed successively in the same CVD apparatus.
[0067] The second layer Al alloy thin lm 1406, a non-doped Si lm 1407 are continuously formed. Thus if a lm of non-doped Si on Al alloy thin lm, if
particularly hydrogen terminated non-doped Si surface, W
W selective growth by F 6 + SiH 4 is completely performed, it is extremely effective for surface planarization. Here, Al alloy, pure Al and Cu, it is needless to
say may be Ag.
[0068] (Embodiment 5) FIG. 8 is a sectional view showing a manufacturing method of a semiconductor and a metal ohmic contact electrode and wiring
structure according to silicide formation according to a fth embodiment of the present invention.
[0069] 801 is a semiconductor layer. Here, an n-type silicon layer as an example. You may be using the p-type depending on the purpose. Si layer 801 may be
a silicon layer formed on the wafer may be a silicon wafer itself. Further, to the surface of several places in the Si layer 801 may be covered with an
insulating layer and a metal layer, diffusion layer impurities several places of the Si layer 801 is added may be formed. The resistivity of the Si layer is, for
example 0.3~1.0Ω · cm. Further, the resistivity depending on the purpose and conditions may even not limited to the range referred to here.
[0070] on the Si layer 801, the insulating lm layer such as SiO 2 layer 802 is formed, the SiO 2 layer 80
Opening 803 for some of 2 to expose the Si layer 801
There are formed at least one place or more. Opening 803
Metal layer so as to cover the, here, for example, Ti layer 804 is 1
It is formed over on the entire surface of the wafer approximately at a thickness of about 0 nm. The metal layer 804, if silicon and stability reacted metal to
form a silicide compound Ta, may be another metal such as Co or W.
[0071] However, the solution to etch the metal,

It is di cult etching reaction proceeds for silicide of the metal, that is, it is required an etching solution, such as can increase the ratio of the etching
reaction of the metal to the etching reaction of the silicide. If dry etching is the same. For the thickness, but may be thicker thinner than this value, it is
uniformly formed a silicide layer, or considering the utmost to prevent the generation of crystal defects during silicide formation, 5 to 10 nm approximately
membrane it is best to to the thickness.
[0072] Further thereon, the resistivity of, for example 0.0

1~10kΩ · Si layer 805 containing a very low concentration impurities of about cm is formed to a thickness of about about 8〜13Nm, some of which are
patterned is applied to any shape of at least one place or more. The thickness of the Si layer 805, 8
Or without limited to 13nm, but in the present embodiment, T
The surface of the i layer 804 and covering completely Si layer 805,
The whole Si layer 805 in consideration of the fact that silicided to, for example, about 8〜13Nm (up to this FIG. 8
(A) see).
[0073] the wafer having the structure of FIG. 8 (a), was subjected to ion implantation. The ion species to be injected,
For example, to implant As ions of n-type dopant. This is good may be the P even Sb. In the present embodiment, since the fabrication of the ohmic contact
electrode and wiring structure has been implanted ions of n-type dopant, if the purpose is simply to silicidation, other ions (e.g. Si, Ti) But good. The
implantation dose, for example as a 2 × 10 15 cm -2, as the acceleration energy of the ions was set to for example 75 keV. In the present embodiment uses
the mixing by ion implantation in order to facilitate the silicidation may not necessarily perform the ion implantation.
[0074] After the ion implantation, it was recrystallization of the formation of the silicide layer by heat treatment (TiSi 2) and the ion implantation layer. The
method of heat treatment using an electric furnace, an Ar gas ow 2l / min, 450 ° C., an annealing treatment was performed for 3 hours. Heat treatment
method may be a lamp heating, may be in other ways. For the gas is not limited to Ar, H 2 depending on the purpose and conditions, N 2, the He, other gases
such as equal or, to may be used a mixed gas thereof, beyond the conditions referred to herein with regard ow But not a problem.
[0075] In addition, or be subjected to heat treatment in a vacuum is a more effective case. Even over temperature and processing time, the objective, of
course, may be used optimal conditions depending on the conditions. Only Ti parts vicinity covered with the Si layer 805 reacts with silicon by this heat
treatment, titanium silicide (TiSi 2) 806 is 12~25nm
It formed with a thickness su cient. Ti other portion not covered with the Si layer 805 remaining in an unreacted state. It injected As is activated as a
dopant by heat treatment, around the silicide layer 806 heavily doped layer 807 of n type is formed (herein to FIG. 8 (b) refer).
Next, a NH 4 OH, H 2 O 2 and H 2 O The wafer 5: 1: mixed aqueous solution at a volume ratio (25
Soaked in ℃). The mixing ratio of the liquid other ratios, such as 4: 1:
1: Even good. Regard liquid temperature, may even not limited to 25 ° C., the liquid temperature is too high results in the decomposition or evaporation of H 2
O 2, conversely, for lowering the reaction rate and liquid temperature is too low, 25 ° C. It was the degree. By immersion in the aqueous solution, Ti layer of
unreacted disappeared is etched SiO 2
The layer 802 surface was exposed. Meanwhile, the portion TiSi 2 is formed remained without being etched, titanium silicide for ohmic contact to Si (TiSi 2)
Electrodes and lead wiring structure that is formed (FIG. 8
(C) reference). Aqueous solution in the present embodiment, although the method of TiSi 2, where the etching after silicide formation by mixing and, for
example, HCl and H 2 O 2 and H 2 O in the case of using other metals, such as Co it may be used.
[0077] In formation of the ultrastructure, are essential patterning by dry etching process. However, if the hard perform dry etching as CuSi is effective wet
etching. That is, to form a silicon layer patterned in a predetermined shape on the high-melting point metal. By dry etching, by performing the ne patterning
in the silicon it is easy. Then, heat treatment was added, or it may be preceded by ion mixing, to form a silicide layer over the entire refractory metal layer.
Since only the high melting point metal portion in contact with silicon and has a silicide, substantially equal to the the width of the formed silicide with the
previously patterned have the width of the silicon layer. Then only the silicide by selective wet etch only unreacted refractory metal remains, it is possible to
manufacture a ne structure such as electrodes and wiring in a predetermined shape (see FIG. 8 (d)).
[0078] (Embodiment 6) FIG. 9 is a sectional view showing a sixth embodiment of the present invention. This embodiment is an electrode and a
semiconductor layer having a shallow Do junction depth, and an electrode structure of a compound of a semiconductor and a metal, and may form the
electrode and wiring structure in any lm thickness.
[0079] 901 is a semiconductor layer. Here, a silicon wafer as an example. The surface of the Si layer 901 is several places may be covered with an insulating
layer and a metal layer, Si
Diffusion layer impurities several places of the layer 901 is added may be formed. On the Si layer 901, the insulating lm layer such as SiO 2 layer 902 is
formed. On the surface of the wafer, the impurity concentration of the n-type part for example 1-2
× 10 20 cm -3 n + high concentration layer 903 are formed is an opening 904 part of the area of the high-concentration layer 903 to the SiO 2 902 as
conducting to the outside electrically can take
There has been provided at least one place.
[0080] On the insulating lm layer 902, so as to cover the opening 904, the metal layer, here, for example Ta layer 905-
1 is formed over on the entire surface of the wafer substantially at about 10nm thick. Metal layer 905-1 may, if silicon and stability reacted metal to form a
silicide compound Ti, W,
It may be another metal such as Pt. For the thickness, but may be thicker thinner than this value, it is uniformly formed a silicide layer, or considering the
utmost to prevent the generation of crystal defects during silicide formation, 5 to 10 nm approximately membrane it is best to to the thickness.
[0081] Further thereon, the resistivity of, for example 0.0

Si layer 906-1 including a very low concentration impurities of about 1~10kΩ · cm is formed about a thickness of about 22 nm. The thickness of the Si layer
906-1 may or may not limited to 22nm, but in this embodiment, be covered with a Si layer 906-1 surfaces completely of Ta layer 905-1 and, Si layer 906
-1 Considering that for the entire silicided to, for example, about 22 nm.
[0082] Subsequently, ion implantation is performed. The ion species to be implanted, for example, to implant As ions of n-type dopant. This is good may be
the P even Sb.
The implantation dose, for example as a 2 × 10 15 cm -2 order, 75 keV for example as an acceleration energy of the ions
And the (see FIG. 9 (a) so far).
[0083] on the Si layer 906-1 is a metal layer, wherein the, for example Ta layer 905-2 is formed over the wafer over the entire surface substantially in the
order of 10nm thickness. Metal layer 905-
2, in some cases may be other metals, metal layers 905-
It is optimally 1 and of the same material. For the thickness, but it may be thicker thinner than this value, it is uniformly formed a silicide layer, or considering
that prevent as much as possible the occurrence of crystal defects during silicide formation, 5-1
It is best to a thickness of about 0 nm. Its On, Si layer 906-2 resistivity containing very low concentration impurities of, for example, about 0.01~10kΩ · cm is
formed to a thickness of about about 22nm further. The thickness of the Si layer 906-2 may or may not limited to 22nm, but in this embodiment, the
complete surface of the Ta layer 905-2 Si layer 906-2
Or it is covered by, considering that to silicide the entire Si layer 906-2, for example, set to about 22 nm (refer to FIG. 9 (b) so far).
[0084] Thereafter, in consideration of the thickness of the formed desired silicide layer, the formation of the silicon layer forming a metal layer to the metal
layer may be repeated any number of times, but repeated twice in this embodiment, the nal the pair of the metal layer and the silicon layer was formed, for
example four layers in manner. Ta layer 905-3 and 90
5-4, Si layer is 906-3 and 906-4 (see FIG. 9 (c) so far).
[0085] was subjected to a subsequent heat treatment. For the method and conditions are exactly the same conditions as for heat treatment described in
Example 1. By heat treatment, tantalum silicide layer 9
07 is formed to a thickness of about 96nm in the thickness. In the present embodiment, although a metal layer and a pair of silicon layer to form 4 layers 96
nm, by controlling the formation number of layers, it is possible to control the thickness of the relatively freely silicide layer. The heat treatment in this
embodiment the was performed once after formation of the nal lm, if Si layer 906-2 formed later may be performed at least once for any number of times
to heat treatment at any time . Further, if the Si layer 906-2 formed after the ion implantation may be performed any number of times at any time. After the
silicide layer 907 formed to prepare an electrode-wiring structure and patterned to arbitrary shape (see FIG. 6 (d) so far).
[0086] By this method, the contact electrode of the silicide and silicon having a very shallow junction was formed. As also noted in Example 1, the results of
the performance of the contact formation step, the dopant concentration becomes the maximum at the interface, yet, as a result of contamination, such as
oxygen is thoroughly reduced, very low contact resistance the could be realized.
[0087] The contact portion, in order to suppress the crystal defects caused by the difference in stress strain or lattice constant, caused by the thermal stress
during the silicide formation, a metal lm thickness as thin as possible is desirable. However, considering the problem of wiring resistance or breakage, in
order to form the lead-out wires and the contact electrode by silicidation at the same time, the metal lm thickness as much as possible thicker is desirable.
By using the manufacturing method shown in this embodiment, while thoroughly suppressing the generation of crystal defects by using a silicide layer
having a certain thickness, it can produce a lead wiring structure as the contact electrode at the same time, yet, the electrical characteristics It is also
excellent and, moreover, in the contact portion, the depth of penetration into the silicon layer even ultra-shallow reduction can be realized caused by silicide
formation. Therefore,
Semiconductor device manufacturing method according to the present embodiment, high performance ULSI
It can be said to be very bene cial for the realization of the.
[0088]
According to the present invention, formation of a metal electrode having a very low contact resistance, and enables achievement of very shallowing of the
junction depth, of the ultra-high density, ultra high performance and reliability ULSI realization is possible.
BRIEF DESCRIPTION OF THE DRAWINGS
[1] is a conceptual diagram showing a rst embodiment of the present invention, it is a conceptual view showing a method of manufacturing an ohmic
contact electrode to the silicon-enriched by silicide electrode in the order of steps.
2 is a graph showing a contact resistance between the electrode and the semiconductor in Example 1.
3 is a graph showing an impurity concentration distribution in a depth direction in the electrode structure of the rst embodiment.
[Figure 4] is a conceptual diagram showing a second embodiment of the present invention, p

Method for producing n junction diode structure is a conceptual diagram showing the order of steps.
[Figure 5] Example 2 diode current - is a graph showing the voltage characteristic.
6 is a conceptual diagram showing a third embodiment of the present invention, it is a conceptual diagram illustrating the steps of the production method of
the joining structure between the silicide and the semiconductor having a very shallow junction.
7 is a fourth embodiment of the present invention, is a conceptual diagram illustrating a method for manufacturing a multilayer wiring structure in the order
of steps with high reliability.
8 is a conceptual diagram showing a fth embodiment of the present invention is a conceptual diagram showing a manufacturing method of an electrode
and wiring shape due to silicide formation in the order of steps.
[Figure 9] is a sixth schematic view showing an embodiment of the present invention, silicide and a is very shallow junction depth of the silicon, and high
reliability silicide electrode-concept manufacturing method shown in the order of steps of the wiring structure it is a diagram.
10 is a conceptual diagram showing the contact between the prior art electrodes and the semiconductor.
11 is a graph showing a contact resistance between the prior art electrodes and the semiconductor.
12 is a graph showing an impurity concentration distribution in a depth direction in the electrode structure of the prior art.
In [13] the prior art, it is a conceptual diagram showing the depth of the silicide-silicon bonding surface.
14 is a conceptual diagram showing another example of a multilayer wiring structure of the present invention.
DESCRIPTION OF SYMBOLS
101 semiconductor, 102 an insulating layer, 103 high-concentration semiconductor layer, 104 opening, 105 metal layers, 106 a semiconductor layer, 107
compound layer between the semiconductor and the metal, 108 metal layers, 403 high-concentration semiconductor layer, the 407 semiconductor and
metal compound layer, 408 a metal layer, 601 a semiconductor, 602 an insulating layer, 603 opening, 604 metal layers, 605 a semiconductor layer, 606
compound layer between the semiconductor and the metal, x j junction depth, 701 semiconductor, 702 an insulating layer, 703 an opening Department, 704
metal layers, 705 a semiconductor layer, a compound layer of 706 semiconductor and a metal, 707 insulating layers, 708 opening, 709 metal layers, 710
compound layer between the semiconductor and the metal, 711 metal layers, 801 a semiconductor, 802 an insulating layer , 803 opening, 804 metal layers,
805 a semiconductor layer, 806 compound layer between the semiconductor and the metal, 901 semiconductor, 902 an insulating layer, 903 high-
concentration semiconductor layer, 904 opening, 905-1, -2, -3, -4 metal layer, 906-1, -2, -3, -4 semiconductor layer, and 907 a semiconductor compound layer
with the metal, 1001 semiconductor, 1002 an insulating layer, 1003 a high concentration semiconductor layer, 1004 opening, 1005 metal layer 1006
compound layer between the semiconductor and the metal, 1007 metal layer, 1401,1404 interlayer insulating lm, 1402 a rst Al alloy wires, 1403,1407,1408
undoped Si layer, 1405 selective growth of tungsten (W), 1406 second Al alloy wiring.
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Publication number Priority date Publication date Assignee Title
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Machines Corporation
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JPH025521A * 1988-06-24 1990-01-10 Fujitsu Ltd Manufacture of semiconductor device
EP0499855A3 * 1991-02-21 1992-10-28 Texas Instruments Method and structure for microelectronic device incorporating low-
Incorporated resistivity straps between conductive regions
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Cited By (2)
Publication number Priority date Publication date Assignee Title
Family To Family Citations
US6449482B1 * 1995-05-24 2002-09-10 Telefonaktiebolaget Creation of overlapping cells when using multi casting
Lm Ericsson (Publ)
US6090707A * 1999-09-02 2000-07-18 Micron Technology, Method of forming a conductive silicide layer on a silicon comprising
Inc. substrate and method of forming a conductive silicide contact
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JP4197607B2 2008-12-17 Manufacturing method of semiconductor device including insulated gate eld effect transistor
US5316977A 1994-05-31 Method of manufacturing a semiconductor device comprising metal silicide
US5665646A 1997-09-09 Method for manufacturing semiconductor device with low electric resistance silicide layer on silicon surface
EP2022085B1 2014-10-15 Method for forming self-aligned metal silicide contacts
KR100515805B1 2005-09-21 method for forming a silicide region on a silicon body
JP3781666B2 2006-05-31 Method for forming gate electrode and gate electrode structure
US8202799B2 2012-06-19 Methods of manufacturing metal-silicide features
TWI255007B 2006-05-11 Method of fabricating a semiconductor device having reduced contact resistance
JP5309454B2 2013-10-09 Manufacturing method of semiconductor device
US4551908A 1985-11-12 Process of forming electrodes and interconnections on silicon semiconductor devices
JP4722448B2 2011-07-13 Method for reducing contact resistance in a semiconductor connection region
US6562718B1 2003-05-13 Process for forming fully silicided gates
US7015126B2 2006-03-21 Method of forming silicided gate structure
US6365516B1 2002-04-02 Advanced cobalt silicidation with in-situ hydrogen plasma clean
JP2005150752A 2005-06-09 Method of forming nickel silicide lm and method of manufacturing semiconductor device using same
EP0126424A2 1984-11-28 Process for making polycide structures
US6020254A 2000-02-01 Method of fabricating semiconductor devices with contact holes
US7084061B2 2006-08-01 Methods of fabricating a semiconductor device having MOS transistor with strained channel
US8101518B2 2012-01-24 Method and process for forming a self-aligned silicide contact
TWI321831B 2010-03-11 Method for integration of silicide contacts and silicide gate metals
US7666748B2 2010-02-23 Method of forming amorphous source/drain extensions
US5937325A 1999-08-10 Formation of low resistivity titanium silicide gates in semiconductor integrated circuits
Priority And Related Applications
Priority Applications (5)
Application Priority date Filing date Title
JP20674193 1993-08-20
JP5-206741 1993-09-02
JP5-218889 1993-09-02
JP21888993 1993-09-02
JP29078693A 1993-08-20 1993-11-19 Manufacturing method of semiconductor device
Applications Claiming Priority (3)
Application Filing date Title
JP29078693A 1993-11-19 Manufacturing method of semiconductor device
PCT/JP1994/001373 1994-08-19 Semiconductor device and its manufacture
EP94924391A 1994-08-19 Semiconductor device and its manufacture
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Concepts
machine-extracted Download Filter table
Name Image Sections Count Query match
semiconductor abstract,title 6 0
manufacturing process title 1 0
layers abstract 17 0
metal abstract 4 0
metals abstract 4 0
moulding (composite fabrication) abstract 4 0
silicide(4-) abstract 3 0
Si-4
silicides abstract 3 0
coesite abstract 1 0
compounds abstract 1 0
cristobalite abstract 1 0
extraction abstract 1 0
heat treatment abstract 1 0
ion implantation abstract 1 0
ions abstract 1 0
patterning abstract 1 0
quartz abstract 1 0
silicium dioxide abstract 1 0
O Si O
silicon dioxide abstract 1 0
stishovite abstract 1 0
thin lms abstract 1 0
tridymite abstract 1 0
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Semiconductor Device and Its Manufacture

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Semiconductor Device and Its Manufacture

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2/7/2020 JPH07122519A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Application JP29078693A events

View 2 more classi cations 2005-08-31 Application granted

2005-08-31 Publication of JP3688727B2

2013-11-19 Anticipated expiration

2020-02-07 Application status is Expired - Fee Related

Show all events

Info: Patent citations (4), Cited by (2), Legal events, Similar

External links: Espacenet, Global Dossier, Discuss

Claims (23) Hide Dependent

5. Injection volume wherein said ions, 1x10 13 to 4

8. Wherein said metal layer is, Ta, Ti, W, Co,

Description translated from Japanese

DETAILED DESCRIPTION OF THE INVENTION

The impurity concentration of the n-type part is the 2 × 10 20 cm -3 n +

Furthermore, the metal layer, Ta, Ti, W, C

Further, the semiconductor layer, the impurity concentration 1x

[0023] In the method of the present invention,

EXAMPLES Hereinafter, Examples illustrate the invention in more detail.

[0043] A second embodiment (Embodiment 2) The present invention FIG. 4

[0051] subjected to a heat treatment, silicide layer (TaSi

[0060] The multilayer interconnection structure forming method of this embodiment,

[0071] However, the solution to etch the metal,

[0072] Further thereon, the resistivity of, for example 0.0

[0081] Further thereon, the resistivity of, for example 0.0

BRIEF DESCRIPTION OF THE DRAWINGS

[Figure 4] is a conceptual diagram showing a second embodiment of the present invention, p

[Figure 5] Example 2 diode current - is a graph showing the voltage characteristic.

Patent Citations (4)

Publication number Priority date Publication date Assignee Title

Family To Family Citations

JPH0831598B2 * 1985-07-03 1996-03-27 株式会社日立製作所 A method of manufacturing a semiconductor device

JPH025521A * 1988-06-24 1990-01-10 Fujitsu Ltd Manufacture of semiconductor device

* Cited by examiner, † Cited by third party

Publication number Priority date Publication date Assignee Title

Family To Family Citations

* Cited by examiner, † Cited by third party, ‡ Family to family citation

Publication Publication Date Title

JP2857006B2 1999-02-10 Self-aligned cobalt silicide on Mos integrated circuits

EP0091775B1 1988-06-22 A method of manufacturing a semiconductor device comprising an interconnection layer

US5316977A 1994-05-31 Method of manufacturing a semiconductor device comprising metal silicide

EP2022085B1 2014-10-15 Method for forming self-aligned metal silicide contacts

KR100515805B1 2005-09-21 method for forming a silicide region on a silicon body

US8202799B2 2012-06-19 Methods of manufacturing metal-silicide features

JP5309454B2 2013-10-09 Manufacturing method of semiconductor device

US6562718B1 2003-05-13 Process for forming fully silicided gates

US7015126B2 2006-03-21 Method of forming silicided gate structure

EP0126424A2 1984-11-28 Process for making polycide structures

US6020254A 2000-02-01 Method of fabricating semiconductor devices with contact holes

US7666748B2 2010-02-23 Method of forming amorphous source/drain extensions

Priority And Related Applications

Priority Applications (5)

Application Priority date Filing date Title

JP29078693A 1993-08-20 1993-11-19 Manufacturing method of semiconductor device

Applications Claiming Priority (3)

Application Filing date Title

JP29078693A 1993-11-19 Manufacturing method of semiconductor device

PCT/JP1994/001373 1994-08-19 Semiconductor device and its manufacture

EP94924391A 1994-08-19 Semiconductor device and its manufacture

Date Code Title Description

Effective date: 20050422

Free format text: JAPANESE INTERMEDIATE CODE: A61