Institute of Space Technology DLD Lab (Engr. M.

Jaleed Khan)

Introduction to ModelSim and Verilog HDL

ModelSim is a simulation environment for simulation of hardware description languages (HDLs) such as
VHDL, Verilog and SystemC. In this lab, we will use ModelSim for simulation of digital systems described
using Verilog HDL.

1. ModelSim Installation

Follow the following steps to install ModelSim:

a. Run “Setup.exe”.
b. Follow the following screen shots to proceed with the installation:
Institute of Space Technology DLD Lab (Engr. M. Jaleed Khan)
Institute of Space Technology DLD Lab (Engr. M. Jaleed Khan)
Institute of Space Technology DLD Lab (Engr. M. Jaleed Khan)
Institute of Space Technology DLD Lab (Engr. M. Jaleed Khan)
Institute of Space Technology DLD Lab (Engr. M. Jaleed Khan)

c. Open “Patch.exe” and apply patch to MGLS.DLL, VLM.EXE and MODELSIM.EXE one by one in
“C:\Modeltech_5.7g\win32” directory
Institute of Space Technology DLD Lab (Engr. M. Jaleed Khan)
Institute of Space Technology DLD Lab (Engr. M. Jaleed Khan)

d. Copy “license.dat” file to “C:\Modeltech_5.7g\win32” directory

e. Create a new folder in “C:” drive named “flexlm”, and copy “license.dat” to “C:\flexlm”
Institute of Space Technology DLD Lab (Engr. M. Jaleed Khan)

2. Using ModelSim for Verilog HDL Simulation

Follow the following steps to simulate a simple AND gate in Verilog HDL.

a. Open ModelSim.
b. Create a new project named “DLD_Lab” and a new Verilog source file named “and_gate”.
Institute of Space Technology DLD Lab (Engr. M. Jaleed Khan)

c. Edit “and_gate.v” from workspace by double-clicking it, add the AND gate implementation code in
this file and save it.

d. Right-click in the workspace and create a new file in the same project names “testbench”.
Institute of Space Technology DLD Lab (Engr. M. Jaleed Khan)

e. Open “testbench.v” and add the Verilog code to simulate the AND gate module that we previously
implemented.

f. Click on the “Compile All” icon to compile both Verilog source files.
Institute of Space Technology DLD Lab (Engr. M. Jaleed Khan)

g. After successful compilation, click on the “Simulate” icon and select “work/testbench”.

h. After both modules have been successfully loaded, right click on “testbench”, click “Add > Add to
Wave”
Institute of Space Technology DLD Lab (Engr. M. Jaleed Khan)

i. A new waveform window will appear. Click on “Run” icon several times to run the simulation and
check the waveform depicting the working of AND gate module implemented in Verilog HDL.

j. Now, this procedure will be followed in each Verilog experiment to create new modules
representing digital circuit elements and simulate them using a testbench module.