DIGITAL CIRCUITS

Parameters of the integrated logic circuits

•Static transfer characteristic

•Noise margins
•Fan-out & fan-in
•Propagation time
•Power Dissipation
 Static Transfer Characteristic
• Output voltage variation function of input dc
voltage
• Cann’t be defined an unique voltage value for
logic ‘1’ or ‘0’
• Transfer characteristic isn’t unique
• characteristic bounded by two limit curves
• to each input or output variable, two voltage
intervals (domains) will be associated: allowed,
and respectively guaranteed
Static Transfer Characteristic for an Inverter

• Four
voltage
ranges
• Two for
inputs
• Two for
outputs
• Defined by
eight
voltage
values
 Input/Output voltage values
• VILmin – minimum voltage level for logic ‘0’ at input
• VILmax - maximum voltage level for logic ‘0’ at input
• VIHmin - minimum voltage level for logic ‘1’ at input
• VIHmax - maximum voltage level for logic ‘1’ at input
• VOLmin - minimum voltage level for logic ‘0’ at output
• VOLmax - maximum voltage level for logic ‘0’ at output
• VOHmin - minimum voltage level for logic ‘1’ at output
• VOHmax - maximum voltage level for logic ‘1’ at output
Index meaning
I – input
O – output
L – low logic ‘0’
H - high logic ‘1’
 Defining the working regions
• A logic circuit will work properly if the input voltage
levels will have admitted values (work in allowed
regions)
• Obtained output voltage levels will be into guaranteed
regions
• Considering that output voltage will become input
voltage for driven circuit(s), have five working regions:
– Normal working region for logic ‘0’ and logic ‘1’
– Working region in presence of noise signals for logic ‘0’ and
respectively ‘1’
– Transitory region
 Normal working region (no noise signals)

• For low input voltage level (L), between

values VIL2 - VIL1
• For high input voltage level (H) between
values VIH2 - VIH1
 Working region when noise signals apply

• For low input voltage level (L), between

values VILmax – VILmin
• For high input voltage level (H) between
values VIHmax - VIHmin
 Transitory region

• For input voltage levels between VIHmin –

VILmax
• Those input voltages driving circuit from one
stable state to the other
 Noise margins

• Noise (immunity) margins: stability at static

perturbations
• the noise margin is the peak amount of spurious or
"noise" voltage that may be superimposed on a weak
gate output voltage signal before the receiving gate
might interpret it wrongly
• Guaranteed noise margin for a logic state is given by
difference between guaranteed output voltage level of
the driving circuit and the worst case for the input
voltage level accepted for that state by the driven
circuit
 Guaranteed noise margins (manufacturer’s
specifications)

• For logic ‘0’ state:

ML=VILmax-VOLmax
• For logic ‘1’ state:
MH=VOHmin-VIHmin
Example for TTL family
 Fan-out and Fan-in
• The input of a circuit is a load for its driver
circuit
• For a logic circuit generates guaranteed output
voltage levels is a must to be driven at inputs
with corresponding current levels
• For circuit interconnection, important to design
the output current of the driving circuit, and to
consider the sum of input currents of the driven
circuits
 Fan-in factor for logic circuits
• Fan-in (FI) and Fan-out (FO) factors are defined
based on some current values, those
correspondind to allowed input voltages and
respectively to guaranteed output voltages, in
the worst case: IILmax, IIHmin, IOLmax şi IOHmin
• For any integrated circuits family, a basic
(fundamental) gate is defined, and the fan-in/
fan-out values for the rest of circuits are defined
as multiples of the values for that basic gate
• For an input, the FI value means the number N
(N>1) of standard inputs (i.e. of basic gate)
equivalent to that input: FI=N
 Fan-out factor for logic circuits
 I OL   I OH 
FOL =  , FOH =  , FO = min( FOL , FOH )
 I IL   I IH 

• When interconnecting logic circuits (from a

family), the following relations must be satisfied
(associate with the worst case):

i =1 i =1
I OL ≥ ∑ I IL , I OH ≥ ∑ I IH
n n
 Propagation Time

• Raising-up and fall-down

times (tr , tf) are defined
using ratios of signal
amplitude (0.1 and 0.9)
• Propagation times (delay) (tpHL si tpLH) are defined for halves the
input/output signal amplitudes
• Average propagation time: tpd=(tpHL+tpLH)/2
• Important parameter for any circuit, giving sign of performance
 Power Dissipation

• Parameter depending on:

–Power supply voltage (VCC);
–Absorbed currents from VCC when
output is logic ‘1’ (ICCH), or ‘0’ logic (ICCL);
–Output current on shortcircuit (IOS);
–Average power consumption (Pm);
 Average power dissipation on cc

P H + PL I CCH + I CCL
PCC = = ⋅ V CC
2 2
 Power dissipation on ac

• Important power component, due to charging/

discharging of stray output capacitances Cp
• Power consumption during the switching
regime:

2
PC = f CV P CC

f – switching frequency
 Total power dissipation

I + I CCL 2
P m = PCC + PC
= CCH
2 V CC
+f CV
P CC
 TTL Logic Integrated Circuits

• General considerations
• TTL standard series
–TTL basic (fundamental) gate
–Circuit description
–Gate operation
–Parameters of TTL basic gate
 General Considerations

• TTL (Transistor-Transistor-Logic)
• Family with a lot of circuit series,
developed based on a trade-off between
propagation speed and power dissipation
• Standard, high-speed (H), Low power (L),
Schottky (S)
TTL Basic Gate

Input stage
• Multi-emitter transistor
T1
• Clipping diodes D1, D2
Driver transistor
• Transistor T2
Output stage
• transistors T4 şi T3
• diode D
Gate operation for one input ‘0’

• T1 saturated, voltage from

T1 collector lowers,
transistor T2 off
• Low voltage level from T2
emitter drives T3off
• High potential of T2
collector opens transistor
T4
• UR2 low, UBE(T4)+UD≈1,5V,
Ue>3,4V corresponding to
logic level "1"
Gate operation when both inputs at logic ‘1’

• T1 base-emitter junctions
reverse biased (reverse active
region)
• T1 base-collector junction and
base-emitter junctions of T2 &
T3 make a chain of open
diodes (forward biased by R1
from power supply), T2 & T3
saturated
• T4 off due to base potential,
lower than emitter’s, due to
presence of diode D
• Ue=UCES(T3) corresponding to
logic "0"
 Ue = A* B

• Transistors T4 & T3 switch in counter-time,

making R4 being low (130Ω), building a
low output impedance and a small time
constant for charge/discharge of output
stray capacitances
 Logic Levels

• VILmax = 0.8 V
• VIHmin = 2 V
• VOLmax = 0.4 V
• VOHmin = 2.4 V
• VT = 1.3V, threshold voltage, same
value for input and output voltages
 Noise Margins

• Guaranteed values
ML = VILmax – VOLmax = 0.8V – 0.4V = 0.4V
MH = VOHmin – VIHmin = 2.4V – 2V = 0.4V
• Real values
ML = VT – VOL = 1.3V – 0.2V = 1.1V
MH = VOH – VT = 3.5V – 1.3V = 2.2V
• It implies that prefered output idle state being '1'
logic, and switching command being ‘zero
active’, i.e. a signal going from high to low
 Input & output currents

• By convention: positive value if gate

sinks current and negative value if gate
generates currents
• IIH = 40 µA
• IIL = -1,6 mA
• IOH = -800 µA
• IOL = 16 mA
 Fan-in/ fan-out

FIL = 1, IIL = - 1,6mA

FIH = 1, IIH = 40µA

 I OL   16mA   800µA 
FOL =  =  = 10, FOH =   = 20, FO = min( FOL , FOH ) = 10
 I IL  1.6mA   40 µA 
 Static transfer characteristic
0V<Ui<0,65V, T1 on, T2 off, Ue = VCC - R2·IR2 - UBE(T4) – VD,
UBE(T4)=VD=0,75V, IR2 ≈ IB(T4) = IOH/(ßN+1), Ue=3,4V, on AB
segment.
0,65V<Ui<1,3V, T2 starts conducting, going into forward active
region. Current gain for transistor T2 over segment BC is:
α ≈ -R2/R3. T4 repeater, T3 off, state for segment BC.
1,3V<Ui<1,5V, T3 starts
conducting, Ue lowers quikly
(segment CD). T2, T4 and T3
conducting into forward
active region. Current sink
from the power supply
increases.
1,5V<Ui<2,25V, T4 off, T3
saturated, Ue=UCEs(T3) ≈
0,2V, region DE.
Input Characteristics
• Vi < 0,8V
V CC - V BE(T1) - V I
II =
R1

• Vi grows over 0,8V, Ii lowers

in absolute value
• Vi > 1,3V, Ii tends abruptly
toward 0
• Vi = 1,7V, Ii=0
• Vi > 2 ÷ 2,25V, Ii ≈ 28µA
Output Characteristics
• VOL = f(IOL)
• IOL depends on T3 base
current, wich depends on T2
emitter current, as:
V CC - V BE(T3) - V CEs(T2)
I C(T2) =
R2
V CC - V BC(T1) - V BE(T2) - V BE(T3)
I B(T2) =
R1
IE(T2) = IB(T2) + IC(T2) =3,2mA
V BE(T3)
I B(T3) = I E(T2) - I 3= I E(T2) -
R3

T3 saturated, ßN=20, output current:

IOL = ßN·IB(T3) = 49mA
IOL
Output Characteristics
• VOH = f(IOH)
• Figure below presents in positive domain
VOH=f(IS) characteristics, where load current IS
is considered IS= -IOH
• T4 on, tending toward saturation
• T4 when in forward active region, segment 1,
VOH and IS are in relation:
IS -
V O = V CC - R 2 V BE(T4) - V D
β N +1

VOH= 3,7 - 32·IS

• T4 saturated, curve 2, relation becomes:

V CC - V O - V D - V BE(T4) V CC - V O - V D - V CE(T4)
I S = I E(T4) = I B(T4) + I C(T4) = +
R2 R4
IS
VO ≈ 4,5 - IS·R4
• Curves 1 and 2 cross eachother at IS ≈ 5mA
 Power dissipation
I CCH + I CCL
PCC = V CC
2

ICCH=IR1=(VCC-VB(T1))/R1≈1mA
ICCL=IE(T2)=IC(T2)+IB(T2)=(VCC - VC(T2))/R2+(VCC-VB(T1))/R1≈3,3mA
PCC ≈ 10mW
PC=CpVCC2f
Cp=15pF; f=1MHz, PC≈0,4mW; f=20MHz, PC≈7,5mW
• Besides the two components PCC and PC, there is another, due
to simultaneous conduction of transistors T3 and T4. This extra
power consumption PDS has the formula:

= ( I CCmax ⋅ t c + I CCmax ⋅ t r )
P DS V CC
2.2 T 2 T
 Propagation Delay
• Given by charging/discharging times of stray capacitance from
gate’s output and by switching times of transistors
• tpHL = tc1 + tdes
• tpLH = tc2 + tinc
• tpd = (tpHL + tpLH)/2
• Switching times: tc1 = 5ns and tc2 = 8ns
• Charging/discharging times of stray capacitances:
V OH - V OL V OH - V OL
t des = C p t inc = C p
I OL I OH
• Formula for tinc, short-circuit current value is considered IOS
• For IOS = 18mA results tinc = 2.5ns
• Calculated values: tpHL = 8ns şi tpLH = 10.5ns
• Data book values: tpHL = 8ns and tpLH= 12ns, resulting tpd = 10ns
 Proposed Problems
• Find out the maximum value of a resistor may be connected
between two standard TTL gates, without modifying the circuit
behavior. How this resistor is affecting the noise margins?
• Design a circuit based on a NAND TTL standard gate, able to
drive a LED. For the LED, following values are considered:
VLED=1,6V and ILED=10mA.
• Design a circuit based on a NOR TTL standard gate, able to
drive a LED. For the LED, following values are considered:
VLED=0,65V and ILED=20mA.
• Design a positive edge detector circuit, using NAND gates.
• If a pulse train signal is propagating through a NAND gate, how
this influences the filling factor of one pulse? But if propagating
through two NAND gates? Input signal has a 20MHz frequency
and a filling factor of ½.