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Microprocessor Notes
Microprocessor Notes
Microprocessor Architecture
The microprocessor is the CPU (Central Processing Unit) of a computer. It is the heart of the computer.
Here, we will describe Intel 8085 as it is one of the most popular 8-bit microprocessor.
Intel 8085
Intel 8085 is an 8-bit, NMOS microprocessor designed by Intel in 1977.
Intel 8085 is used in mobile phones, microwave ovens, washing machines etc.
ALU
The Arithmetic and Logic Unit, ALU performs the arithmetic and logical operations:
o Addition
o Subtraction
o Logical AND
o Logical OR
o Logical EXCLUSIVE OR
o Complement (Logical NOT)
o Increment (add 1)
o Decrement (subtract 1)
o Left shift, Rotate left, Rotate right
o Clear, etc.
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o It is used to generate timing and control signals which are necessary for the execution of
instructions.
o It is used to control data flow between CPU and peripherals (including memory).
o It is used to provide status, control and timing signals which are required for the operation of
memory and I/O devices.
o It is used to control the entire operations of the microprocessor and peripherals connected to it.
Thus we can see that the control unit of the CPU acts as the brain of the computer system.
Registers
Registers are used for temporary storage and manipulation of data and instructions by the
microprocessor. Data remain in the registers till they are sent to the I/O devices or memory. Intel 8085
microprocessor has the following registers:
In addition to the above mentioned registers the 8085 microprocessor contains a set of five flip-flops
which serve as flags (or status flags).
A flag is a flip-flop which indicates some conditions which arises after the execution of an arithmetic or
logical instruction.
a. Accumulator (ACC): The accumulator is an 8-bit register associated with the ALU. The register 'A'
is an accumulator in the 8085. It is used to hold one of the operands of an arithmetic and logical
operation.
The final result of an arithmetic or logical operation is also placed in the accumulator.
b. General-Purpose Registers: The 8085 microprocessor contains six 8-bit general purpose
registers. They are: B, D, C, E, H and L register.
To hold data of 16-bit a combination of two 8-bit registers can be employed.
The combination of two 8-bit registers is called register pair. The valid register pairs in the 8085
are: D-E, B-C and H-L. The H-L pair is used to act as a memory pointer.
c. Program Counter (PC): It is a 16-bit special purpose register. It is used to hold the address of
memory of the next instruction to be executed. It keeps the track of the instruction in a program
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while they are being executed.
The microprocessor increments the content of the next program counter during the execution of an
instruction so that at the end of the execution of an instruction it points to the next instruction?s
address in the program.
d. Stack Pointer (SP): It is a 16-bit special function register used as memory pointer. A stack is
nothing but a portion of RAM. In the stack, the contents of only those registers are saved, which
are needed in the later part of the program.
The stack pointer (SP) controls the addressing of the stack. The Stack Pointer contains the address
of the top element of data stored in the stack.
e. Instruction Register: The instruction register holds the opcode (operation code or instruction
code) of the instruction which is being decoded and executed.
f. Temporary Register: It is an 8-bit register associated with the ALU. It holds data during an
arithmetic/logical operation. It is used by the microprocessor. It is not accessible to programmer.
g. Flags: The Intel 8085 microprocessor contains five flip-flops to serve as a status flags. The flip-
flops are reset or set according to the conditions which arise during an arithmetic or logical
operation.
If a flip-flop for a particular flag is set, then it indicates 1. When it is reset, it indicates 0.
Pin Configuration
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o A8 ? A15 (Output): These are address bus and are used for the most significant bits of the
memory address or 8-bits of I/O address.
o AD0 ? AD7 (Input/output): These are time multiplexed address/data bus i.e. they serve dual
purpose. They are used for the least significant 8 bits of the memory address or I/O address during
the first cycle. Again they are used for data during 2nd and 3rd clock cycles.
o ALE (Output): ALE stands for Address Latch Enable signal. ALE goes high during first clock
cycle of a machine cycle and enables the lower 8-bits of the address to be latched either into the
memory or external latch.
o IO/M (Output): It is a status signal which distinguishes whether the address is for memory or
I/O device.
o S0, S1 (Output): These are status signals sent by the microprocessors to distinguish the various
types of operation given in table below:
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Status codes for Intel 8085
S1 S0 Operations
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH
o RD (Output): RD is a signal to control READ operation. When it goes low, the selected I/O
device or memory is read.
o WR (Output): WR is a signal to control WRITE operation. When it goes low, the data bus' data
is written into the selected memory or I/O location.
o READY (Input): It is used by the microprocessor to sense whether a peripheral is ready to
transfer a data or not. If READY is high, the peripheral is ready. If it is low the micro processor
waits till it goes high.
o HOLD (INPUT): HOLD indicates that another device is requesting for the use of the address and
data bus.
o HLDA (OUTPUT): HLDA is a signal for HOLD acknowledgement which indicates that the HOLD
request has been received. After the removal of this request the HLDA goes low.
o INTR (Input): INTR is an Interrupt Request Signal. Among interrupts it has the lowest priority.
The INTR is enabled or disabled by software.
o INTA (Output): INTA is an interrupt acknowledgement sent by the microprocessor after INTR
is received.
o RST 5.5, 6.5, 7.5 and TRAP (Inputs): These all are interrupts. When any interrupt is
recognized the next instruction is executed from a fixed location in the memory as given below:
TRAP 0024
The TRAP has the highest priority among interrupts. The order of priority of interrupts is as follows:
Reset Signals
o RESET IN (Input): It resets the program counter (PC) to 0. It also resets interrupt enable and
HLDA flip-flops. The CPU is held in reset condition till RESET is not applied.
o RESET OUT (Output): RESET OUT indicates that the CPU is being reset.
Clock Signals
o X1, X2 (Input): X1 and X2 are terminals to be connected to an external crystal oscillator which
drives an internal circuitry of the microprocessor. It is used to produce a suitable clock for the
operation of microprocessor.
o CLK (Output): CLK is a clock output for user, which can be used for other digital ICs. Its
frequency is same at which processor operates.
o SID (Input): SID is data line for serial input. The data on this line is loaded into the seventh bit
of the accumulator when RIM instruction is executed.
o SOD (Output): SOD is a data line for serial output. The seventh bit of the accumulator is output
on SOD line when SIM instruction is executed.
Power Supply
8085 Instructions
An instruction of computer is a command given to the computer to perform a specified operation on
given data. Some instructions of Intel 8085 microprocessor are: MOV, MVI, LDA, STA, ADD, SUB, RAL,
INR, MVI, etc.
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The 1st part of an instruction which specifies the task to be performed by the computer is called Opcode.
The 2nd part of the instruction is the data to be operated on, and it is called Operand. The Operand (or
data) given in the instruction may be in various forms such as 8-bit or 16-bit data, 8-bit or 16-bit address,
internal registers or a register or memory location.
According to the word size, the Intel 8085 instructions are classified into the following three
types:
All the above two examples are only one byte long. All one-byte instructions contain information regarding
operands in the opcode itself.
2. Two-byte instruction: In a two byte instruction the first byte of the instruction is its opcode and the
second byte is either data or address.
Example:
The first byte 06 is the opcode for MVI B and second byte 05 is the data which is to be moved to register
B.
3. Three-byte instruction: The first byte of the instruction is its opcode and the second and third bytes
are either 16-bit data or 16-bit address.
Example:
The first byte 21 is the opcode for the instruction LXI H. The second 00 is 8 LSBs of the data (2400H),
which is loaded into register L. The third byte 24 is 8 MSBs of the data (2400H), which is loaded into
register H.
Instruction Cycle
The time required to fetch an instruction and necessary data from memory and to execute it, is called
an instruction cycle. Or the total time required to execute an instruction is given by:
IC = FC + EC
Where,
IC = Instruction Cycle
FC = Fetch Cycle
EC = Execute Cycle
In the beginning of the fetch cycle, the content of the program counter (PC), which is the address of the
memory location where opcode is available, is sent to the memory. The memory puts the opcode on the
data bus so as to transfer it to the CPU.
The whole operation of fetching an opcode takes three clock cycles. A slow memory may take more time.
The opcode fetched from the memory goes to the data register, DR and then to instruction register, IR.
From the IR it goes to the decoder circuitry which decodes the instruction. Decoder circuitry is within the
microprocessor.
If the operand is reside the general purpose registers, execution is immediately performed. The time
taken in decoding and execution of an instruction is one clock cycle.
In some situations, an execute cycle may involve one or more read or write cycles or both.
Read Cycle: If an instruction contains data or operand address which are in the memory, the CPU has to
perform some read operations to get the desired data. In case of a read cycle the instruction received
from the memory are data or operand address instead of an opcode.
Write Cycle: In write cycle data are sent from the CPU to the memory or an output device.
The necessary steps carried out to perform the operation of accessing either memory or input output
device, constitute a machine cycle. In other words, necessary steps carried out to perform a fetch, a
read or a write operation constitutes a machine cycle.
One sub-division of an operation performed in one clock cycle is called a state or T-state. In short, one
clock cycle of the system clock is referred to as a state.
Timing Diagram
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The necessary steps carried out in a machine cycle can be represented graphically. Such a graphical
representation is called timing diagram. The timing diagram for opcode fetch, memory read, memory
write, I/O read and I/O write will be discussed below:
ALE: ALE indicates the availability of a valid address on the multiplexed address/data lines. When it is
high or 1, then it acts as an address bus and when low or 0, then it acts as a data bus.
RD (low active): If it is high or 1, then no data is read by the microprocessor. If signal is low or 0, then
data is read by the microprocessor.
WR (low active): If it is high or 1, then no data is written by the microprocessor. If signal is low or 0,
then data is written by the microprocessor.
IO/M (low active): A high or 1 on this signal indicates I/O operation while a low or 0 indicates memory
operation.
The below table, shows the status of different control signal for different operation:
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Immediate Mode
In this mode, the operand is specified in the instruction itself. An immediate mode instruction has an
operand field rather than the address field.
For example: ADD 7, which says Add 7 to contents of accumulator. 7 is the operand here.
Register Mode
In this mode the operand is stored in the register and this register is present in CPU. The instruction
has the address of the Register where the operand is stored.
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Advantages
Disadvantages
Instruction Cycle
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An instruction cycle, also known as fetch-decode-execute cycle is the basic operational process of
a computer. This process is repeated continuously by CPU from boot up to shut down of computer.
Following are the steps that occur during an instruction cycle:
The cycle is then repeated by fetching the next instruction. Thus in this way the instruction cycle is
repeated continuously.
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Addressing Modes-
The different ways of specifying the location of an operand in an instruction are called
as addressing modes.
1. Implied / Implicit Addressing Mode
2. Stack Addressing Mode
3. Immediate Addressing Mode
4. Direct Addressing Mode
5. Indirect Addressing Mode
6. Register Direct Addressing Mode
7. Register Indirect Addressing Mode
8. Relative Addressing Mode
9. Indexed Addressing Mode
10. Base Register Addressing Mode
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11. Auto-Increment Addressing Mode
12. Auto-Decrement Addressing Mode
In this article, we will discuss about these addressing modes in detail.
Examples-
Example-
ADD
This instruction simply pops out two symbols contained at the top of the stack.
The addition of those two operands is performed.
The result so obtained after addition is pushed again at the top of the stack.
Examples-
The address field of the instruction contains the effective address of the operand.
Only one reference to memory is required to fetch the operand.
It is also called as absolute addressing mode.
Example-
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ADD X will increment the value stored in the accumulator by the value stored at memory location
X.
AC ← AC + [X]
The address field of the instruction specifies the address of memory location that contains the
effective address of the operand.
Two references to memory are required to fetch the operand.
Example-
ADD X will increment the value stored in the accumulator by the value stored at memory location
specified by X.
AC ← AC + [[X]]
Example-
ADD R will increment the value stored in the accumulator by the content of register R.
AC ← AC + [R]
NOTE-
It is interesting to note-
The address field of the instruction refers to a CPU register that contains the effective address of
the operand.
Only one reference to memory is required to fetch the operand.
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Example-
ADD R will increment the value stored in the accumulator by the content of memory location
specified in register R.
AC ← AC + [[R]]
NOTE-
It is interesting to note-
Effective address of the operand is obtained by adding the content of program counter with the
address part of the instruction.
Effective Address
= Content of Program Counter + Address part of the instruction
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NOTE-
Program counter (PC) always contains the address of the next instruction to be executed.
After fetching the address of the instruction, the value of program counter immediately increases.
The value increases irrespective of whether the fetched instruction has completely executed or not.
Effective address of the operand is obtained by adding the content of index register with the
address part of the instruction.
Effective Address
= Content of Index Register + Address part of the instruction
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Effective address of the operand is obtained by adding the content of base register with the
address part of the instruction.
Effective Address
= Content of Base Register + Address part of the instruction
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This addressing mode is a special case of Register Indirect Addressing Mode where-
In this addressing mode,
After accessing the operand, the content of the register is automatically incremented by step size
‘d’.
Step size ‘d’ depends on the size of operand accessed.
Only one reference to memory is required to fetch the operand.
Example-
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Assume operand size = 2 bytes.
Here,
After fetching the operand 6B, the instruction register R AUTO will be automatically incremented by 2.
Then, updated value of RAUTO will be 3300 + 2 = 3302.
At memory address 3302, the next operand will be found.
NOTE-
In auto-increment addressing mode,
This addressing mode is again a special case of Register Indirect Addressing Mode where-
In this addressing mode,
Example-
Assume operand size = 2 bytes.
Here,
Eg: - RLC
2. RRC: - Each binary bit of the accumulator is rotated right by one position. Bit D0 is placed in the
position of D7 as well as in the Carry flag. CY is modified according to bit D0. Any other bit is not
affected.
Eg: - RRC
3. RAL: - Each binary bit of the accumulator is rotated left by one position through the Carry flag. Bit D7 is
placed in the Carry flag, and the Carry flag is placed in the least significant position D0. CY is modified
according to bit D7.
Eg: - RAL
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4. RAR: - Each binary bit of the accumulator is rotated right by one position through the Carry flag. Bit D0
is placed in the Carry flag, and the Carry flag is placed in the most significant position D7. CY is modified
according to bit D0.
Eg: - RAR
Eg: - CMA
Eg: - CMC
Eg: - STC
Eg: - CMP B
CMP M
2. CPI: - (compare immediate with accumulator) The second byte (8-bit data) is compared with the
contents of the accumulator. The values being compared remain unchanged. The result of the
comparison is shown by setting the flags of the PSW as follows:
3. ANA: - logical AND operation is performed with the specified register or memory with accumulator.
Eg: - ANA B
ANA M
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4. ANI: - (AND operation with immediate data) AND operation is performed between accumulator and
specified immediate data.
5.XRA: - The content of accumulator are exclusive OR with specified register or memory location.
Eg: - XRA B
XRA M
6. XRI: - The content of accumulator are exclusive OR with the immediate data.
7. ORA: - Logical OR operation is performed between accumulator and specified register and memory
location.
Eg: - ORA B
ORA M
MOV M,Rs (This instruction copies the content of register Rs to memory location pointed by HL
Register)
MOV Rd, M (This instruction copies the content of memory location pointed by the HL
register to the register Rd.)
3.LDA: - Load accumulator. (this instruction copies the data from a given 16 bit address to the
accumulator)
4.LDAX(Load accumulator indirect): - The contents of the designated register pair point to a memory
location. This instruction copies the contents of that memory location into the accumulator. The contents
of either the register pair or the memory location are not altered.
Eg: - LDAX B
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5.LXI(Load register pair immediate): - The instruction loads 16-bit data in the register pair designated in
the
operand.
Eg: - LXI H, 2034H (2034H is stored in HL pair so that it act as memory pointer)
LXI H, XYZ (address of level XYZ is copied in HL pair)
6.LHLD(Load H and L register direct): - this instruction loads the contents of the 16- bit memory location
into the HL register pair.
Eg: - LHLD 3000H (the content of location 3000h is copied into the HL reg pair)
7.STA: - the content of accumulator are copied into the memory location.
Eg: - STA 3000H (the content of accumulator is stored into the memory location 3000h)
8.STAX(Store accumulator indirect): - The contents of the accumulator are copied into the memory
location specified by the contents of the operand (register pair). The contents of the accumulator are not
altered.
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Eg: - STAX B (the content of accumulator is stored into the memory location specified by the BC register
pair.)
9.SHLD(store H and L register direct): - The contents of register L are stored into the memory location
specified by the 16-bit address in the operand and the contents of H register are stored into the next
memory location by incrementing the operand. The contents of registers HL are not altered. This is a 3-
byte instruction, the second byte specifies the low-order address and the third byte specifies the high-
order address.
1. Control
2. Logical
3. Branching
4. Arithmetic
5. Data Transfer
Control Instructions
Example: NOP
HLT none Halt and enter The CPU finishes executing the current instruction and halts any further
wait state execution. An interrupt or reset is necessary to exit from the halt state.
Example: HLT
DI none Disable The interrupt enable flip-flop is reset and all the interrupts except the TRAP
interrupts are disabled. No flags are affected.
Example: DI
EI none Enable The interrupt enable flip-flop is set and all interrupts are enabled. No flags
interrupts are affected. After a system reset or the acknowledgement of an interrupt,
the interrupt enable flipflop is reset, thus disabling the interrupts. This
instruction is
necessary to reenable the interrupts (except TRAP).
Example: EI
RIM none Read interrupt This is a multipurpose instruction used to read the status of interrupts 7.5,
mas 6.5, 5.5 and read serial data input bit. The instruction loads eight bits in the
accumulator with the following interpretations.
Example: RIM
SIM none Set interrupt This is a multipurpose instruction and used to implement the 8085
mask interrupts 7.5, 6.5, 5.5, and serial data output. The instruction interprets the
accumulator contents as follows.
Example: SIM
LOGICAL INSTRUCTIONS
CMP R Compare register The contents of the operand (register or memory) are M compared with
or memory with the contents of the accumulator. Both contents are preserved . The result
M accumulator
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of the comparison is shown by setting the flags of the PSW as follows:
CPI 8-bit Compare The second byte (8-bit data) is compared with the contents of the
data immediate with accumulator. The values being compared remain unchanged. The result
accumulator of the comparison is shown by setting the flags of the PSW as follows:
ANA R Logical AND The contents of the accumulator are logically ANDed with M the
register or memory contents of the operand (register or memory), and the result is placed in
M with accumulator the accumulator. If the operand is a memory location, its address is
specified by the contents of HL registers. S, Z, P are modified to reflect
the result of the operation. CY is reset. AC is set.
ANI 8-bit Logical AND The contents of the accumulator are logically ANDed with the
data immediate with 8-bit data (operand) and the result is placed in the
accumulator accumulator. S, Z, P are modified to reflect the result of the
operation. CY is reset. AC is set.
XRA R Exclusive OR The contents of the accumulator are Exclusive ORed with M the contents
register or memory of the operand (register or memory), and the result is placed in the
M with accumulator accumulator. If the operand is a memory location, its address is specified
by the contents of HL registers. S, Z, P are modified to reflect the result
of the operation. CY and AC are reset.
XRI 8-bit Exclusive OR The contents of the accumulator are Exclusive ORed with the 8-bit data
data immediate with (operand) and the result is placed in the accumulator. S, Z, P are
accumulator modified to reflect the result of the operation. CY and AC are reset.
ORA R Logical OR register The contents of the accumulator are logically ORed with M the contents
or memory with of the operand (register or memory), and the result is placed in the
M accumulator accumulator. If the operand is a memory location, its address is specified
by the contents of HL registers. S, Z, P are modified to reflect the result
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of the operation. CY and AC are reset.
ORI 8-bit Logical OR The contents of the accumulator are logically ORed with the 8-bit data
data immediate with (operand) and the result is placed in the accumulator. S, Z, P are
accumulator modified to reflect the result of the operation. CY and AC are reset.
RLC none Rotate accumulator Each binary bit of the accumulator is rotated left by one position. Bit D7
left is placed in the position of D0 as well as in the Carry flag. CY is modified
according to bit D7. S, Z, P, AC are not affected.
Example: RLC
RRC none Rotate accumulator Each binary bit of the accumulator is rotated right by one position. Bit D0
right is placed in the position of D7 as well as in the Carry flag. CY is modified
according to bit D0. S, Z, P, AC are not affected.
Example: RRC
RAL none Rotate accumulator Each binary bit of the accumulator is rotated left by one position through
left through carry the Carry flag. Bit D7 is placed in the Carry flag, and the Carry flag is
placed in the least significant position D0. CY is modified according to
bit D7. S, Z, P, AC are not affected.
Example: RAL
RAR none Rotate accumulator Each binary bit of the accumulator is rotated right by one position
right through carry through the Carry flag. Bit D0 is placed in the Carry flag, and the Carry
flag is placed in the most significant position D7. CY is modified
according to bit D0. S, Z, P, AC are not affected.
Example: RAR
CMA none Complement The contents of the accumulator are complemented. No flags are
accumulator affected.
Example: CMA
CMC none Complement carry The Carry flag is complemented. No other flags are affected.
Example: CMC
Example: STC
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BRANCHING INSTRUCTIONS
Example: RET
Opcod Flag none Return from The program sequence is transferred from
Description subroutine the subroutine to the calling program based
e Status
conditionally on the specified flag of the PSW as
RC Return on Carry CY = 1
described below. The two bytes from the top
Return on no of the stack are copied into the program
RNC CY = 0
Carry counter, and program execution begins at
Return on the new address.
RP S=0
positive
Example: RZ
RM Return on minus S = 1
RZ Return on zero Z=1
Return on no
RNZ Z=0
zero
Return on parity
RPE P=1
even
Return on parity
RPO P=0
odd
PCHL none Load program The contents of registers H and L are copied
counter with HL into the program counter. The contents of H
contents are placed as the high-order byte and the
contents of L as the low-order byte.
Example: PCHL
Restart
Instructi
Addre
on
ss
RST 0 0000H
RST1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H
The 8085 has four additional interrupts and
these interrupts generate RST instructions
internally and thus do not require any
external hardware. These instructions and
their Restart addresses are:
Restart
Interrup
Addres
t
s
TRAP 0024H
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH
Arithmetic Instructions
47
Opcod Operand Explanation of Description
e Instruction
ADD R Add register or The contents of the operand (register or memory) are added to the
memory, to contents of the accumulator and the result is stored in the
M accumulator accumulator. If the operand is a memory location, its location is
specified by the contents of the HL registers. All flags are modified to
reflect the result of the addition.
ADC R Add register to The contents of the operand (register or memory) and M the Carry flag
accumulator with are added to the contents of the accumulator and the result is stored
M carry in the accumulator. If the operand is a memory location, its location is
specified by the contents of the HL registers. All flags are modified to
reflect the result of the addition.
ADI 8-bit data Add immediate to The 8-bit data (operand) is added to the contents of the accumulator
accumulator and the result is stored in the accumulator. All flags are modified to
reflect the result of the addition.
ACI 8-bit data Add immediate to The 8-bit data (operand) and the Carry flag are added to the contents
accumulator with of the accumulator and the result is stored in the accumulator. All flags
carry are modified to reflect the result of the addition.
LXI Reg. pair, Load register pair The instruction loads 16-bit data in the register pair designated in the
16-bit data immediate operand.
DAD Reg. pair Add register pair to The 16-bit contents of the specified register pair are added to the
H and L registers contents of the HL register and the sum is stored in the HL register.
The contents of the source register pair are not altered. If the result is
larger than 16 bits, the CY flag is set. No other flags are affected.
Example: DAD H
SUB R Subtract register or The contents of the operand (register or memory ) are subtracted from
memory from the contents of the accumulator, and the result is stored in the
M accumulator accumulator. If the operand is a memory location, its location is
specified by the contents of the HL registers. All flags are modified to
reflect the result of the subtraction.
SUI 8-bit data Subtract immediate The 8-bit data (operand) is subtracted from the contents of the
from accumulator accumulator and the result is stored in the accumulator. All flags are
modified to reflect the result of the subtraction.
SBI 8-bit data Subtract immediate The contents of register H are exchanged with the contents of register
from accumulator D, and the contents of register L are exchanged with the contents of
with borrow register E.
Example: XCHG
INR R Increment register The contents of the designated register or memory) are incremented
or memory by 1 by 1 and the result is stored in the same place. If the operand is a
M memory location, its location is specified by the contents of the HL
registers.
INX R Increment register The contents of the designated register pair are incremented by 1 and
pair by 1 the result is stored in the same place.
Example: INX H
DCR R Decrement register The contents of the designated register or memory are M
or memory by 1 decremented by 1 and the result is stored in the same place. If the
M operand is a memory location, its location is specified by the contents
of the HL registers.
DCX R Decrement register The contents of the designated register pair are decremented by 1 and
pair by 1 the result is stored in the same place.
Example: DCX H
DAA none Decimal adjust The contents of the accumulator are changed from a binary value to
accumulator two 4-bit binary coded decimal (BCD) digits. This is the only instruction
that uses the auxiliary flag to perform the binary to BCD conversion,
and the conversion procedure is described below. S, Z, AC, P, CY flags
are altered to reflect the results of the operation.
Example: DAA
MOV Rd, Rs Copy from This instruction copies the contents of the source register into the
source(Rs) to destination register; the contents of the source register are not
M, Rs destination(Rd) altered. If one of the operands is a memory location, its location is
specified by the contents of the HL registers.
Rd, M
Example: MOV B, C or MOV B, M
MVI Rd, data Move immediate The 8-bit data is stored in the destination register or memory. If
8-bit the operand is a memory location, its location is specified by the
M, data contents of the HL registers.
LDA 16-bit Load The contents of a memory location, specified by a 16-bit address
address accumulator in the operand, are copied to the accumulator. The contents of the
source are not altered.
LDAX B/D Reg. Load The contents of the designated register pair point to a memory
pair accumulator location. This instruction copies the contents of that memory
indirect location into the accumulator. The contents of either the register
pair or the memory location are not altered.
Example: LDAX B
LXI Reg. pair, Load register pair The instruction loads 16-bit data in the register pair designated in
16-bit immediate the operand.
data
50
LHLD 16-bit Load H and L The instruction copies the contents of the memory location
address registers direct pointed out by the 16-bit address into register L and copies the
contents of the next memory location into register H. The contents
of source memory locations are not altered.
STA 16-bit 16-bit address The contents of the accumulator are copied into the memory
address location specified by the operand. This is a 3-byte instruction, the
second byte specifies the low-order address and the third byte
specifies the high-order address.
STAX Reg. pair Store The contents of the accumulator are copied into the memory
accumulator location specified by the contents of the operand (register pair).
indirect The contents of the accumulator are not altered.
Example: STAX B
SHLD 16-bit Store H and L The contents of register L are stored into the memory location
address registers direct specified by the 16-bit address in the operand and the contents of
H register are stored into the next memory location by
incrementing the operand. The contents of registers HL are not
altered. This is a 3-byte instruction, the second byte specifies the
low-order address and the third byte specifies the high-order
address.
XCHG none Exchange H and The contents of register H are exchanged with the contents of
L with D and E register D, and the contents of register L are exchanged with the
contents of register E.
Example: XCHG
SPHL none Copy H and L The instruction loads the contents of the H and L registers into
registers to the the stack pointer register, the contents of the H register provide
stack pointer the high-order address and the contents of the L register provide
the low-order address. The contents of the H
and L registers are not altered.
Example: SPHL
XTHL none Exchange H and The contents of the L register are exchanged with the stack
L with top of location pointed out by the contents of the stack pointer register.
stack The contents of the H register are exchanged with the next stack
location (SP+1); however, the contents of the stack pointer register
51
are not altered.
Example: XTHL
PUSH Reg. pair Push register pair The contents of the register pair designated in the operand are
onto stack copied onto the stack in the following sequence. The stack pointer
register is decremented and the contents of the highorder register
(B, D, H, A) are copied into that location. The stack pointer register
is decremented again and the contents of the low-order register
(C, E, L, flags) are copied to that location.
POP Reg. pair Pop off stack to The contents of the memory location pointed out by the stack
register pair pointer register are copied to the low-order register (C, E, L, status
flags) of the operand. The stack pointer is incremented by 1 and
the contents of that memory location are copied to the high-order
register (B, D, H, A) of the operand. The stack pointer register is
again incremented by 1.
OUT 8-bit Output data from The contents of the accumulator are copied into the I/O port
port accumulator to a specified by the operand.
address port with 8-bit
address Example: OUT F8H
IN 8-bit Input data to The contents of the input port designated in the operand are read
port accumulator from and loaded into the accumulator.
address a port with 8-bit
address Example: IN 8CH
Statement: Add the 16-bit number in memory locations 4000H and 4001H to the 16-bit number in memory
locations 4002H and 4003H. The most significant eight bits of the two numbers to be added are in memory locations
4001H and 4003H. Store the result in memory locations 4004H and 4005H with the most significant byte in memory
location 4005H.
1. Sample problem:
2. (4000H) = 15H
3. (4001H) = 1CH
4. (4002H) = B7H
5. (4003H) = 5AH
6. Result = 1C15 + 5AB7H = 76CCH
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7. (4004H) = CCH
8. (4005H) = 76H
9.
10. Source Program 1:
11. LHLD 4000H : "Get first I6-bit number in HL"
12. XCHG : "Save first I6-bit number in DE"
13. LHLD 4002H : "Get second I6-bit number in HL"
14. MOV A, E : "Get lower byte of the first number"
15. ADD L : "Add lower byte of the second number"
16. MOV L, A : "Store result in L register"
17. MOV A, D : "Get higher byte of the first number"
18. ADC H : "Add higher byte of the second number with CARRY"
19. MOV H, A : "Store result in H register"
20. SHLD 4004H : "Store I6-bit result in memory locations 4004H and 4005H"
21. HLT : "Terminate program execution"
1. Source program 2:
2. LHLD 4000H : Get first I6-bit number
3. XCHG : Save first I6-bit number in DE
4. LHLD 4002H : Get second I6-bit number in HL
5. DAD D : Add DE and HL
6. SHLD 4004H : Store I6-bit result in memory locations 4004H and 4005H.
7. HLT : Terminate program execution
NOTE: In program 1, eight bit addition instructions are used (ADD and ADC) and addition is performed in two steps.
First lower byte addition using ADD instruction and then higher byte addition using ADC instruction.In program 2,
16-bit addition instruction (DAD) is used.
Statement: Add the contents of memory locations 40001H and 4001H and place the result in the memory locations
4002Hand 4003H.
1. Sample problem:
2. (4000H) = 7FH
3. (400lH) = 89H
4. Result = 7FH + 89H = lO8H
5. (4002H) = 08H
6. (4003H) = 0lH
7. Source program:
8. LXI H, 4000H : "HL Points 4000H"
9. MOV A, M : "Get first operand"
10. INX H : "HL Points 4001H"
11. ADD M : "Add second operand"
12. INX H : "HL Points 4002H"
13. MOV M, A : "Store the lower byte of result at 4002H"
53
14. MVIA, 00 : "Initialize higher byte result with 00H"
15. ADC A : "Add carry in the high byte result"
16. INX H : "HL Points 4003H"
17. MOV M, A : "Store the higher byte of result at 4003H"
18. HLT : "Terminate program execution"
Statement: Subtract the 16-bit number in memory locations 4002H and 4003H from the 16-bit number in memory
locations 4000H and 4001H. The most significant eight bits of the two numbers are in memory locations 4001H and
4003H. Store the result in memory locations 4004H and 4005H with the most significant byte in memory location
4005H.
1. Sample problem:
2. (4000H) = 19H
3. (400IH) = 6AH
4. (4004H) = I5H (4003H) = 5CH
5. Result = 6A19H – 5C15H = OE04H
6. (4004H) = 04H
7. (4005H) = OEH
8. Source program:
9. LHLD 4000H : "Get first 16-bit number in HL"
10. XCHG : "Save first 16-bit number in DE"
11. LHLD 4002H : "Get second 16-bit number in HL"
12. MOV A, E : "Get lower byte of the first number"
13. SUB L : "Subtract lower byte of the second number"
14. MOV L, A : "Store the result in L register"
15. MOV A, D : "Get higher byte of the first number"
16. SBB H : "Subtract higher byte of second number with borrow"
17. MOV H, A : "Store l6-bit result in memory locations 4004H and 4005H"
18. SHLD 4004H : "Store l6-bit result in memory locations 4004H and 4005H"
19. HLT : "Terminate program execution"
Statement: Find the l’s complement of the number stored at memory location 4400H and store the complemented
number at memory location 4300H.
1. Sample problem:
2. (4400H) = 55H
3. Result = (4300B) = AAB
4. Source program:
5. LDA 4400B : "Get the number"
6. CMA : "Complement number"
7. STA 4300H : "Store the result"
8. HLT : "Terminate program execution"
Statement: Find the 2′s complement of the number stored at memory location 4200H and store the complemented
number at memory location 4300H
1. Sample problem:
2. (4200H) = 55H
3. Result = (4300H) = AAH + 1 = ABH
4. Source program:
5. LDA 4200H : "Get the number"
6. CMA : "Complement the number"
7. ADI, 01 H : "Add one in the number"
8. STA 4300H : "Store the result"
9. HLT : "Terminate program execution"
Hexadecimal Addition
Example − Addition
57
Hexadecimal Subtraction
The subtraction of hexadecimal numbers follow the same rules as the subtraction of numbers in any
other number system. The only variation is in borrowed number. In the decimal system, you borrow a
group of 1010. In the binary system, you borrow a group of 2 10. In the hexadecimal system you borrow
a group of 1610.
Example - Subtraction
EA+AE=
FIRST RHS A+E i.e A=10,E=14 SO ADDITON OF 10+14=24 AND DO 24-15=9 THE AGAIN DO ONE DECREAMENT i.e 9-1=8
CARRY=1
E A
A E
8
NOW DO THE CALCULATION OF REMAINING BITS
SO
CARRY=1
E A
+A E
9 8
SO FINAL RESULT
E A
58
+A E
19 8
-1046
14CC