51172018 Explore your design with these useful singletine doGet scripts Explore your design with these useful single-line dbGet scripts Problem What are some of the basic dbGet scripts to explore the design? Solution You can use the following single-line dbGet scripts to explore various aspects of your design: + List all unplaced instances in the design dbGet et -p nsts.p) placed) -name + List all placed instances in the design dbGet [daGet -p top. insts.pstatus + List all fixe stances in the design dGet [dbcet + List the metal layers on which the U/O pins of the block reside dboet terms.pins.allshapes.layer.name + List the non default rules (NDR) in the design dbGet head. rules.name + List the NDRs applied on a specified net dbGet [dbGet -p top-nets.name netName! name + List net names with specific max or min voltage pGet. [dbGet top.nets.maxVoltage value -p] .name abGet [dbGet top.nets.minVoltage value -p] .name + Got the placement status of an instance dbGet [dbGetinetsyName 4 eName] .pStatus ing of a specified mul it flop, during multibit Optimization dbGetInstByName ] dontSplitMultibit 1 + To avoid merging of a specified multibit flop, during multibit Optimization dbset [dbGetInstayName ] .dontMergetultibit 1 + Get the coordinates of a rectangular routing blockage + List all cell types used in the design dbGet -u top.insts.cell.name Note: The parameter fiters out the duplicate objects. hntpsslisuppor.cadence.com/apex/Acclelachmen'Porta7id=a Os0000000nUuIEAU&nageName=AticleContent&sq: )sovoDO0NEKZIAGAD_ 201851604900451172018 Explore your design with these useful singltine doGet seipts + Get the size of block placement halos + dbGer [dbGet -p2 + dbGes [apGet ~ ‘ + dbGez [dbGet -p2 top.insts.cell.subClass block") .pHaloLeft + dbGet [abGet -p2 nsts.cell.subClass ight + Get the size and top/bottom layers of block routing halos + dbGer [abGet -p2 t ts.cell.subClass block*].rHaloSidesize -cell.subClass block*]. + dbGet [dbGet -p2 top. ins oBotLayer name + dbGot [dbGet -p2 top.insts.cell-subClass block*}.rHaloTopLayer.name + Ensure all your tiehiltielo connections have tie cells (and are not connected to a rail instead) insts.instTerns.isTieii 1 verms.isTieLe 1 ‘The previous commands should return "0x0" if all connections have tie cells. "1s" are returned, use the following ‘commands to find the terms that still need a tie cell insts.instTerms.isTielii 1] name + dbGez [dbGet -p ts. inseTes + dbGer [dbGet -p top. ins s.isTieLe 1} .name + Get all instTerm names that are tied to tieLo calls, dbGet [daGet -p [deGet -p2 top.insts.cell.subClass eTieLo] .instTerns.net.allterms.isinput 1].name + Change the routing status of a net (for example, from FIXED to ROUTED) top.nets.name netNane] .wires.status route + Get the status of the design + dbGet top. statustoPlaced + dbGet top.statusPiaced + dbGot Lop. statusCiocksyathesized . tatusRouted + dbGot top. statusRCExtracted + dbGet top. statusPowernalyzed + List the layers used in a net gbGet [dbGet -p top.nete.name netiame] .wires pane Find all instances of a certain cell type dbGet [dbGet -p2 top.inets.cell.name ceiName] .name + Determine the size of a cell in the library, but not necessarily in the current design dbGet [dbGetCel1ByName celiName] .size List the nets marked in the db as clock net ebGet [dbGet -p Lop.nets.isClock 1] .name Note: Before running the previous command, build a timing graph using the t imeDesi gn command. + Set all instances with a particular pattern in the name to fixed status hips: suppor. cadence.com/apex/Artclaachmen!Portal7id=a Od0000000nUuIEAU&pageName=ArticleConlent&sq=0050V000006K2JAGA0_20185 1604999451172018 Explore your design with these useful singltine doGet seipts dbSet [dbGet -p top. insts.name *clk*]. tus fixed Get top and bottom routing layers for a route_type abGet (dbcet head. routeTypes.name routeTypeName] . topPreferredLayer. nun dGet [dbcet eTypeName] -bottomPreferrediayer .num Get database units dbGet_head.dbunits Get the manufacturing grid dbGet head.mfgGrid Get phys al only cells such as filler cell, end cap cell, and so on dpGet [dbeet top.insts.is yoOnly 1] .name Filter all PG pins with direction bidi of a specific instance dbGet [dbcet bidi] .name dbGet -p top.insts.name instWame] .pgCe!l Terms. indutDir Get class and subClass of a cell + dbGet [dbGetCelipyName cellNane] .baseClass + dbGez [dbGetceliByName cellNane] .subClass Get the instname / cellname of the driver driving a specific net + set netNane netWane cbGet -p [dbé ne} .all Terms. is¢ =p top.nets-name $m © Puts "Net: SnetNane, driving inst name: [dbGet $inst.name], driving cell name name]" [dbGet $inst.cet ist all layers for the pin of a cell dGet [dbcet selected.cell.terms.name pinName] .pins.allshapes. layer .extName Report points of the polyon that forms the die area dbshape -output -fPlan.boxes ygon [dbGet Get Verilog module ports alltreetnst BGet. [ dbGet —pl top.hIn SmoduleInstName] .hinst'Terms .hTerm.name To query top level term pin coordinates and layer number Lindex [dbGet [dbGet top-hinst-hinstTerms.term.name - p].ping.allshapes.shapes.rect] 0 dbGet [dbGet top.hinst.hinstTerms.term.name p].pins.allshapes. layer .num Query max_cap for alist of colls List [abGet -p head.alicelis.n ame BUF* Scel1Ptr.nane: srmilame] 1)") cellPtr Scel1Ptrhis ScellPtr.terms.nane uts "[dbGe Find all instances with a spe property name "myProp" (string property type) and valu + set inst ptzs [dbGet —p top.insts.props {.name == "myPzop" 6& .value == "xyz2y"] hips: suppor. cadence.com/apex/Artclalachmen!Portal7d=a 1 Od0000000nUUIEAU&pageName=ArtcleConlent&sq=0050V000006KJAGAD_20185 1604990451172018 Explore your design with these useful singletine doGet scripts ‘operty myProp and value xyzzy: [dbGet $inst_pt Instances wit! + Find non-clock ports in a design net.isClock 0].isTnput 1) .name dbGet [dbcet doGet -p2 top. term + To get information on all tech sites in the design ebGet head. site: Get head.sites.size dbIsTechsitevoponBottom [db nead.sites.name -p] + Identify and report ‘physical only’ types of cells (well tap, tie hillo, filler, endcap/decap) You can query the subclass for a cell to check whether itis welltap, tiehigh, tielow or end cap: head.1ibCells.subClass ) .name dbGet [dbcet For example, to get names of well tap cells (specified as ‘CLASS CORE WELLTAP ' in LEF), you can use the following command: aGet [dbcet Libcells.subClass corellel1?ap] .name Similatly, to get names of tie high / tie low cells (specified as ‘CLASS CORE TIEHIGH' or ‘CLASS CORE TIELOW' in LEF), use the following command: dbGet [dbGet -p head. 1ibCells.subClass coreTieHigh] -name oR peels. Get [daGet -p head. 1 ‘lass coretieLow] .name To report endcap cells (specified as ‘CLASS ENDCAP’’in LEF), use the following command: dbGet [dbcet ad. libCells.subclass coreindCap*] -name Similarly, to query filler cells with ‘CLASS CORE SPACER ’’in the LEF syntax, you can use the following command (similar to other physical-only cells): ead. 1ibcells. sul er] name ebGet [dbcet + Print all module names in the design each module nae [dbGet top.hinst.treellInsts.cel? ute "module name" This will not include the top module name. To get the top module name, run the following command: dbGet top.name + Get all leaf cells used in the design Get -u top. insts.cell.name Put "Sleaf name" + Apply set_dont_touch on selected instances Select the instances on which to apply set_dont_touen. For example, select all level-shifter instances with the "LS" prefix: dbGet nsts.name LS* Then, run the following command: ms net. term name] foreach term [dbGet selected. in: set_dont_touch [dbGet Sterm.ni hips: suppor. cadence.com/apex/Artclalachmen!Portal7d=a 1 Od0000000nUUIEAU&pageName=ArtcleConlent&sq=0050V000006KJAGAD_20185 1604990451172018 Explore your design with these useful singltine doGet seipts + Skip routes hierarchical hard macro nets proc skiproutesontineNe deselectall (hntasteattern sel Inst *$hninstPattern* doset sclected.hinst.hnets.net.skipRouting 1 deselectAll + Get the number of vias that are not power in a routed design Length et [dbGet -p top.nets.isPwrOrGnd 0] vias] + Break the DFM flow if metal fills are not added to design using run_pvs_metal_fill. Include following set of command to break the script if metal fill is not added to design puts équot;Checking if run inserted metal £111 hapes...equots if ([dbGet top.nets.name _§ RVED] .siiires.shape fillwire] ° puts squot;db has metal fill - continuing... squot; set has_fill 1 else { puts = stopping dfm run... squot; set has. 1 £ (ghas_ £411 < 1} ( break } else < rest 0: of your script + Report instance pin shape mask You can use TCL procedure below to report the mask(color) of the instance pin: ncolor {instPin layer) { [regexp Slayer [dbGet [dbGet top. insts.i Pl Term.ping.allShapes.layer.name) | Puts "SinstPin doesn't have pin shape on Slayer" else { dbeet [a sts.instTerms.name SinstPin ~ Slayer ~p2].shapes.mask pinColor Ainst/o VIAL + Report latency of all memories in the design Following script prints the latency of all memories with cell name *RAM* and clock pin name *CLK, You can change *RAM* with cell name of the desired memories, or as per your design. set mem_pin [doget [dbget top.insts.cell.name *RAM* ~p2).instTerms.name *CLiK] foreach i $mem_pin ( puts "$i [get_property [get_pins $i] actual_latency_late_rise_max]" ' + Report all flop instances with reset pin connected to the supply f dentify all flops with reset tied directly to the ves rail 4 report total count, and cach instname and cellname to an ' put file named ‘flop with tied_rst.rpt' proc findRstPinsTiedToRail{ $VSS_name $RSTport tps: suppor. cadence.com/apex/ArtclalachmentPortal7d=a1]0d0000000nUuIEAU&pageName=ArticleConlent&sq=0050V000006KJAGAD_20185 1604990451172018 Explore your design with these useful singltine doGet seipts # don't echo dbGet, etc. to screen/log: setPreference CndLogtiode 1 # output file name: set ofile "£lop with tied _ret.rpt" set ecofp [ open Sofile w ] set ont [Llength [dbGet [dbGet (dbGet top.nets.name SVSS_name - p]-instTerms.celiferm.name $RSTport ~p2 ].inst.name |) Set insts [dbGet [dbGet [dbGet top.nets.name $VSS_name ~ pl-instTerms.celiferm.name $RSIport -p2 ].inst ] set ont2 [llength Sinste] puts $ecofp "Total: Sent gent2” Hforeach inst_ptr [deGet [dbGet [dbGet top.nets.nane $VSS_name - p].instTerns.celiTerm.name §RSTport -p2 ].inst ] foreach inst_ptr Sinsts { set inst_fame [dbGet Sinst_ptr.name] set cell ptr [doInstCell Sinst ptr] set celi_name [dbGet Scell_ptr.name] set rst port (dnGet Sinst_ptr.instTerms.cellferm.nane SRSTport -p2] set net [dbGet Srst_port.nct-name] puts Secofp "Sinst_hame $celi_nane " , close Secofp , To get the status of a design: encounter> dbGet top particular stage statusClockSynthesized statusGRouted: 0 statusloPlaced: 1 statusPlaced: 1 statusPowerAnalyzed: 0 statuskcExtracted: 0 statusRouted: 1 statusScanOpted: 0 status* // reports the list of status at ° Example to check a particular value: encounter> dbGet top. statusPlaced 1 // it shows design is placed Note: The top. statusClecksynthes ized flag is only for FE-CTS [setcr'sMode -engine eX] not for cCopt. ‘Return to the top of the page hips: suppor. cadence.com/apex/Artclalachmen!Portal7d=a 1 Od0000000nUUIEAU&pageName=ArtcleConlent&sq=0050V000006KJAGAD_20185 16049904