1.

2 Micron CMOS Process Family

Process parameters

1.2µm
Units
5volts

Metal I or II pitch (width/space) 1.2 / 1.2 µm

Features Metal III pitch (width/space) 5.0 / 5.0 µm
• Double Poly / Double Metal, Poly pitch (width/space) 1.2 / 1.2 µm
• 2.4 µm Poly and Metal I Pitch,
• 5.5 Volts Maximum Operating Voltage, Contact 1.2 x 1.2 µm
• Twin-tub process on P-type or N-type wafers, Via 1 & 2 1.4 x 1.4 µm
• ProToDuctionTM Option for low cost prototypes,
• Triple Metal option available, Gate geometry 1.2 µm
.• Low leakage process N-well junction depth 4.0 µm
• Standard cell library available
P-well junction depth 4.0 µm
Description
N+ junction depth 0.20 µm
The 1.2µm process provides flexibility,
speed and packing density needed in mixed signal P+ junction depth 0.31 µm
designs. The aggressive design rules on both metal
Gate oxide thickness 225 Å
layers are comparable to most 0.8µm processes.
Also, the overall design rules are compatible with Inter poly oxide thickness 390 Å
most other 1.2um processes making second
sourcing easy.
MOSFET Electrical Parameters
1.2 MICRON - 5 volts
Technology outline Units Conditions
N Channel P Channel
min. typ. max. min. typ. max.

Vt (10x1.2µm) 0.55 0.70 0.85 0.55 0.70 0.85 V saturation

• Drain Engineered Structure to Ensure
Reliability against Hot-Carrier Injection Ids (10x1.2µm) 220 115 µA/µm Vds=Vgs=5v

• Planarization with non-etch-back Gain β (10x10µm) 73 24 µA/V2

SOG Processes
Body Factor (50x50µm) 0.56 0.73 √v
• State-of-the-art Metal technology :
Ti/TiN/Al/TiN sandwich Bvdss 10 15 10 12 V Ids=20nA

• Plasma Silicon Nitride Passivation Subthreshold Slope 90 90 mV/dec. Vds=0.1v

for Reliability against Moisture
Maximum Substrate 0.20 .01 µA/µm Vds=5.5v
• Latchup Free Process on Non-Epi Current (50x1.2µm) Vgs=2.7v
Material Achieved
Field Threshold 10 15 10 15 V Ids = 14µA

L Effective 1.0 0.82 µm L drawn = 1.5µm

An ISO-9001 Certified Company

United States Henderson NV (800) 324-0329 + Canada Bromont QC (800) 718-9701 + Europe Swindon UK 44 1793 518000
Printed in Canada
 Mitel FTI-12-01-Rev.8 20 April 1998
1.2 Micron CMOS Process Family [cont’d]

Capacitances (fF/µm2) Resistances (Ω /sq.)

min. typ. max. min. typ. max.

Inter-poly 0.88 1.06 1.27 Nwell* 570

Gate oxide 1.4 1.5 1.6 Pwell 2300

N+ Junction 0.35 N+ 35 42 55

P+ Junction 0.60 P+ 80 85 120

Poly gate 15 22 25

Poly capacitor 75 100 125

Metal I 0.038
1
Bipolar gain Metal II 0.038

typ. * For narrow Nwell resistor

R = (573 x width) / (width - 2.0)
NPN lateral [p- substrate] 80

PNP vertical 10

1
Test condition : Vce = 5 volts

FIG 1 : I-V Characteristics for a 50x1.2µm N-MOSFET FIG 2 : I-V Characteristics for a 50x1.2µm P-MOSFET
12 -7
Vgs = 5 volts
Vgs = -5 volts
-6
10

Vgs = 4 volts -5
8 Vgs = -4 volts
Ids (mA)
Ids (mA)

-4
6
Vgs = 3 volts -3
Vgs = -3 volts
4
-2
Vgs = 2 volts
2 -1 Vgs = -2 volts

0 0
0 1 2 3 4 5 6 0 -1 -2 -3 -4 -5 -6
Vds (volts) Vds (volts)

FIG 3 : Subthreshold Characteristics at Vds=0.1 volt for FIG 4 : Subthreshold Characteristics at Vds=-0.1 volt for
a 50x1.2µm N-MOSFET a 50x1.2µm P-MOSFET
10-03 360 10-03 14

10-04 320 10-04

12
10-05 10-05
280
10-06 10-06 10
240
10-07 10-07
Ids (µA)
Ids (µA)
Ids (A)

200 8
Ids (A)

10-08 10-08
160 6
10-09 10-09
120 -8
10-10 10-10 4
80 -6
10-11 10-11
-4 2
10-12 40 10-12
-2
10-13 0 10-13 0
0 0.4 0.8 1.2 1.6 2.0 0 0.4 0.8 1.2 1.6 2.0
Vgs (volts) Vgs (volts)

NOTE : These values are for guidance only. Many of them can be adjusted to suit customer requirements.
For full process specifications contact a Mitel sales office or representative.
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