CODE No.

:10BT60405

SREE VIDYANIKETHAN ENGINEERING COLLEGE

(An Autonomous Institution, Affiliated to JNTUA, Anantapur)
IV B.Tech I Semester (SVEC10) Supplementary Examinations November - 2016
VLSI DESIGN
[ Electrical and Electronics Engineering ]

Time: 3 hours Max. Marks: 70

Answer any FIVE questions
All questions carry equal marks

1. a) What is doping? Explain Ion-implantation technique with neat sketch.

b) Explain the metallization process in detail.

2. µ ∈ ins ε o W
a) Derive an expression for Gm =
D (
L Vgs − Vt )
b) In the inverter circuit what is meant by Zp.u, and Zp.d. Derive the required
ratio between Zp.u. and Zp.d. if an n-MOS inverter driven by another.

3. a) Draw a stick diagram and layout for a two-input CMOS NOR gate.
b) Discuss the limitations of scaling.

4. a) Realize the function y = A( B + C ) + DE in CMOS logic.

b) Explain the concept of sheet resistance applied to MOS transistors and inverters.
What are silicides?

5. a) Explain the operation of a carry-select adder.

b) Draw the schematic of a 4x4 array multiplier and explain its operation.

6. a) Describe Semi-Custom Design Flow.

b) Distinguish FPGA and CPLD.

7. a) Explain different types of Modeling's in VHDL.

b) Briefly describe about Design Capture and Verification Tools.

8. Write short notes on

i) Automatic test pattern generation (ATPG) method.
ii) IDDQ testing.
iii) Fault models.

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