Vol. 38, No.

4 Journal of Semiconductors April 2017

Performance analysis of SiGe double-gate N-MOSFET

A. Singh1; Ž , D. Kapoor1 , and R. Sharma2
1 Department of Electronics and Communication Engineering, Vaish College of Engineering, Rohtak 124001, India
2 Department of Electronics and Communication Engineering, Northern India Engineering College, New Delhi 110053, India

Abstract: The major purpose of this paper is to find an alternative configuration that not only minimizes the
limitations of single-gate (SG) MOSFETs but also provides the better replacement for future technology. In this
paper, the electrical characteristics of SiGe double-gate N-MOSFET are demonstrated and compared with electrical
characteristics of Si double-gate N-MOSFET. Furthermore, in this paper the electrical characteristics of Si double-
gate N-MOSFET are demonstrated and compared with electrical characteristics of Si single-gate N-MOSFET.
The simulations are carried out for the device at different operational voltages using Cogenda Visual TCAD tool.
Moreover, we have designed its structure and studied both Id –Vg characteristics for different voltages namely 0.05,
0.1, 0.5, 0.8, 1 and 1.5 V and Id –Vd characteristics for different voltages namely 0.1, 0.5, 1 and 1.5 V at work
functions 4.5, 4.6 and 4.8 eV for this structure. The performance parameters investigated in this paper are threshold
voltage, DIBL, subthreshold slope, GIDL, volume inversion and MMCR.

Key words: double gate MOSFET; DIBL; GIDL; volume inversion; SiGe; Genius tool
DOI: 10.1088/1674-4926/38/4/04xxxx PACS: 73.63.-b EEACC: 2570

1. Introduction over SG-MOSFETsŒ7 . However, on applying scaling on MOS-

As Si planar MOSFETs are reaching their scaling limits,
there is a requirement for discovering advanced device designs
so as to substitute the current planar technology. The different
alternatives to the above technology include structures like Fin-
FETs and double-gate (DG) FETs, having the capability to en-
hance gate control for reducing short channel effectsŒ1 . When
gate length of MOSFETs approaches the nanometer region, dif-
ferent short channel effects like DIBL and GIDL are devel-
oping more significantlyŒ2 . DIBL occurs when a high drain
voltage is applied to a short-channel device; it lowers the bar-
rier height, resulting in further decrease of the threshold volt-
ageŒ3 . GIDL is defined as the parasitic current, which arises
from inter-band/band-to-band tunneling (BTBT) mechanism.
This leakage mechanism mainly influences the device perfor-
mance by limiting the off state current to a minimum valueŒ4 .
However, continuous efforts for minimizing the short-
channel effects and enhancing the current drive has led to
growth of SOI (Silicon-on-Insulator) MOS transistors from
planar, traditional, single-gate devices into three-dimensional
(3D) multi-gate devices (double-, triple- or quadruple-gate de-
vices)Œ5 . Different multiple-gate (MG) like double-gate SOI
MOSFETs are necessary candidates for accompanying the
trend of scaling for the bulk MOSFETs in nanometer re-
gion, because of their high driving capability for current and
outstanding capability for reducing the short-channel effects.
Moreover, their supremacy arises from better carrier confine-
ment gates and better control of the channelŒ6 . On the basis of
analysis carried for 1–3 nm thick double-gate (DG) and single-
gate SOI MOSFETs, interface coupling is stronger for DG-
MOSFETs and sub threshold swing is nearly ideal in the case
of DG-MOSFETs. Moreover, transconductance and volume
inversion also demonstrates the superiority of DG-MOSFETs
FETs at very short channel lengths, the effect of the mobility,
band structure, density of states (DOS) and high-field trans-
port provides the path for the calculations of drive current, for
which we need further investigationŒ8 .
Double-gate SOI MOSFET utilizes two gates simultane-
ously for charge control in the thin silicon body layer per-
mitting two channels for current flow. Due to the thin nature
of SOI film, between the front and back gate, a direct charge
coupling is present that affects the device terminal character-
isticsŒ9 . Double-gate- (DG-) MOSFETs are more flexible for
scaling in comparison to conventional MOSFETs as they pro-
vide the ability to get scaled down even at the very shortest
channel length for a particular gate-oxide thicknessŒ10 . A DG-
MOSFET, that utilizes the same material and thickness for the
front and back gate electrodes, is defined as a symmetric DG-
MOSFET while a DG-MOSFET having different material and
thickness for the front and back gate electrodes, is defined
as an asymmetric DG-MOSFETŒ11 . DG-MOSFET with chan-
nel material SiGe possesses the main attribute of lattice ther-
mal conductivity, which decreases with an increase in germa-
nium content until 50%Œ12 . Above, 50% this reverses to give
the conclusion that the value is moving towards pure germa-
niumŒ12 . Using this property, construction of the device has
been doneŒ12 .
This means, precise control of channel materials is im-
portant, i.e. for Six Ge1 x , value of x D 0:2, it becomes
Si0:2 Ge0:8 , which is similar to Si D 20% and Ge D 80%Œ13
that we have used for our device in this paper.
2. Device structure and operation
Double-gate-MOSFET (DG) consists of two gates, one at
the front and the other at the back of the device as depicted in

† Corresponding author. Email: singhakshat001.as@gmail.com

Received 1 July 2016, revised manuscript received 26 October 2016 © 2017 Chinese Institute of Electronics

04xxxx-1
J. Semicond. 2017, 38(4) A. Singh et al.

Fig. 1. Schematic structure of an N-channel DG-MOSFET using SiGe.

Fig. 3. (Color online) DG N-MOSFET structure of SiGe after mesh-

ing.

Table 1. Various parameters used in N-channel DG-MOSFET using

SiGe.
Parameter Value
Oxide length (LFoxide D LBoxide/ 20 nm
Gate length (LFGate D LBGate / 20 nm
Oxide width oxide width 1 nm
(W Foxide D WBoxide /
Gate width (WFGate D WBGate / 1 nm
Spacer lengths (Ls / 10 nm
Spacer widths (Ws / 2 nm
Body concentration (Na / 3  1018 cm 3
Source concentration (Ns / 1020 cm 3
Fig. 2. (Color online) DG N-MOSFET structure of SiGe before mesh- Drain concentration (Nd/ 1020 cm 3
ing.

3. Results and Discussion

Fig. 1 to Fig. 3. The channel of the device is highly doped SiGe
with body concentration as Na . Source and drain are highly
doped with source concentration as Ns and drain concentration
as Nd and are of the same length defined as LS D LD and the
same width defined as WS D WD and both utilize Al contacts.
N-poly silicon is utilized for two gates of the same length
LFGate D LBGate and same width WFGate D WBGate . Front as
well as back oxide layers (SiO2 / are also of the same length
LFoxide D LBoxide and same width WFoxide D WBoxide . Four ni-
tride spacers partially covering source and drain regions, hav-
ing the same length defined as LS1 D LS2 D LS3 D LS4 and
same width defined as WS1 D WS2 D WS3 D WS4 , are de-
veloped for reducing the overlap capacitance between the gate
and the source/drain electrodes and protect it from the outside
environment.
The various parameters utilized above are summarized be-
low in Table 1. The device remains in the off state condition and
electrons cannot move from source to the body until a voltage
equal to or greater than the threshold voltage is supplied to de-
vice. As gate potential applied to both terminals becomes equal
to or greater than threshold voltage, potential of the surface
starts increasing, forward biasing the source-body junction, so
exponential increase in injecting electron from source to body
can be seen due to the enhancement in the energy level of elec-
tronsŒ14 .
The simulation was done using basic drift-diffusion model
along with Poisson’s equation at 300 K. The electrical char-
acteristics of the device are demonstrated and compared with
electrical characteristics of Si double-gate N-MOSFET.
Further, electrical characteristics of Si double-gate N-
MOSFET are demonstrated and compared with electrical char-
acteristics of Si single-gate N-MOSFET. The various perfor-
mance parameters namely threshold voltage, DIBL, GIDL,
subthreshold slope, volume inversion and maximum-minimum
current ratio (MMCR) are also investigated.
3.1. Contours of SiGe DG-MOSFET
Contours describing the distribution of various device
parameters such as electron density, electron mobility, hole
density and hole mobility are shown below in Fig. 4 to Fig.
7 respectively.
In order to explain the distribution of electrons across the
device, we have defined the parameter, named electron den-
sity. Its distribution is higher across source and drain while it
is varying across substrate as substrate is using acceptor type
doping while source and drain are using donor type doping as
described in Fig. 4.
In order to explain the distribution of electron mobility
across the device, we have defined the parameter, named elec-
tron mobility. Its distribution is uniform at zero potential, and
afterwards with increase in potential it is decreasing in channel

04xxxx-2
J. Semicond. 2017, 38(4)
Fig. 4. (Color online) Electron Density Distribution for SiGe DG-
MOSFET.
Fig. 5. (Color online) Electron Mobility Distribution for SiGe DG-
MOSFET.
as electric field increases as described in Fig. 5.
In order to explain the distribution of holes across the de-
vice, we have defined the parameter, named hole density. Its
distribution is higher across the substrate as the substrate is
using acceptor-type doping while source and drain are using
donor-type doping as described in Fig. 6.
In order to explain the distribution of hole mobility across
the device, we have defined the parameter, named hole mobil-
ity. Its distribution is uniform at zero potential, and afterwards
with increase in potential it is decreasing in channel as electric
field increases as described in Fig. 7.
3.2. Electrical Characteristics of SiGe DG-MOSFET
The electrical characteristics of SiGe MOSFET include
transfer I –V characteristics (Id –Vg characteristics) and output
I –V characteristics (Id –Vd characteristics).
The transfer characteristics define the drain current re-
sponse to the input gate-source driving voltage. These char-
acteristics are plotted by keeping the source at constant volt-
age mode (0 V), drain at constant voltage mode (0.05, 0.1, 0.5,
0.8,1 and 1.5 V) and gate at voltage sweep mode (start voltage
D 0 V, stop voltage D 1 V and step voltage D 0.05 V) at work
functions 4.5, 4.6 and 4.8 eV respectively.
04xxxx-3
A. Singh et al.
Fig. 6. (Color online) Hole Density Distribution for SiGe DG-
MOSFET.
Fig. 7. (Color online) Hole Mobility Distribution for SiGe DG-
MOSFET.
The Id –Vg characteristics show that one can locate the
threshold voltage (gate voltage at which the transistor passes
the current and leaves the OFF state).
Fig. 8 depicts the comparison of the Id –Vg characteristics
for DGMOS using SiGe at work function 4.8 eV (for Vd D
0.05, 0.1, 0.5, 0.8, 1 and 1.5 V).
It can be seen that as Vd decreases, threshold voltage in-
creases because at lower Vd , both leakage and drive current are
minimum while at higher Vd both are higher. From the above
graph, it is quite clear that for different values of drain voltages
used, the best Id –Vg characteristics are achieved in the case of
Vd D 0.05 V, as at these values, leakage current is minimum
while threshold voltage is maximum.
Similarly, the comparison plot of Id –Vg characteristics at
work functions 4.5, 4.6 and 4.8 eV is shown below in Fig. 9.
It can be concluded that for constant Vd , if work function
is increased, threshold voltage increases because in this situ-
ation, leakage current is minimum while if Vd increases and
work function is constant, both threshold voltage and drive cur-
rent decrease. From the above graphs, it is quite clear that in
the case of Vd D 0.05 V, the best Id –Vg characteristics are
J. Semicond. 2017, 38(4)
Fig. 8. Comparison plot of Id –Vg characteristics of SiGe DG-
MOSFET at work function equal to 4.8 eV for different values of Vd .
achieved in the case of work function at value 4.8 eV as at this
value, leakage current is minimum while threshold voltage is
maximum.
As channel length is reduced from 20 to 15 nm, 15 to 10 nm
and 10 to 7 nm, it is found that the reduction in channel length
leads to a reduction in threshold voltage drasticallyŒ15 . In order
to calculate threshold voltage, we have used ‘constant current
threshold voltage’ method, according to which threshold volt-
age is a value of voltage at which current is defined by equa-
tionŒ16 as
It D W=L  10 7 A; (1)
where It is typically between 50 and 500 nA, W is width for
drain and source region and L is length for drain and source
region. In our device, W D 10 nm, L D 20 nm. Hence, It D
0:5  10 7 A, i.e. 50 nA. Using this concept, threshold voltage
for SiGe calculated at work function equal to 4.8 eV is 0.55 V.
Similarly, for L D 15, 10, 7 nm, values calculated are 0.34 ,
0.31 and 0.25 V, respectively. DIBL is defined by equation Œ16
as
DIBL D .VtLin VtSat /=.VSat VLin /; (2)
where VtLin is threshold voltage in linear mode, VtSat is thresh-
old voltage in saturation mode, VSat is voltage in saturation
mode and VLin is voltage in linear mode. Using this concept,
DIBL for SiGe is calculated at work function equal to 4.8 eV
and its value is 66.66 mdB.
Subthreshold swing is calculated for the modelled device
using ‘subthreshold slope’ method. According to which, sub-
threshold swing is calculated using the following equationŒ17
as
SS D dVg = d.log Id /; (3)
where d Vg is change in gate voltage, d (log Id / is one decade
increase in the output current. Using this concept, subthreshold
swing for SiGe calculated at work function equal to 4.8 eV is
86.84 mV/dB.
Comparison plot of GIDL for DGMOS using Si and for
DGMOS using SiGe at work function 4.8 eV is shown below in
Fig. 10. It is plotted by keeping source at constant voltage mode
(0 V), drain at constant voltage mode (1 V), gate at voltage
sweep mode (start voltage D –0.4 V, stop voltage D 1 V and
step voltage D 0.05 V) and by assigning BTBT model to body
of DGMOS.
04xxxx-4
A. Singh et al.
Fig. 9. Comparison plot of Id –Vg characteristics of SiGe DG-
MOSFET at Vd D0.05 V for different values of work function.
Fig. 10. Comparison plot of GIDL for Si DG-MOSFET and for SiGe
DG-MOSFET at Vd D 0.1 V and work function equal to 4.8 eV.
It is seen that GIDL value is more for DGMOS using SiGe
in the range –0.4 to 0.35 V in comparison to DGMOS using
Si. GIDL value is more for DGMOS using Si in the range 0.35
to 1 V, as in this region threshold voltage is more for SiGe so
BTBT leakage is less in SiGe in comparison to Si.
Under volume inversion concept, in DG structures, the in-
version layers are present at the opposite SOI interfaces. When
two inversion layers bisect each other, two inversion channels
formed on the opposite side will possess larger charge concen-
tration at the middle region in UTB in comparison to other por-
tions of the UTB region. It is well known that short-channel
effects are reduced in ultra-thin SOI films. A direct application
of these extremely thin films is DG-MOSFET, which makes
use of the volume inversion conceptŒ18 . This concept of vol-
ume inversion is described in Fig. 11 and Fig. 12. Fig. 11 shows
that the hole mobility of SiGe device is more at the center com-
pared to hole mobility at the Si-SiO2 interfaces. Similarly, Fig.
12 shows that the electron mobility of SiGe device is more at
the center compared to electron mobility at the Si–SiO2 inter-
faces. It is obtained by measuring electron mobility and hole
mobility across the device by simulating it at Vd equal to 0 V
and work function equal to 4.8 eV.
The output characteristic defines the drain current response
to the output drain-source driving voltage. These characteris-
J. Semicond. 2017, 38(4)
Fig. 11. Hole mobility variation for SiGe DG-MOSFET at Vd D 0 V
and work function equal to 4.8 eV.
Fig. 12. Electron mobility variation for SiGe DG-MOSFET at Vd D
0 V and work function equal to 4.8 eV.
tics are plotted by keeping source at constant voltage mode
(0 V), gate at constant voltage mode (0.5, 1 and 1.5 V) and
drain at voltage sweep mode (start voltage D 0 V, stop voltage
D 1 V and step voltage D 0.05 V) at work functions 4.5, 4.6
and 4.8 eV, respectively. The Id –Vd characteristics show the
two conduction states of the device, i.e. the saturated state and
the non-saturated state.
Fig. 13 depicts the comparison of Id –Vd characteristics for
DGMOS using SiGe at work function 4.5 eV for Vg D0.1 V,
Vg D 0.5 V, Vg D 1 V and Vg D 1.5 V.
It is seen that as Vg increases, inversion charge increases,
that increases Id . From the above graphs, it is quite clear that
for each of the values of work function (4.5, 4.6 and 4.8 eV),
the best Id –Vd characteristics are achieved in the case of Vd D
1.5 V, as at these values, leakage current is minimum.
Similarly, the comparison plot of Id –Vd characteristics for
DGMOS using SiGe at work functions 4.5, 4.6 and 4.8 eV is
shown below in Fig. 14.
It is seen that for constant Vg , as work function is de-
creased, drain current increases while leakage current de-
creases as more conduction of electrons will be there from
source to drain, if Vg increases and work function is constant,
drain current increases. From the above graphs, it is quite clear
that in the case of Vg D 1.5 V, the best Id –Vd characteristics
04xxxx-5
A. Singh et al.
Fig. 13. Comparison plot of Id –Vd characteristics of SiGe DG-
MOSFET at work function equal to 4.5 eV for different values of Vg .
Fig. 14. Comparison plot of Id –Vd characteristics of SiGe DG-
MOSFET at Vg D 1.5 V for different values of work function.
are achieved in the case of work function at value 4.5 eV as at
this value, leakage current is minimum.
Maximum-Minimum Current Ratio (MMCR) is calculated
using the following equation as
MMCR D IMAX =IMIN ; (4)
where IMAX is maximum value of current in Id –Vd character-
istics, IMIN is minimum value of current in Id –Vd character-
istics. Using this concept, maximum–minimum current ratio
(MMCR) for SiGe calculated at work function equal to 4.5 eV
is 2.7  1010 .
Comparison between various parameters used in N-
channel DG-MOSFET using SiGe and N-channel DG-
MOSFET using Si and comparison between various para-
meters used in N-channel SG-MOSFET using Si and N-
channel DG-MOSFET using Si is given below in Tables 2 and
3, respectively.
On analyzing Id –Vg characteristics of Si DG-MOSFET
and SiGe DG-MOSFET, it is concluded that better threshold
voltage is obtained for SiGe in comparison with Si and is
shown below in Fig. 15.
Fig. 16 defines the Id –Vd characteristics of Si DG-
MOSFET and SiGe DG-MOSFET. The drain current value is
higher for SiGe in comparison to Si as Si possesses the larger
J. Semicond. 2017, 38(4) A. Singh et al.

Table 2. Comparison between various parameters used in N-channel DG-MOSFET using SiGe and N-channel DG-MOSFET using Si.
Parameter SiGe DG-MOSFET Si DG-MOSFET
Channel length (nm) 20 20
Design Doping concentration (cm 3 / 3  1018 1018
Gate oxide thickness (nm) 1 1
0.55 0.35
0.34 0.16
Threshold voltage (V) (L D20, 15, 10 and 7nm) 0.31 0.14
Short channel effects 0.25 0.12
DIBL (mdB) 66.66 80
SS (mV/dB) 86.84 82.23
MMCR 2.7  1010 1.3  108

Table 3. Comparison between various parameters used in N-channel SG-MOSFET using Si and N-channel DG-MOSFET using Si.
Parameter Si DG-MOSFET Si SG-MOSFET
Channel length (nm) 20 20
Design Doping concentration (cm 3 / 1018 1018
Gate oxide thickness (nm) 1 1
0.35 0.2
0.16 0.12
Threshold oltage (V) (L D20nm, 15nm, 10nm and 7nm) 0.14 0.1
Short Channel Effects 0.12 0.07
DIBL (mdB) 80 100
SS (mV/dB) 82.23 87.86
MMCR 1.3  108 7  105

Fig. 15. Comparison plot of Id –Vg characteristics of Si DG-MOSFET Fig. 16. Comparison plot of Id –Vd characteristics of DG-MOSFET
and SiGe DG-MOSFET at Vd D 0.05 V and work function equal to using Si and DG-MOSFET using SiGe at Vg D 1.5 V and work func-
4.8 eV. tion equal to 4.5 eV.

value of resistance because the substrate is available near the
channel.
On analyzing Id –Vg characteristics of Si SG-MOSFET and
Si DG-MOSFET, it is concluded that better threshold voltage is
obtained for DG- MOSFET in comparison with SG-MOSFET
and is shown below in Fig. 17.
Fig. 18 shows Id –Vd characteristics of Si DG-MOSFET
and Si SG-MOSFET. The drain current value is higher for Si
DG-MOSFET in comparison to Si SG-MOSFET as Si SG-
MOSFET possesses the larger value of resistance because the
substrate is available near the channel.
4. Conclusion
The simulation results show that the electrical characteris-
tics of double-gate MOSFET using SiGe are better in compari-
son with double-gate MOSFET using Si and electrical charac-
teristics of Si double-gate MOSFET are better in comparison
with Si single-gate MOSFET. The device exhibits various de-
sirable features such as improved ON current, higher thresh-
old voltage, lower DIBL, lower GIDL in region of threshold
voltage and higher MMCR, whereas subthreshold swing of
SiGe double-gate MOSFET is more than that of Si double-gate
MOSFET. Moreover, there is no problem of device burnout
in double-gate MOSFET using SiGe as it has larger value of
threshold voltage. It is a low-power device and has better vol-
ume inversion.

04xxxx-6
J. Semicond. 2017, 38(4)
Fig. 17. Comparison plot of Id –Vg characteristics of double-gate
MOSFET using Si and single-gate MOSFET using Si at Vd D 0.05V
and work function equal to 4.8 eV.
Fig. 18. Comparison plot of Id –Vd characteristics of Si double-gate
MOSFET and Si single-gate MOSFET at Vg D 1.5 V and work func-
tion equal to 4.5 eV.
References
[1] Mehrotra S R. Simulation study of silicon nanowire field effect
transistors (FETs). Master of Science Dissertation, University of
Delhi, 2007
[2] Valinajad H, Hosseini R, Akbari M E. Electrical characteristics
of strained double gate MOSFET. International J Res Rev Appl
04xxxx-7
A. Singh et al.
Sci, 2012, 13(2): 436
[3] Roy K, Mukhopadhyay S, Meimand H M. Leakage current
mechanisms and reduction in techniques in deep-sub microme-
ter CMOS circuits. Proc IEEE, 2003, 91(2): 305
[4] Rafhay Q, Xu C, Batude P, et al. Revisited approach for the char-
acterization of gate induced drain leakage. Solid-State Electron,
2012, 71(1): 37
[5] Colinge J P. Multi-gate SOI MOSFETs. Microelectron Eng,
2007, 84(9): 2071
[6] Mohammadi H, Abdullah H, Fu Dee C. A review on modeling
the channel potential in multi-gate MOSFETs. Sains Malaysiana
Publications, 2014, 43(6):861
[7] Ernst T, Cristoloveanu S, Ghibaudo G, et al. Ultimately thin
double-gate SOI MOSFETs. IEEE Trans Electron Devices, 2003,
50(3): 830
[8] Krishnamohan T, Jungemann C, Kim D, et al. High performance,
uniaxially-strained Si and Ge, double-gate P-MOSFETs. Micro-
electron Eng, 2007, 84(9): 2063
[9] Mani P, Pandey M K. Silicon on insulator MOSFET development
from single-gate to multiple-gate. Int J Adv Res Comput Scie
Softw Eng, 2012, 2(6): 297
[10] Dubey S, Tiwari P K, Jit S. On-current modeling of short-channel
double-gate (DG) MOSFETs with a vertical Gaussian-like dop-
ing profile. J Semicond, 2013, 34(5): 1
[11] Subramaniam S, Wale R N A, Joshi S M. Drain current models for
single-gate MOSFETs and undoped symmetric and asymmetric
double-gate SOI MOSFETs and quantum mechanical effects: a
review. Int J Eng Sci Technol, 2013, 5(1): 96
[12] Wagner M.Simulation of thermoelectric devices. Doctorate of
Philosophy Dissertation, Vienna Univ ersity of Technology, 2007
[13] Kim D. Theoretical performance evaluations of N MOS double
gate FETs with high mobility material: strained III-V, Ge and Si.
Doctorate of Philosophy Dissertation Stanford University, 2009
[14] Sahu D, Tirkey A. Design and simulation of double gate FETs us-
ing ATLAS. Bachelors of Technology Project, National Institute
of Technology, Rourkela, 2014
[15] Singh A, Kapoor D, and Sharma R. Review of SiGe double gate
N-MOSFET. Int J Inform Technol Syst, 2015, 4(1): 19
[16] Loke A, Wu Z Y, Moallemi R, et al. Constant-current threshold
voltage extraction in HSPICE for nanoscale CMOS analog de-
sign. Synopsys Users Group (SNUG): Advanced Micro Devices
Inc., Third Edition, 2010
[17] Boucart K, Ionescu A M. Double-gate tunnel FE T with high-gate
dielectric. IEEE Trans Electron Devices, 2007, 54(7): 17
[18] Sharma R. Analytical modeling of volume inversion and channel
length modulation in fully depleted double gate nanoscale SOI
MOSFETs. J Electron Devices, 2013, 18(2): 1553