Scribd Logo
Upload

Welcome to Scribd!

  • Compal La-7092p r0.3 Schematics

    Uploaded by

    Luciano Lucas
    27 views47 pages
    ESQUEMA ELÉTRICO

    Original Title

    compal_la-7092p_r0.3_schematics

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    ESQUEMA ELÉTRICO

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    27 views47 pages

    Compal La-7092p r0.3 Schematics

    Uploaded by

    Luciano Lucas
    ESQUEMA ELÉTRICO

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 47

    A B C D E

    1 1

    Compal Confidential
    2 2

    JE50/HM50/SJV50_BZ
    P5WE6/P5WH6/P5WS6 Schematics Document
    AMD Brazos
    Brazos with Zacate / Hudson M1 / Seymour XT
    DIS only / UMA only / PX Muxless / PX Muxless with BACO
    3 3

    2010-10-28 ZZZ

    LA-7092P REV: 0.3 PCB


    Part Number = DA60000L000

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Cover Page
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 1 of 46
    A B C D E
    A B C D E

    Compal Confidential
    Model Name : P5WE6/P5WH6/P5WS6
    JE50/HM50/SJV50_BZ VRAM 512M/1G
    64M16/128M16 x 4
    1
    PCB PN : DA60000L000

    DDR3
    page 23
    Brazos 1

    ATI Vancuver Seymour Memory BUS(DDR3) 204pin DDRIII-SO-DIMM X2


    Single Channel BANK 0, 1, 2, 3 page 8,9
    uFCBGA-962 PCI-Express x 4
    Thermal Sensor AMD Brazos APU 1.5V DDRIII 800~1066MHz
    Page 18,19,20,21,22 Gen2
    ADM1032
    page 19 FT1
    DP0 BGA 413-Ball
    19mm x 19mm
    LVDS
    page 10
    DP1 page 5,6,7
    2 2
    CRT USB port 0,1,2 USB port 5 USB port 7 USB port6 USB port 8
    page 12
    UMI Gen.1 x4 USB CMOS Bluetooth Card Mini
    PCI-Express Reader card
    HDMI 2.5GT/s per lane Conn x 3 Camera Conn
    RT5137 (WL)X1
    Conn.
    page 11
    page 33 page 10 page 33 page 29 page 29

    FCH
    3.3V 48MHz USB
    Hudson-M1
    3.3V 24.576MHz/48Mhz HD Audio
    BGA 605-Ball
    23mm x 23mm
    S-ATA Gen2
    page 13,14,15,16,17
    MINI Card LAN(GbE)
    LED Atheros HDA Codec
    3
    page 32 WLAN AR8151 CX20584 3

    page 29 page 26 page 27


    GPP3 GPP2 LPC BUS SATA HDD SATA ODD
    RTC CKT. Conn. page 30 Sub/B page 30
    RJ45 MIC Jack x 1
    page 13 port 0 port 1
    page 26
    HP Jack x 1
    Int MIC x 1
    Power On/Off CKT. ENE KB930
    page 34
    Int SPK x 1
    page 31 page 28

    Power sequence
    VGA DC/DC Touch Pad Int.KBD
    page 24,25 page 32 page 32

    DC/DC Interface CKT. Fan Control EC I/O Buffer BIOS


    4
    page 34 4
    page 32 page 32
    page 35

    Extend Card/B
    Power Circuit 1. USB X2 Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title
    page 36,37,38,39,40,41 Block Diagrams
    42,43,44,45 2. ODD X1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    B 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 2 of 46
    A B C D E
    A B C D E

    Voltage Rails BOARD ID Table


    SIGNAL
    Power Plane Description S1 S3 S5 STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
    Board ID PCB Revision
    VIN Adapter power supply (19V) N/A N/A N/A Full ON HIGH HIGH HIGH HIGH ON ON ON ON 0
    B+ AC or battery power rail for power circuit. N/A N/A N/A 1
    S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
    +VSB VSB always on power rail ON ON ON* 2
    +3VALW 3.3V always on power rail ON ON ON* S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF 3
    1 1
    +5VALW 5V always on power rail ON ON ON*
    S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
    4
    +1.1VALW 1.1V always on power rail ON ON ON* 5
    +APU_CORE Core voltage for CPU (0.7-1.2V) ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF 6
    +APU_CORE_NB 1.0V switched power rail ON OFF OFF 7
    +1.5V 1.5V power rail for CPU VDDIO and DDRIII ON ON OFF Board ID / SKU ID Table for AD channel
    +0.75VS 0.75VS switched power rail for DDR terminator ON OFF OFF Vcc 3.3V +/- 5%
    +1.05VS 1.05V switched power rail for APU VDD10 ON OFF OFF Ra/Rc/Re 100K +/- 5% Project ID Table
    +1.1VS 1.1VS switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
    Board ID PCB Revision
    +1.8VS 1.8V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
    0
    +3VS 3.3V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
    1
    +5VS 5V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
    2
    +VGA_CORE Core voltage for GPU ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
    3
    +3VSG 3.3V switched power rail for GPU ON OFF OFF 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
    4
    +1.8VSG 1.8V switched power rail for GPU ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
    5
    +1.5VSG 1.5V switched power rail for GPU ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
    6
    +1.0VSG 1.0V switched power rail for GPU ON OFF OFF 7 NC 2.500 V 3.300 V 3.300 V
    2
    +3V_LAN 3.3V power rail for LAN ON ON ON
    7 2

    +RTCVCC RTC power ON ON ON


    Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

    BOARD ID Table
    BTO Option Table
    Board ID PCB Revision
    EC SM Bus1 address EC SM Bus2 address 0 EVT / DVT BTO Item BOM Structure
    1 Display from APU UMA@
    Device Address HEX Device Address HEX 2 Display from VGA DISO@
    ADM1032 (GPU) 1001-101xb 9AH 3 Use VGA VGA@
    4 Muxless w/BACO BACO@
    5 Muxless wo/BACO WOBACO@
    SM Bus Controller 0 (FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#)
    6 Muxless PX@
    7 w/Vancouver Serise VAN@
    Device Address HEX w/Manhttan Serise MAN@
    APU SIC/SID (FCH_SMB3)
    Bluetooth BT@
    3
    H_THERMTRIP# (FCH_ALERT#)
    Project ID Table AR8151 8151@ 3

    Seymour Seymour@
    Board ID PCB Revision
    wo/Muxless WOPX@
    SM Bus Controller 1 (FCH_SMB0)
    0
    wo/VGA WOVGA@
    1
    APU 1.5G 15G@
    Device Address HEX 2
    APU 1.6G 16G@
    DDR DIMM1 (FCH_SMB0) 1001-000xb
    3
    90
    DDR DIMM2 (FCH_SMB0) 1001-001xb
    4
    92
    WLAN (FCH_SMB0)
    5
    6
    7
    *UMA only : UMA@ BT@ 8151@ WOVGA@ WOPX@

    VGA Chip SEL: APU Chip SEL:


    1. Seymour@ + Van@ 1. 16G@
    2. Robson@ + Man@ 2. 15G@
    *DIS only : VGA@ DISO@ WOBACO@ BT@ 8151@ WOPX@
    4 *Muxless w/BACO : UMA@ VGA@ PX@ BACO@ BT@ 8151@ 4

    Muxless wo/BACO : UMA@ VGA@ PX@ WOBACO@ BT@ 8151@

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Notes List
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 3 of 46
    A B C D E
    5 4 3 2 1

    Without BACO option :


    Power-Up/Down Sequence PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation
    1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON
    sequence, though a shorter ramp-up duration is preferred.
    BACO option :
    2. VDDR3 should ramp-up before or simultaneously with VDDC. PE_GPIO0 : High ->Normal operation (dGPU is not reseton BACO mode)
    PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)
    3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
    D DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10. dGPU Power Pins Voltage PX 3.0 BACO Mode Max current
    D

    4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, 1.8V OFF ON 1679mA
    VDD_CT have ramped up. DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
    DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
    5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
    DPLL_PVDD, MPV18, and SPV18
    ramp-up (or vice versa).)
    DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and 1.0V OFF ON 575mA
    SPV10
    PCIE_VDDC 1.0V OFF ON 2A
    VDDR3(3.3VSG) Note: Do not drive any IOs before VDDR3 is ramped up.
    VDDR3 , and A2VDD 3.3V OFF ON 190mA
    BIF_VDDC (current consumption = 55mA@1.0V, in Same as OFF ON 70mA
    PCIE_VDDC(1.0V) BACO mode) VDDC Same as
    PCIE_VDDC
    VDDR1 1.5V OFF OFF 2.8A
    C
    VDDR1(1.5VSG) VDDC/VDDCI 1.12V OFF OFF 12.9A C

    VDDC/VDDCI(1.12V)

    VDD_CT(1.8V)
    PE_GPIO0 PE_EN BACO Switch
    iGPU dGPU
    PERSTb BIF_VDDC

    PE_GPIO1

    REFCLK PX_mode

    B +3.3VALW MOS
    +3.3VSG B

    Straps Reset 1
    +1.5V SI4800
    +1.5VSG
    Straps Valid +1.0V +1.0VSG
    Regulator
    2 3

    Global ASIC Reset


    +B Regulator
    +VGA_CORE
    +1.8V +1.8VSG
    T4+16clock
    SI4800
    5 4
    PWRGOOD

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    dGPU Block Diagram
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 4 of 46
    5 4 3 2 1
    5 4 3 2 1

    +1.8VS U22B

    R398 1 2 150_0402_1%

    DISPLAYPORT 1
    <11> APU_HDMI_TX2P A8 TDP1_TXP0 DP_ZVSS H3

    DP MISC
    <11> APU_HDMI_TX2N B8 TDP1_TXN0
    G2 APU_ENBKL <10>
    R399 1K_0402_5% APU_SVC DP_BLON
    1 2 <11> APU_HDMI_TX1P B9 H2 APU_ENVDD <10>
    R400 1K_0402_5% APU_SVD TDP1_TXP1 DP_DIGON
    1 2 <11> APU_HDMI_TX1N A9
    TDP1_TXN1 DP_VARY_BL
    H1 APU_BLPWM <10>
    D R142 300_0402_5% APU_RST# D
    2 1
    R401 2 1 300_0402_5% APU_PWRGD D10
    TEST_25_L <11> APU_HDMI_TX0P TDP1_TXP2 APU_HDMI_CLK
    R402 1 2 510_0402_1% C10 B2
    <11> APU_HDMI_TX0N TDP1_TXN2 TDP1_AUXP APU_HDMI_CLK <11>
    R141 1 2 1K_0402_5% TEST36 C2 APU_HDMI_DATA
    TDP1_AUXN APU_HDMI_DATA <11>
    <11> APU_HDMI_CLKP A10
    TDP1_TXP3
    <11> APU_HDMI_CLKN B10 C1 APU_HDMI_HPD <11>
    TDP1_TXN3 TDP1_HPD
    C237 0.01U_0402_25V7K B5 A3 APU_LCD_CLK
    <10> APU_TXOUT2+ LTDP0_TXP0 LTDP0_AUXP APU_LCD_CLK <10>
    1 @ 2 APU_RST# APU_LCD_DATA

    DISPLAYPORT 0
    <10> APU_TXOUT2- A5 B3 APU_LCD_DATA <10>
    C238 0.01U_0402_25V7K LTDP0_TXN0 LTDP0_AUXN
    1 @ 2 APU_PWRGD D6 D3 R406 1 2 100K_0402_5%
    <10> APU_TXOUT1+ LTDP0_TXP1 LTDP0_HPD
    <10> APU_TXOUT1- C6 LTDP0_TXN1
    DAC_RED C12 APU_CRT_R <12>
    A6 D13 R407 1 2 150_0402_1%
    <10> APU_TXOUT0+ LTDP0_TXP2 DAC_REDB
    <10> APU_TXOUT0- B6 LTDP0_TXN2 DAC_GREEN A12 APU_CRT_G <12>
    +3VS B12 R408 1 2 150_0402_1%
    DAC_GREENB
    D8 A13

    VGA DAC
    APU_PROCHOT# <10> APU_TXCLK+ LTDP0_TXP3 DAC_BLUE APU_CRT_B <12>
    R410 1 2 1K_0402_5% C8 B13 R409 1 2 150_0402_1%
    <10> APU_TXCLK- LTDP0_TXN3 DAC_BLUEB
    R109 1 UMA@ 2 4.7K_0402_5% APU_CRT_DDC_SCL V2 E1
    <13> APU_CLKP CLKIN_H DAC_HSYNC APU_CRT_HSYNC <12>
    <13> APU_CLKN V1 CLKIN_L DAC_VSYNC E2 APU_CRT_VSYNC <12>
    R155 1 UMA@ 2 4.7K_0402_5% APU_CRT_DDC_SDA

    CLK
    <13> APU_DISP_CLKP D2 DISP_CLKIN_H DAC_SCL F2 APU_CRT_DDC_SCL <12>
    R411 1 2 1K_0402_5% APU_ALERT#_R For DVT 1011 D1 D4
    <13> APU_DISP_CLKN DISP_CLKIN_L DAC_SDA APU_CRT_DDC_SDA <12>
    R143 1 2 1K_0402_5% APU_SIC J1 D12 R144 1 2 499_0402_1%
    <44> APU_SVC SVC DAC_ZVSS
    <44> APU_SVD J2 SVD

    SER
    R414 1 2 1K_0402_5% APU_SID R1 PAD T66
    APU_SIC TEST4
    P3 SIC TEST5 R2 PAD T67
    APU_SID P4 R6
    SID TEST6
    TEST14 T5 PAD T68
    T3 E4 TEST15 R415 1 @ 2 1K_0402_5%
    C <13> APU_RST# RESET_L TEST15 C
    <13> APU_PWRGD T4 K4

    CTRL
    PWROK TEST16
    TEST17 L1
    R169 1 2 0_0402_5% APU_PROCHOT# U1 L2 TEST18 R416 1 2 1K_0402_5%
    <31> EC_THERM# APU_THERMTRIP# U2 PROCHOT_L TEST18 TEST19
    R168 1 @ 2 0_0402_5% M2 R417 1 2 1K_0402_5%

    TEST
    <13> FCH_PROCHOT# APU_ALERT#_R THERMTRIP_L TEST19 TEST25_H
    T2 K1 R418 1 2 510_0402_1%
    ALERT_L TEST25_H TEST_25_L
    TEST25_L K2
    APU_TDI N2 L5
    APU_TDO TDI TEST28_H
    N1 M5
    APU_TCK TDO TEST28_L TEST31
    P1 M21 PAD T73
    TCK TEST31

    JTAG
    APU_TMS P2 J18 TEST33_H C5161 2 0.1U_0402_16V4Z R420 1 2 51_0402_1%
    APU_TRST# TMS TEST33_H TEST33_L C5171
    T93PAD M4 J19 2 0.1U_0402_16V4Z R421 1 2 51_0402_1%
    APU_DBRDY TRST_L TEST33_L Delete Test point for layout limitation
    T94PAD M3 U15
    Close to APU APU_DBREQ# DBRDY TEST34_H 20100917
    M1 T15
    DBREQ_L TEST34_L TEST35 R422 1 @
    H4 2 1K_0402_5%
    TEST35 TEST36
    <44> APU_VDDNB_RUN_FB_H F4 N5
    VDDCR_NB_SENSE TEST36 TEST37 R958 1
    <44> APU_VDD0_RUN_FB_H G1 R5 PAD T76 2 1K_0402_5% +1.8VS
    VDDCR_CPU_SENSE TEST37
    T77PAD F3
    VDDIO_MEM_S_SENSE

    <44> APU_VDD0_RUN_FB_L F1
    VSS_SENSE
    K3
    TEST38
    B4 T1 ALLOW_STOP# <13>
    RSVD_1 DMAACTIVE_L
    W11
    RSVD_2 R423 1
    V5 2 1K_0402_5% +1.8VS
    RSVD_3
    +3VS ONTARIO-2M161000-1.6G_BGA413
    15G@

    APU : SA00004DO60 (S IC ZACATE 2M151132B1240 1.5G BGA)


    1

    R424 APU : SA000046G80 (S IC ZACATE 2M161232B2240 1.6G BGA )


    10K_0402_5%
    2

    B R425 U22 16G@ B


    2

    1K_0402_5%
    2
    B

    AMD Debug
    1

    Q79
    E

    APU_THERMTRIP# 3 1 H_THERMTRIP# <14>


    C

    Zacate FT1 B0
    MMBT3904_NL_SOT23-3 +1.8VS +1.8VS

    1 2 JHDT1
    R427 @ 0_0402_5% 1 2 APU_TCK R843 2 1 1K_0402_5%
    1 2

    1K_0402_5%
    If FCH internal pull-up disabled, level-shifter could be deleted. 3 4 APU_TMS R840 2 1 1K_0402_5%
    2 3 4
    Need BIOS to disable internal pull-up!!
    R842

    5 6 APU_TDI R798 2 1 1K_0402_5%


    5 6
    7 8 APU_TDO
    0_0402_5% 7 8
    CPU TSI interface level shift
    1

    APU_TRST# R846 1 2 APU_TRST#_R 9 10 APU_PWRGD


    9 10 +1.8VS
    @ BSH111, the Vgs is: FDV301N, the Vgs is: R847 2 1 10K_0402_5% 11 12 APU_RST#
    C236 1 11 12
    2 0.1U_0402_10V7K min = 0.4V min = 0.65V
    R176 2 1 10K_0402_5% 13 14 APU_DBRDY
    @ @ Typ = 1.0V Typ = 0.85V 13 14

    +3VS 1 R428 2 1 R160 2 Max = 1.3V Max = 1.5V R177 2 1 10K_0402_5% 15 16 APU_DBREQ# R178 1 2 300_0402_5%
    15 16
    31.6K_0402_1% 30K_0402_1% 17 18 J108_PLLTST0 R799 1 2 0_0402_5% TEST19
    17 18
    1.607V for Gate If use level shift, EC_SMB need pull up
    (pop R747 & R748) 19 20 J108_PLLTST1 R863 1 2 0_0402_5% TEST18
    19 20
    2
    G

    Please be noted about TEST_18 and TEST_19


    APU_SID 3 1 EC_SMB_DA 1 @ 2 FCH_SID T0 FCH
    A FCH_SID <14> A
    @ R429 0_0402_5% SAMTE_ASP-136446-07-B
    S

    Q22 1 2 EC_SMB_DA2 TO EC CONN@


    EC_SMB_DA2 <19,31>
    BSH111 1N_SOT23-3 R430 0_0402_5%

    1 2
    R431 0_0402_5%
    2
    G

    APU_SIC 3 1
    @
    EC_SMB_CK 1
    R432
    @ 2
    0_0402_5%
    FCH_SIC
    FCH_SIC <14> T0 FCH
    Security Classification Compal Secret Data Compal Electronics, Inc.
    S

    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title


    Q23 EC_SMB_CK2
    1 2 EC_SMB_CK2 <19,31> TO EC FT1 CTRL/DP/CRT
    BSH111 1N_SOT23-3 R433 0_0402_5%
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    1 2 Custom 0.3
    R434 0_0402_5%
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 5 of 46
    5 4 3 2 1
    A B C D E

    U22E
    DDR_A_MA0 R17 B14 DDR_A_D0
    DDR_A_MA1 M_ADD0 M_DATA0 DDR_A_D1
    H19 A15
    DDR_A_MA2 M_ADD1 M_DATA1 DDR_A_D2
    J17 A17
    DDR_A_MA3 M_ADD2 M_DATA2 DDR_A_D3 DDR_A_D[0..63]
    H18 D18 DDR_A_D[0..63] <8,9>
    DDR_A_MA4 M_ADD3 M_DATA3 DDR_A_D4
    H17 A14
    DDR_A_MA5 M_ADD4 M_DATA4 DDR_A_D5 DDR_A_MA[0..15]
    G17 C14 DDR_A_MA[0..15] <8,9>
    DDR_A_MA6 M_ADD5 M_DATA5 DDR_A_D6
    H15 C16
    DDR_A_MA7 M_ADD6 M_DATA6 DDR_A_D7 DDR_A_DM[0..7]
    G18 D16 DDR_A_DM[0..7] <8,9>
    4 DDR_A_MA8 M_ADD7 M_DATA7 4
    F19
    DDR_A_MA9 M_ADD8 DDR_A_D8
    E19 C18
    DDR_A_MA10 M_ADD9 M_DATA8 DDR_A_D9
    T19 A19
    DDR_A_MA11 M_ADD10 M_DATA9 DDR_A_D10
    F17 B21
    DDR_A_MA12 M_ADD11 M_DATA10 DDR_A_D11
    E18 D20
    DDR_A_MA13 M_ADD12 M_DATA11 DDR_A_D12
    W17 A18
    DDR_A_MA14 M_ADD13 M_DATA12 DDR_A_D13
    E16 B18
    DDR_A_MA15 M_ADD14 M_DATA13 DDR_A_D14
    G15 A21
    M_ADD15 M_DATA14

    DDR SYSTEM MEMORY


    C20 DDR_A_D15
    M_DATA15
    <8,9> DDR_A_BS0 R18
    M_BANK0 DDR_A_D16
    <8,9> DDR_A_BS1 T18 C23
    M_BANK1 M_DATA16 DDR_A_D17
    <8,9> DDR_A_BS2 F16 D23
    M_BANK2 M_DATA17 DDR_A_D18
    F23
    DDR_A_DM0 M_DATA18 DDR_A_D19
    D15 F22
    DDR_A_DM1 M_DM0 M_DATA19 DDR_A_D20
    B19 C22
    DDR_A_DM2 M_DM1 M_DATA20 DDR_A_D21
    D21 D22
    DDR_A_DM3 M_DM2 M_DATA21 DDR_A_D22
    H22 F20
    DDR_A_DM4 M_DM3 M_DATA22 DDR_A_D23
    P23 F21
    DDR_A_DM5 M_DM4 M_DATA23
    V23
    DDR_A_DM6 M_DM5 DDR_A_D24
    AB20 H21
    DDR_A_DM7 M_DM6 M_DATA24 DDR_A_D25
    AA16 H23
    M_DM7 M_DATA25 DDR_A_D26 U22A
    K22
    DDR_A_DQS0 M_DATA26 DDR_A_D27 PCIE_GTX_C_FRX_P0
    <8,9> DDR_A_DQS0 A16 K21 <18> PCIE_GTX_C_FRX_P0 AA6 AB6 PCIE_FTX_GRX_P0 C518 1VGA@2 0.1U_0402_16V7K
    PCIE_FTX_C_GRX_P0 <18>
    DDR_A_DQS#0 M_DQS_H0 M_DATA27 DDR_A_D28 PCIE_GTX_C_FRX_N0 P_GPP_RXP0 P_GPP_TXP0 C519 1VGA@2 0.1U_0402_16V7K
    <8,9> DDR_A_DQS#0 B16 G23 <18> PCIE_GTX_C_FRX_N0 Y6 AC6 PCIE_FTX_GRX_N0 PCIE_FTX_C_GRX_N0 <18>
    DDR_A_DQS1 M_DQS_L0 M_DATA28 DDR_A_D29 P_GPP_RXN0 P_GPP_TXN0
    <8,9> DDR_A_DQS1 B20 H20
    DDR_A_DQS#1 M_DQS_H1 M_DATA29 DDR_A_D30 PCIE_GTX_C_FRX_P1
    <8,9> DDR_A_DQS#1 A20 K20 <18> PCIE_GTX_C_FRX_P1 AB4 AB3 PCIE_FTX_GRX_P1 C520 1VGA@2 0.1U_0402_16V7K
    PCIE_FTX_C_GRX_P1 <18>

    PCIE I/F
    DDR_A_DQS2 M_DQS_L1 M_DATA30 DDR_A_D31 PCIE_GTX_C_FRX_N1 P_GPP_RXP1 P_GPP_TXP1 C521 1VGA@2 0.1U_0402_16V7K
    <8,9> DDR_A_DQS2 E23 K23 <18> PCIE_GTX_C_FRX_N1 AC4 AC3 PCIE_FTX_GRX_N1 PCIE_FTX_C_GRX_N1 <18>
    DDR_A_DQS#2 M_DQS_H2 M_DATA31 P_GPP_RXN1 P_GPP_TXN1
    <8,9> DDR_A_DQS#2 E22
    DDR_A_DQS3 M_DQS_L2 DDR_A_D32 PCIE_GTX_C_FRX_P2 PCIE_FTX_GRX_P2 C522 1VGA@2 0.1U_0402_16V7K
    <8,9> DDR_A_DQS3 J22 N23 <18> PCIE_GTX_C_FRX_P2 AA1 Y1 PCIE_FTX_C_GRX_P2 <18>
    DDR_A_DQS#3 M_DQS_H3 M_DATA32 DDR_A_D33 PCIE_GTX_C_FRX_N2 P_GPP_RXP2 P_GPP_TXP2 PCIE_FTX_GRX_N2 C523 1VGA@2 0.1U_0402_16V7K
    <8,9> DDR_A_DQS#3 J23 P21 <18> PCIE_GTX_C_FRX_N2 AA2 Y2 PCIE_FTX_C_GRX_N2 <18>
    DDR_A_DQS4 M_DQS_L3 M_DATA33 DDR_A_D34 P_GPP_RXN2 P_GPP_TXN2
    <8,9> DDR_A_DQS4 R22 T20
    DDR_A_DQS#4 M_DQS_H4 M_DATA34 DDR_A_D35 PCIE_GTX_C_FRX_P3 PCIE_FTX_GRX_P3 C524 1VGA@2 0.1U_0402_16V7K
    <8,9> DDR_A_DQS#4 P22 T23 <18> PCIE_GTX_C_FRX_P3 Y4 V3 PCIE_FTX_C_GRX_P3 <18>
    3 DDR_A_DQS5 M_DQS_L4 M_DATA35 DDR_A_D36 PCIE_GTX_C_FRX_N3 P_GPP_RXP3 P_GPP_TXP3 PCIE_FTX_GRX_N3 C525 1VGA@2 0.1U_0402_16V7K 3
    <8,9> DDR_A_DQS5 W22 M20 <18> PCIE_GTX_C_FRX_N3 Y3 V4 PCIE_FTX_C_GRX_N3 <18>
    DDR_A_DQS#5 M_DQS_H5 M_DATA36 DDR_A_D37 P_GPP_RXN3 P_GPP_TXN3
    <8,9> DDR_A_DQS#5 V22 P20
    DDR_A_DQS6 M_DQS_L5 M_DATA37 DDR_A_D38 P_ZVDD_10 R436 1 1.27K_0402_1%
    <8,9> DDR_A_DQS6 AC20 R23 +1.05VS 1 2 Y14 AA14 P_ZVSS 2
    DDR_A_DQS#6 M_DQS_H6 M_DATA38 DDR_A_D39 R435 2K_0402_1% P_ZVDD_10 P_ZVSS
    <8,9> DDR_A_DQS#6 AC21 T22
    M_DQS_L6 M_DATA39
    <8,9> DDR_A_DQS7
    DDR_A_DQS7 AB16
    M_DQS_H7
    Less than 1"
    DDR_A_DQS#7 AC16 V20 DDR_A_D40 Less than 1"
    <8,9> DDR_A_DQS#7 M_DQS_L7 M_DATA40
    V21 DDR_A_D41 <13> UMI_RX0P AA12 AB12 UMI_TX0P_C C526 1 2 0.1U_0402_16V7K
    M_DATA41 P_UMI_RXP0 P_UMI_TXP0 UMI_TX0P <13>
    DDR_A_CLK0 M17 Y23 DDR_A_D42 <13> UMI_RX0N Y12 AC12 UMI_TX0N_C C527 1 2 0.1U_0402_16V7K
    <8> DDR_A_CLK0 M_CLK_H0 M_DATA42 P_UMI_RXN0 P_UMI_TXN0 UMI_TX0N <13>
    DDR_A_CLK#0 M16 Y22 DDR_A_D43
    <8> DDR_A_CLK#0 M_CLK_L0 M_DATA43
    DDR_A_CLK1 M19 T21 DDR_A_D44 <13> UMI_RX1P AA10 AC11 UMI_TX1P_C C528 1 2 0.1U_0402_16V7K
    <8> DDR_A_CLK1 M_CLK_H1 M_DATA44 P_UMI_RXP1 P_UMI_TXP1 UMI_TX1P <13>
    DDR_A_CLK#1 M18 U23 DDR_A_D45 Y10 AB11 UMI_TX1N_C C529 1 2 0.1U_0402_16V7K

    UMI I/F
    <8> DDR_A_CLK#1 M_CLK_L1 M_DATA45 <13> UMI_RX1N P_UMI_RXN1 P_UMI_TXN1 UMI_TX1N <13>
    DDR_B_CLK2 N18 W23 DDR_A_D46
    <9> DDR_B_CLK2 M_CLK_H2 M_DATA46
    DDR_B_CLK#2 N19 Y21 DDR_A_D47 <13> UMI_RX2P AB10 AA8 UMI_TX2P_C C530 1 2 0.1U_0402_16V7K
    <9> DDR_B_CLK#2 M_CLK_L2 M_DATA47 P_UMI_RXP2 P_UMI_TXP2 UMI_TX2P <13>
    DDR_B_CLK3 L18 <13> UMI_RX2N AC10 Y8 UMI_TX2N_C C531 1 2 0.1U_0402_16V7K
    <9> DDR_B_CLK3 M_CLK_H3 P_UMI_RXN2 P_UMI_TXN2 UMI_TX2N <13>
    DDR_B_CLK#3 L17 Y20 DDR_A_D48
    <9> DDR_B_CLK#3 M_CLK_L3 M_DATA48
    AB22 DDR_A_D49 <13> UMI_RX3P AC7 AB8 UMI_TX3P_C C532 1 2 0.1U_0402_16V7K
    M_DATA49 P_UMI_RXP3 P_UMI_TXP3 UMI_TX3P <13>
    DDR_RST# L23 AC19 DDR_A_D50 <13> UMI_RX3N AB7 AC8 UMI_TX3N_C C533 1 2 0.1U_0402_16V7K
    <8,9> DDR_RST# M_RESET_L M_DATA50 P_UMI_RXN3 P_UMI_TXN3 UMI_TX3N <13>
    DDR_EVENT# N17 AA18 DDR_A_D51
    <8,9> DDR_EVENT# M_EVENT_L M_DATA51
    AA23 DDR_A_D52 ONTARIO-2M161000-1.6G_BGA413
    M_DATA52 DDR_A_D53 15G@
    AA20
    DDR_CKE0 M_DATA53 DDR_A_D54
    <8,9> DDR_CKE0 F15 AB19
    DDR_CKE1 M_CKE0 M_DATA54 DDR_A_D55
    <8,9> DDR_CKE1 E15 Y18
    M_CKE1 M_DATA55
    AC17 DDR_A_D56
    M_DATA56 DDR_A_D57
    Y16
    DDR_A_ODT0 M_DATA57 DDR_A_D58
    <8> DDR_A_ODT0 W19 AB14
    DDR_A_ODT1 M0_ODT0 M_DATA58 DDR_A_D59
    <8> DDR_A_ODT1 V15 AC14
    DDR_B_ODT0 M0_ODT1 M_DATA59 DDR_A_D60
    <9> DDR_B_ODT0 U19 AC18
    DDR_B_ODT1 M1_ODT0 M_DATA60 DDR_A_D61
    <9> DDR_B_ODT1 W15 AB18
    M1_ODT1 M_DATA61 DDR_A_D62
    AB15
    DDR_CS0_DIMMA# M_DATA62 DDR_A_D63
    <8> DDR_CS0_DIMMA# T17 AC15
    DDR_CS1_DIMMA# M0_CS_L0 M_DATA63
    <8> DDR_CS1_DIMMA# W16
    2 DDR_CS0_DIMMB# M0_CS_L1 2
    <9> DDR_CS0_DIMMB# U17
    DDR_CS1_DIMMB# M1_CS_L0 +MEM_VREF
    <9> DDR_CS1_DIMMB# V16
    M1_CS_L1 M_VREF
    M23 15 mils
    DDR_A_RAS# U18
    <8,9> DDR_A_RAS# M_RAS_L
    DDR_A_CAS# V19
    <8,9> DDR_A_CAS# M_CAS_L
    DDR_A_WE# V17 M22 R437 2 1 +1.5V
    <8,9> DDR_A_WE# M_WE_L M_ZVDDIO_MEM_S
    ONTARIO-2M161000-1.6G_BGA413 39.2_0402_1%
    15G@

    +1.5V
    2

    +1.5V R438
    1K_0402_1%

    R149 1 2 DDR_EVENT#
    1

    1K_0402_5% +MEM_VREF
    2

    1 1
    R439 C534 C535
    1 1K_0402_1% 1
    1000P_0402_50V7K 0.1U_0402_16V4Z
    2 2
    1

    Place within 1000 mils to APU


    20100526 Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    FT1 DDRIII/UMI/PCIE
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 6 of 46
    A B C D E
    5 4 3 2 1

    +APU_CORE

    +1.8VS

    11A U22C 2A L29


    +APU_CORE +VDD_18 2 1 U22D

    TSense/PLL/DP/PCIE/IO
    E5 U8 FBMA-L11-201209-221LMA30T_0805 A7 N13

    10U_0603_6.3V6M
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    180P_0402_50V8J

    0.1U_0402_16V7K
    VDDCR_CPU_1 VDD_18_1 VSS_1 VSS_50
    1 1 1 1 1 1 1 E6 W8 1 1 1 1 1 1 1 B7 N20
    C539 C536 C541 C542 C543 C544 C540 VDDCR_CPU_2 VDD_18_2 VSS_2 VSS_51

    C545

    C537

    C546

    C538

    C547

    C548

    C549
    F5 U6 B11 N22
    D VDDCR_CPU_3 VDD_18_3 Change from SM010014520 to SD002000080 VSS_3 VSS_52 D
    F7 U9 B17 P10
    10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M VDDCR_CPU_4 VDD_18_4 20100816 VSS_4 VSS_53
    G6 W6 B22 P14
    2 2 2 2 2 2 2 VDDCR_CPU_5 VDD_18_5 2 2 2 2 2 2 2 VSS_5 VSS_54
    G8 T7 C4 R4
    10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M VDDCR_CPU_6 VDD_18_6 VSS_6 VSS_55
    H5 V7 D5 R7
    VDDCR_CPU_7 VDD_18_7 VSS_7 VSS_56

    CPU CORE
    H7 D7 R20
    VDDCR_CPU_8 VSS_8 VSS_57
    J6 D9 T6
    VDDCR_CPU_9 VSS_9 VSS_58
    J8 D11 T9
    VDDCR_CPU_10 VSS_10 VSS_59
    L7 D14 T11
    VDDCR_CPU_11 VSS_11 VSS_60
    M6 B15 T13
    VDDCR_CPU_12 VSS_12 VSS_61
    1 1 1 1 1 1 M8 D17 U4
    C550 C551 C552 C553 C554 C555 VDDCR_CPU_13 VSS_13 VSS_62
    N7 D19 U5
    VDDCR_CPU_14 +1.8VS VSS_14 VSS_63
    R8 E7 U7
    VDDCR_CPU_15 VSS_15 VSS_64

    GND
    1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 180P_0402_50V8J 180P_0402_50V8J 0.15A E9 U12
    2 2 2 2 2 2 +APU_CORE_NB L30 VSS_16 VSS_65
    10A add Cap. for CRT DVT E12
    VSS_17 VSS_66
    U20

    DAC
    1U_0402_6.3V6K E8 W9 +VDD_18_DAC 2 1 E20 U22
    VDDCR_NB_1 VDD_18_DAC VSS_18 VSS_67
    E11 F8 V8

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    180P_0402_50V8J
    VDDCR_NB_2 FBMA-L11-201209-221LMA30T_0805 VSS_19 VSS_68
    E13 1 1 1 1 1 F11 V9

    1U_0402_6.3V6K
    VDDCR_NB_3 @ VSS_20 VSS_69

    C556

    C557

    C558

    C604

    C684
    F9 F13 V11
    VDDCR_NB_4 Change from SM010014520 to SD002000080 VSS_21 VSS_70
    F12 G4 V13
    VDDCR_NB_5 VSS_22 VSS_71

    GPU AND NB CORE


    20100816
    G11
    G13
    VDDCR_NB_6
    VDDCR_NB_7
    POWER 2 2 2 2 2
    G5
    G7
    VSS_23
    VSS_24
    VSS_72
    VSS_73
    W1
    W2
    H9 +1.05VS G9 W4
    VDDCR_NB_8 VSS_25 VSS_74
    1 1 1 1 1 H12 G12 W5
    C559 C560 C561 C562 C563 VDDCR_NB_9 VSS_26 VSS_75
    K11
    VDDCR_NB_10 0.2A L31
    G20
    VSS_27 VSS_76
    W7
    K13 G22 W12
    VDDCR_NB_11 VSS_28 VSS_77

    DIS PLL
    0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K L10 U11 +VDDL_10 2 1 H6 W20
    2 2 2 2 2 VDDCR_NB_12 VDDPL_10 VSS_29 VSS_78
    L12 H11 Y5

    1U_0402_6.3V6K
    180P_0402_50V8J

    10U_0603_6.3V6M
    0.1U_0402_16V7K
    0.1U_0402_16V7K VDDCR_NB_13 FBMA-L11-201209-221LMA30T_0805 VSS_30 VSS_79
    L14 1 1 1 1 H13 Y7
    VDDCR_NB_14 VSS_31 VSS_80

    C564

    C565

    C566

    C567
    M11 J4 Y9
    VDDCR_NB_15 VSS_32 VSS_81
    M12 J5 Y11
    VDDCR_NB_16 VSS_33 VSS_82
    M13 J7 Y13
    VDDCR_NB_17 2 2 2 2 VSS_34 VSS_83
    N10 J20 Y15
    VDDCR_NB_18 VSS_35 VSS_84
    N12 K10 Y17
    +APU_CORE_NB VDDCR_NB_19 L32 VSS_36 VSS_85
    N14
    VDDCR_NB_20 5.5A K14
    VSS_37 VSS_86
    Y19

    PCIE/IO/DDR3 Phy
    P11 +VDD_10 2 1 L4 AA4
    VDDCR_NB_21 VSS_38 VSS_87
    P13 U13 L6 AA22

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    1U_0402_6.3V6K

    1U_0402_6.3V6K
    180P_0402_50V8J

    0.1U_0402_16V7K

    0.1U_0402_16V7K
    VDDCR_NB_22 VDD_10_1 FBMA-L11-201209-221LMA30T_0805 VSS_39 VSS_88
    W13 1 1 1 1 1 1 1 L8 AB2
    +1.5V VDD_10_2 VSS_40 VSS_89

    C568

    C569

    C570

    C571

    C572

    C573

    C574
    C 2A VDD_10_3
    V12
    Change from SM010014520 to SD002000080
    L11
    VSS_41 VSS_90
    AB5 C
    G16 T12 L13 AB9
    VDDIO_MEM_S_1 VDD_10_4 20100816 VSS_42 VSS_91
    G19 L20 AB13
    VDDIO_MEM_S_2 2 2 2 2 2 2 2 VSS_43 VSS_92
    1 1 1 1 1 E17 L22 AB17
    C575 C576 C577 C578 C579 VDDIO_MEM_S_3 VSS_44 VSS_93
    J16 M7 AB21
    VDDIO_MEM_S_4 VSS_45 VSS_94

    DDR3
    L16 N4 AC5
    10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M VDDIO_MEM_S_5 VSS_46 VSS_95
    L19 N6 AC9
    2 2 2 2 2 VDDIO_MEM_S_6 VSS_47 VSS_96
    N16 N8 AC13
    VDDIO_MEM_S_7 VSS_48 VSS_97
    R16 N11 A11

    DP Phy/IO
    VDDIO_MEM_S_8 VSS_49 VSSBG_DAC
    R19
    VDDIO_MEM_S_9 0.5A +3VS
    W18
    VDDIO_MEM_S_10 ONTARIO-2M161000-1.6G_BGA413
    U16 A4
    VDDIO_MEM_S_11 VDD_33 15G@

    1U_0402_6.3V6K
    0.1U_0402_16V7K
    1 1
    ONTARIO-2M161000-1.6G_BGA413

    C580

    C581
    15G@
    Power Cap. Summary
    C582
    1
    C583
    1
    C584
    1
    C585
    1
    C586
    1
    C587
    1
    C588
    1 2 2 APU
    S POLY C 330U 2.5V M D2E TPE LESR9M H1.8 --->+APU_CORE(Qty : 3) Unpop:2
    1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 180P_0402_50V8J 180P_0402_50V8J +APU_CORE
    2 2 2 2 2 2 2
    +1.5V
    S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+APU_CORE(Qty : 2)

    S POLY C 330U 2.5V Y D2 LESR9M EEFS H1.9 --->+APU_CORE_NB(Qty : 1)


    +APU_CORE_NB
    S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU--->+APU_CORE_NB(Qty : 1)
    1 1
    C589 C590
    S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+1.5V(Qty : 1) +1.5V
    1 1 1 1 10U_0603_6.3V6M 10U_0603_6.3V6M
    C591 C592 C593 C594 2 2
    S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->1.05VS(Qty : 1) +1.05VS
    0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K
    2 2 2 2
    S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+1.8VS(Qty : 1) +1.8VS
    1 1 1 1
    C595 C596 C597 C598
    B DDR3 Socket B

    1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K S POLY C 330U 2V M X LESR6M SX H1.9 --->1.5V(Qty : 1) +1.5V
    POWER +1.05VS
    2 2 2 2

    FCH
    S POLY C 330U 2.5V Y D2 LESR9M EEFS H1.9 --->1.1VS(Qty : 1) UMA unpop +1.1VS
    1
    C620
    1
    C621 + C599
    1
    C600
    1
    C601
    1
    C602
    1
    C603
    1 GPU
    @ @ S POLY C 330U 2V M X LESR6M SX H1.9 --->VGA_CORE(Qty : 2) Unpop:1
    10U_0603_6.3V6M 390U_2.5V_10M 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 180P_0402_50V8J 180P_0402_50V8J +GPU_CORE
    2 2 2 2 2 2 2
    S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+VGA_CORE(Qty : 1)

    S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+1.5VSG(Qty : 1) +1.5VSG


    180PF Qt'y follow the distance between
    +1.5V CPU socket and DIMM0. <2.5inch> USB
    +APU_CORE POWER S_A-P_CAP 220U 6.3V M C45 R17M SVPE H4.4 --->+USB_VCCA(Qty : 1) +USB_VCCA
    2 2 1 1
    C101 C102 C103 C104
    0.1U_0402_16V7K 0.1U_0402_16V7K 180P_0402_50V8J 180P_0402_50V8J
    10U_0603_6.3V6M
    1 1
    330U_D2E_2.5VM_R9M
    1 1
    390U_2.5V_10M
    1 1 1 2 2 By case (Along split)
    1
    C605 + C606 + C607 + C1104+ C1105+ C616
    @ @ @ +1.5V
    330U_D2E_2.5VM_R9M 330U_D2E_2.5VM_R9M 390U_2.5V_10M
    2 2 2 2 2 2

    +1.5V POWER +1.8VS POWER


    Near CPU Socket

    180P_0402_50V8J

    180P_0402_50V8J

    180P_0402_50V8J

    180P_0402_50V8J
    0.1U_0402_16V7K

    0.1U_0402_16V7K

    0.1U_0402_16V7K

    0.1U_0402_16V7K
    +APU_CORE_NB
    change 0603 for DVT 1 1 1 1 1 1 1 1

    C608

    C609

    C610

    C611

    C612

    C613

    C614

    C615
    A 1 A
    1 1 1 1 2 2 2 2 2 2 2 2
    C623 C685 C624 + C625
    1 1 C622 + @
    1 10U_0603_6.3V6M 390U_2.5V_10M 10U_0603_6.3V6M
    C617 + C618 + C619 390U_2.5V_10M 2 2 2 2
    2 10U_0603_6.3V6M
    390U_2.5V_10M 330U_D2_2.5VY_R9M 10U_0603_6.3V6M
    2 2 2

    Near CPU Socket Near CPU Socket Near CPU Socket


    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    P07-FT1 PWR/VSS
    Size Document Number Rev
    (390uF_2.5V_6.3x5.7_ESR10m)*1=(SF000002O00) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    C 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Monday, November 01, 2010 Sheet 7 of 46
    5 4 3 2 1
    5 4 3 2 1

    +1.5V +1.5V

    JDIMM1
    +VREF_DQ 1 VREF_DQ VSS1 2
    3 4 DDR_A_D4 +1.5V +1.5V
    DDR_A_D0 VSS2 DQ4 DDR_A_D5 DDR_A_D[0..63]
    5 DQ0 DQ5 6
    DDR_A_D1 DDR_A_D[0..63] <6,9>
    1 1 7 DQ1 VSS3 8

    2
    C626 C627 9 10 DDR_A_MA[0..15]
    VSS4 DQS#0 DDR_A_DQS#0 <6,9> DDR_A_MA[0..15] <6,9>
    DDR_A_DM0 11 12 R145 R146
    DM0 DQS0 DDR_A_DQS0 <6,9> DDR_A_DM[0..7]
    0.1U_0402_16V4Z 1000P_0402_50V7K 13 14 DDR_A_DM[0..7] <6,9> 1K_0402_1% 1K_0402_1%
    2 2 DDR_A_D2 VSS5 VSS6 DDR_A_D6
    DDR_A_D3
    15 DQ2 DQ6 16
    DDR_A_D7
    15mil 15mil
    17 18

    1
    DQ3 DQ7
    19 20 +VREF_DQ +VREF_CA
    D DDR_A_D8 VSS7 VSS8 DDR_A_D12 D
    21 22
    DDR_A_D9 DQ8 DQ12 DDR_A_D13
    23 24
    DQ9 DQ13

    2
    25 26
    VSS9 VSS10 DDR_A_DM1 R147 R148
    <6,9> DDR_A_DQS#1 27 28
    DQS#1 DM1 1K_0402_1% 1K_0402_1%
    <6,9> DDR_A_DQS1 29 30 DDR_RST# <6,9>
    DQS1 RESET#
    31 32
    DDR_A_D10 VSS11 VSS12 DDR_A_D14
    33 34

    1
    DDR_A_D11 DQ10 DQ14 DDR_A_D15
    35 36
    DQ11 DQ15
    37 38
    DDR_A_D16 VSS13 VSS14 DDR_A_D20
    39 40
    DDR_A_D17 DQ16 DQ20 DDR_A_D21
    41 42
    DQ17 DQ21
    43 44
    VSS15 VSS16 DDR_A_DM2
    <6,9> DDR_A_DQS#2 45 DQS#2 DM2 46
    <6,9> DDR_A_DQS2 47 DQS2 VSS17 48
    49 50 DDR_A_D22
    DDR_A_D18 VSS18 DQ22 DDR_A_D23
    51 DQ18 DQ23 52
    DDR_A_D19 53 54
    DQ19 VSS19 DDR_A_D28
    55 VSS20 DQ28 56
    DDR_A_D24 57 58 DDR_A_D29
    DDR_A_D25 DQ24 DQ29
    59 DQ25 VSS21 60
    61 VSS22 DQS#3 62 DDR_A_DQS#3 <6,9>
    DDR_A_DM3 63 64
    DM3 DQS3 DDR_A_DQS3 <6,9>
    65 VSS23 VSS24 66
    DDR_A_D26 67 68 DDR_A_D30
    DDR_A_D27 DQ26 DQ30 DDR_A_D31
    69 DQ27 DQ31 70
    71 VSS25 VSS26 72

    +1.5V
    <6,9> DDR_CKE0 73 CKE0 CKE1 74 DDR_CKE1 <6,9>
    C 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C
    75 VDD1 VDD2 76
    77 78 DDR_A_MA15 2 2 2 2 2 2 2 2 2 2 2 2
    NC1 A15 DDR_A_MA14
    <6,9> DDR_A_BS2 79 BA2 A14 80
    81 82 C628 C629 C630 C631 C632 C633 C634 C635 C636 C637 C638 C110
    DDR_A_MA12 VDD3 VDD4 DDR_A_MA11
    83 A12/BC# A11 84
    DDR_A_MA9 DDR_A_MA7 1 1 1 1 1 1 1 1 1 1 1 1
    85 A9 A7 86
    87 88 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    DDR_A_MA8 VDD5 VDD6 DDR_A_MA6
    89 A8 A6 90
    DDR_A_MA5 91 92 DDR_A_MA4
    A5 A4
    93 VDD7 VDD8 94
    DDR_A_MA3 95 96 DDR_A_MA2
    DDR_A_MA1 A3 A2 DDR_A_MA0
    97 98
    A1 A0
    99 100
    VDD9 VDD10
    101 102 DDR_A_CLK1 <6>
    <6> DDR_A_CLK0 CK0 CK1
    103 104 DDR_A_CLK#1 <6>
    <6> DDR_A_CLK#0 CK0# CK1#
    105 106
    DDR_A_MA10 VDD11 VDD12
    107 108 DDR_A_BS1 <6,9>
    A10/AP BA1
    <6,9> DDR_A_BS0 109 110 DDR_A_RAS# <6,9>
    BA0 RAS#
    111 112
    VDD13 VDD14
    <6,9> DDR_A_WE#
    113
    115
    WE# S0#
    114
    116
    DDR_CS0_DIMMA# <6> CRB 0.1u X1 4.7u X1 CRB 100U X2
    <6,9> DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 <6>
    117 118
    DDR_A_MA13 VDD15 VDD16
    119 120 DDR_A_ODT1 <6>
    A13 ODT1 +0.75VS
    121 122
    <6> DDR_CS1_DIMMA# S1# NC2
    123 124
    VDD17 VDD18 +1.5V
    125 126 +VREF_CA
    NCTEST VREF_CA
    127 128
    DDR_A_D32 VSS27 VSS28 DDR_A_D36
    129 130 2 2 1 1
    DDR_A_D33 DQ32 DQ36 DDR_A_D37 C640 C641 C642
    131 132 1 1
    DQ33 DQ37 C645 C644 @ + C1102
    133 134
    B VSS29 VSS30 DDR_A_DM4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0603_6.3V6K 330U_D2E_2.5VM_R9M B
    <6,9> DDR_A_DQS#4 135 136
    DQS#4 DM4 1000P_0402_50V7K 0.1U_0402_16V4Z 1 1 2
    <6,9> DDR_A_DQS4 137 138
    DQS4 VSS31 DDR_A_D38 2 2 2
    139 140
    DDR_A_D34 VSS32 DQ38 DDR_A_D39
    141 142
    DDR_A_D35 DQ34 DQ39
    143 144
    DQ35 VSS33 DDR_A_D44
    145 146
    DDR_A_D40 VSS34 DQ44 DDR_A_D45
    147 148
    DDR_A_D41 DQ40 DQ45
    149 150
    DQ41 VSS35
    151 152 DDR_A_DQS#5 <6,9>
    DDR_A_DM5 VSS36 DQS#5
    153
    DM5 DQS5
    154 DDR_A_DQS5 <6,9> Place near JDIMM1 330U ESR:9m H:2
    155 156
    DDR_A_D42 157
    VSS37 VSS38
    158 DDR_A_D46 P/N:SGA20331E10
    DDR_A_D43 DQ42 DQ46 DDR_A_D47
    159 160
    DQ43 DQ47
    161 162
    DDR_A_D48 VSS39 VSS40 DDR_A_D52
    163 164
    DDR_A_D49 DQ48 DQ52 DDR_A_D53
    165 166
    DQ49 DQ53
    167 168
    VSS41 VSS42 DDR_A_DM6
    <6,9> DDR_A_DQS#6 169 170
    DQS#6 DM6
    <6,9> DDR_A_DQS6 171 172
    DQS6 VSS43 DDR_A_D54
    173
    VSS44 DQ54
    174 EMI For DVT 10/20
    DDR_A_D50 175 176 DDR_A_D55
    DDR_A_D51 DQ50 DQ55
    177 178
    DQ51 VSS45 DDR_A_D60
    179 180
    DDR_A_D56 VSS46 DQ60 DDR_A_D61 +1.5V
    181 182
    DDR_A_D57 DQ56 DQ61 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    183 184
    DQ57 VSS47 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    185 186 DDR_A_DQS#7 <6,9>
    DDR_A_DM7 VSS48 DQS#7
    187 188 DDR_A_DQS7 <6,9> 2 2 2 2
    DM7 DQS7
    189 190
    DDR_A_D58 VSS49 VSS50 DDR_A_D62 C643 C675 C676 C678
    191 192
    DDR_A_D59 DQ58 DQ62 DDR_A_D63
    193 194
    A DQ59 DQ63 1 1 1 1 A
    195 196
    VSS51 VSS52
    1 2 197 198 DDR_EVENT# <6,9>
    R150 10K_0402_5% SA0 EVENT#
    +3VS 199 200 FCH_SMDAT0 <9,14,29>
    VDDSPD SDA
    201 202 FCH_SMCLK0 <9,14,29>
    SA1 SCL
    1 1 203 204 +0.75VS
    VTT1 VTT2
    1

    C646 C647
    R151 205 206
    2.2U_0603_6.3V4Z
    2
    0.1U_0402_16V4Z
    2 10K_0402_5%
    G1 G2
    FOX_AS0A626-U8SN-7F
    DDR3 SO-DIMM A H:8mm
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Standard Type Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title
    CONN@
    DDR3 SODIMM-I Socket
    2

    P/N:SP07000HA00 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    F/P:FOX_AS0A626-U8SN-7F_204P AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 8 of 46
    5 4 3 2 1
    5 4 3 2 1

    +1.5V +1.5V

    JDIMM2
    +VREF_DQ 1 VREF_DQ VSS1 2
    3 4 DDR_A_D4
    DDR_A_D0 VSS2 DQ4 DDR_A_D5
    5 DQ0 DQ5 6
    1 1 DDR_A_D1 7 8
    C680 C681 DQ1 VSS3
    9 VSS4 DQS#0 10 DDR_A_DQS#0 <6,8>
    DDR_A_DM0 11 12 DDR_A_D[0..63]
    DM0 DQS0 DDR_A_DQS0 <6,8> DDR_A_D[0..63] <6,8>
    0.1U_0402_16V4Z 1000P_0402_50V7K 13 14
    2 2 DDR_A_D2 VSS5 VSS6 DDR_A_D6 DDR_A_MA[0..15]
    15 16 DDR_A_MA[0..15] <6,8>
    D DDR_A_D3 DQ2 DQ6 DDR_A_D7 D
    17 18
    DQ3 DQ7 DDR_A_DM[0..7]
    19 20 DDR_A_DM[0..7] <6,8>
    DDR_A_D8 VSS7 VSS8 DDR_A_D12
    21 22
    DDR_A_D9 DQ8 DQ12 DDR_A_D13
    23 24
    DQ9 DQ13
    25 26
    VSS9 VSS10 DDR_A_DM1
    <6,8> DDR_A_DQS#1 27 28
    DQS#1 DM1
    <6,8> DDR_A_DQS1 29 30 DDR_RST# <6,8>
    DQS1 RESET#
    31 32
    DDR_A_D10 VSS11 VSS12 DDR_A_D14
    33 34
    DDR_A_D11 DQ10 DQ14 DDR_A_D15
    35 36
    DQ11 DQ15
    37 38
    DDR_A_D16 VSS13 VSS14 DDR_A_D20
    39 DQ16 DQ20 40
    DDR_A_D17 41 42 DDR_A_D21
    DQ17 DQ21
    43 VSS15 VSS16 44
    45 46 DDR_A_DM2
    <6,8> DDR_A_DQS#2 DQS#2 DM2
    <6,8> DDR_A_DQS2 47 DQS2 VSS17 48
    49 50 DDR_A_D22
    DDR_A_D18 VSS18 DQ22 DDR_A_D23
    51 DQ18 DQ23 52
    DDR_A_D19 53 54
    DQ19 VSS19 DDR_A_D28
    55 VSS20 DQ28 56
    DDR_A_D24 57 58 DDR_A_D29
    DDR_A_D25 DQ24 DQ29
    59 DQ25 VSS21 60
    61 VSS22 DQS#3 62 DDR_A_DQS#3 <6,8>
    DDR_A_DM3 63 64
    DM3 DQS3 DDR_A_DQS3 <6,8> +1.5V
    65 VSS23 VSS24 66
    DDR_A_D26 67 68 DDR_A_D30
    DDR_A_D27 DQ26 DQ30 DDR_A_D31 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    69 DQ27 DQ31 70
    71 VSS25 VSS26 72 2 2 2 2 2 2 2 2 2 2 2 2
    C44 C45 C652 C653 C654 C655 C682 C46 C683 C47 C48 C49
    0.1U_0402_16V4Z
    73 74 1 1 1 1 1 1 1 1 1 1 1 1
    C <6,8> DDR_CKE0 CKE0 CKE1 DDR_CKE1 <6,8> C
    75 76 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    VDD1 VDD2 DDR_A_MA15
    77 NC1 A15 78
    79 80 DDR_A_MA14
    <6,8> DDR_A_BS2 BA2 A14
    81 VDD3 VDD4 82
    DDR_A_MA12 83 84 DDR_A_MA11
    DDR_A_MA9 A12/BC# A11 DDR_A_MA7
    85 A9 A7 86
    87 VDD5 VDD6 88
    DDR_A_MA8 89 90 DDR_A_MA6
    DDR_A_MA5 A8 A6 DDR_A_MA4
    91
    93
    A5 A4
    92
    94
    CRB 0.1u X1 4,7uX1
    DDR_A_MA3 VDD7 VDD8 DDR_A_MA2
    95 96
    DDR_A_MA1 A3 A2 DDR_A_MA0
    97 98
    A1 A0 +0.75VS
    99 100
    VDD9 VDD10
    101 102 DDR_B_CLK3 <6>
    <6> DDR_B_CLK2 CK0 CK1
    103 104 DDR_B_CLK#3 <6>
    <6> DDR_B_CLK#2 CK0# CK1#
    105 106 2 2 1
    DDR_A_MA10 VDD11 VDD12 C50 C51 C664
    107 108 DDR_A_BS1 <6,8>
    A10/AP BA1 @
    <6,8> DDR_A_BS0 109 110 DDR_A_RAS# <6,8>
    BA0 RAS# 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
    111 112
    VDD13 VDD14 1 1 2
    113 114 DDR_CS0_DIMMB# <6>
    <6,8> DDR_A_WE# WE# S0#
    <6,8> DDR_A_CAS# 115 116 DDR_B_ODT0 <6>
    CAS# ODT0
    117 118
    DDR_A_MA13 VDD15 VDD16
    119 120 DDR_B_ODT1 <6>
    A13 ODT1
    121 122
    <6> DDR_CS1_DIMMB# S1# NC2
    123 124
    VDD17 VDD18
    125 126 +VREF_CA
    NCTEST VREF_CA
    127
    VSS27 VSS28
    128 Place near JDIMM2
    DDR_A_D32 129 130 DDR_A_D36
    DDR_A_D33 DQ32 DQ36 DDR_A_D37
    131 132 1 1
    DQ33 DQ37 C665 C666
    133 134
    VSS29 VSS30 DDR_A_DM4
    <6,8> DDR_A_DQS#4 135 136
    DQS#4 DM4 0.1U_0402_16V4Z 1000P_0402_50V7K
    <6,8> DDR_A_DQS4 137 138
    B DQS4 VSS31 DDR_A_D38 2 2 B
    139 140
    DDR_A_D34 VSS32 DQ38 DDR_A_D39
    141 142
    DDR_A_D35 DQ34 DQ39
    143 144
    DQ35 VSS33 DDR_A_D44
    145 146
    DDR_A_D40 VSS34 DQ44 DDR_A_D45
    147 148
    DDR_A_D41 DQ40 DQ45
    149 150
    DQ41 VSS35
    151 152 DDR_A_DQS#5 <6,8>
    DDR_A_DM5 VSS36 DQS#5
    153 154 DDR_A_DQS5 <6,8>
    DM5 DQS5
    155 156
    DDR_A_D42 VSS37 VSS38 DDR_A_D46
    157 158
    DDR_A_D43 DQ42 DQ46 DDR_A_D47
    159 160
    DQ43 DQ47
    161 162
    DDR_A_D48 VSS39 VSS40 DDR_A_D52
    163 164
    DDR_A_D49 DQ48 DQ52 DDR_A_D53
    165 166
    DQ49 DQ53
    167 168
    VSS41 VSS42 DDR_A_DM6
    <6,8> DDR_A_DQS#6 169 170
    DQS#6 DM6
    <6,8> DDR_A_DQS6 171 172
    DQS6 VSS43 DDR_A_D54
    173 174
    DDR_A_D50 VSS44 DQ54 DDR_A_D55
    175 176
    DDR_A_D51 DQ50 DQ55
    177 178
    DQ51 VSS45 DDR_A_D60
    179 180
    DDR_A_D56 VSS46 DQ60 DDR_A_D61
    181 182
    DDR_A_D57 DQ56 DQ61
    183 184
    DQ57 VSS47
    185 186 DDR_A_DQS#7 <6,8>
    DDR_A_DM7 VSS48 DQS#7
    187 188 DDR_A_DQS7 <6,8>
    For DRAM strap pin reservation DM7 DQS7
    189 190
    20100817 DDR_A_D58 VSS49 VSS50 DDR_A_D62
    191 192
    DDR_A_D59 DQ58 DQ62 DDR_A_D63
    193 194
    R961 1 DQ59 DQ63
    2 10K_0402_5% 195 196
    R153 1 @ VSS51 VSS52
    2 10K_0402_5% 197
    SA0 EVENT#
    198 DDR_EVENT# <6,8>
    +3VS 199 200 FCH_SMDAT0 <8,14,29>
    @ VDDSPD SDA
    1 2 201 SA1 SCL 202 FCH_SMCLK0 <8,14,29>
    A A
    1 1 203 VTT1 VTT2 204 +0.75VS
    C667 C668 R154
    10K_0402_5% 205 206
    2.2U_0603_6.3V4Z 0.1U_0402_16V4Z G1 G2
    2 2 FOX_AS0A626-U4SN-7F
    2

    CONN@
    R962
    CRB only one 4.7k 10K_0402_5%
    Security Classification Compal Secret Data Compal Electronics, Inc.
    DDR3 SO-DIMM B H:4mm Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title
    1

    For DRAM strap pin reservation Standard Type


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DDR3 SODIMM-II Socket
    20100817 P/N:SP07000H800 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 0.3
    F/P:FOX_AS0A626-U4SN-7F_204P DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 9 of 46
    5 4 3 2 1
    5 4 3 2 1

    LCD POWER CIRCUIT LCD/LED PANEL Conn.


    JLVDS1 W=60mils
    1 1 +INVPWR_B+
    41 G1 2 2
    +LCDVDD 42 3
    +3VALW +3VS G2 3 +LCDVDD_L @
    43 4 2 1 +LCDVDD
    G3 4
    For LCD flash W=60mils 44 5 +LCDVDD R841 0_0603_5%
    G4 5

    1
    Change as 10k ohm 45
    G5 6
    6
    D D
    46
    G6 7
    7
    INVT_PWM
    +3VS W=60mils
    R396 1 8
    8

    1
    300_0603_5% R393 C669 9 DISPOFF#
    10K_0402_5% 4.7U_0603_6.3V6K 9 I2CC_SCL
    10

    2
    10 I2CC_SDA
    2
    Change 0603 size 11
    11
    12
    R397 For DVT 12
    13 TXOUT0- DAC_BRIG <31>

    2
    13

    3
    D 1K_0402_5% S TXOUT0+
    14
    Q81 AO3413L_SOT23-3 14
    2 2 1 2 15
    15
    SSM3K7002F_SC59-3 G G Q82 16 TXOUT1-
    D 16 TXOUT1+
    S 1 17

    1
    C670 +LCDVDD 17
    18 18
    0.047U_0402_16V7K W=60mils 19 TXOUT2-
    19

    1
    D TXOUT2+
    2 <NCQD0 use> 20 20
    <5> APU_ENVDD 1 UMA@ 2 LCDVDD_ON 2 Q83
    21 21
    R963 0_0402_5% G SSM3K7002F_SC59-3 1 1 22 TXCLK-
    C1005 C1006 22 TXCLK+
    S 23

    3
    4.7U_0603_6.3V6K 0.1U_0402_16V4Z 23
    24 24
    25 25

    1
    2 2
    <18> VGA_ENVDD 1 DISO@ 2 26 26
    R964 0_0402_5% R395 Change 0603 size 27 27 R862 2 @ 1 0_0402_5% LOCAL_DIM <31>
    28
    100K_0402_5% For DVT 28
    29
    29 R860 2 @
    30 1 0_0402_5% COLOY_ENG_EN <31>
    2

    30
    31 31
    32 32
    <19> VGA_ENBKL R1097 1 DISO@ 2 0_0402_5% 33
    33
    34 34
    35 35
    36 36
    +INVPWR_B+ L2 B+ R156 1 UMA@ 2 0_0402_5% 37
    <5> APU_ENBKL ENBKL <31> 37 +3VS
    W=60mils FBMA-L11-201209-221LMA30T_0805 38
    C 38 USB20_N5 <14> C
    2 1 1 2 39 39 USB20_P5 <14>
    L1 L113 40
    FBMA-L11-201209-221LMA30T_0805 1.2UH_1127AS-1R2N_2.4A_30% 40
    1 2
    2 1 R157 100K_0402_1% IPEX_20143-040E-20F
    EMI request for DVT +3VS
    CONN@
    1 1
    C673 C674 SM010014520 3000ma
    680P_0402_50V7K 68P_0402_50V8J 220ohm@100mhz

    1
    @
    2 2 DCR 0.04 R483 D15 @
    10K_0402_5% 6 3 USB20_N5
    CH3 CH2
    +LCDVDD Place closed to JLVDS1

    2
    1 2
    R484 0_0402_5% +3VS 5 2
    Vp Vn
    C1007 2 1 220P_0402_50V7K DAC_BRIG 1 1
    1 2 DISPOFF# C671 C672
    <31> BKOFF#
    C677 2 1 220P_0402_50V7K INVT_PWM USB20_P5 4
    CH4 CH1
    1
    RB751V_SOD323 10U_0603_6.3V6M 0.1U_0402_16V4Z
    C679 2 1 220P_0402_50V7K DISPOFF# 2 1 D4 @ 2 2 CM1293-04SO_SOT23-6
    10K_0402_5% R485
    Change P/N as SC300000B00
    Change 0603 size
    For DVT

    B
    VGA ONLY B
    TXCLK+ 2 3 VGA_TXCLK+
    TXCLK- VGA_TXCLK- VGA_TXCLK+ <18>
    1 4 VGA_TXCLK- <18>
    DISO@RP2
    DISO@RP2 0_0404_4P2R_5%
    TXOUT2+ 2 3 VGA_TXOUT2+
    TXOUT2- VGA_TXOUT2- VGA_TXOUT2+ <18> INVT_PWM
    1 4 VGA_TXOUT2- <18> <5> APU_BLPWM 1 2
    DISO@RP4
    DISO@RP4 0_0404_4P2R_5% R1098 UMA@ 0_0402_5%
    TXOUT1+ 2 3 VGA_TXOUT1+ 1 2
    VGA_TXOUT1+ <18> <31> EC_INVT_PWM

    1
    TXOUT1- 1 4 VGA_TXOUT1- R158 DISO@ 0_0402_5%
    VGA_TXOUT1- <18>
    DISO@RP6
    DISO@RP6 0_0404_4P2R_5% 1 2 R1100
    TXOUT0+ VGA_TXOUT0+ <18> VGA_INVT_PWM
    2 3 R1099 @ 0_0402_5% 100K_0402_5%
    VGA_TXOUT0+ <18>
    TXOUT0- 1 4 VGA_TXOUT0-
    VGA_TXOUT0- <18>
    DISO@RP8
    DISO@RP8 0_0404_4P2R_5%
    2

    I2CC_SCL 0_0402_5% 2 DISO@ 1 R270 VGA_LCD_CLK


    VGA_LCD_CLK <19>
    I2CC_SDA 0_0402_5% 2 1 R272 VGA_LCD_DAT
    VGA_LCD_DAT <19>
    DISO@

    UMA ONLY
    TXCLK+ 1 4 APU_TXCLK+
    APU_TXCLK+ <5>
    TXCLK- 2 3 APU_TXCLK-
    APU_TXCLK- <5>
    UMA@RP1
    UMA@ RP1 0_0404_4P2R_5%
    TXOUT2+ 1 4 APU_TXOUT2+
    APU_TXOUT2+ <5>
    TXOUT2- 2 3 APU_TXOUT2-
    APU_TXOUT2- <5>
    UMA@RP3
    UMA@ RP3 0_0404_4P2R_5%
    TXOUT1+ 1 4 APU_TXOUT1+
    TXOUT1- APU_TXOUT1- APU_TXOUT1+ <5>
    2 3 APU_TXOUT1- <5>
    UMA@RP5
    UMA@ RP5 0_0404_4P2R_5%
    TXOUT0+ 1 4 APU_TXOUT0+
    APU_TXOUT0+ <5>
    TXOUT0- 2 3 APU_TXOUT0-
    APU_TXOUT0- <5>
    UMA@RP7
    UMA@ RP7 0_0404_4P2R_5%
    A A
    I2CC_SCL 0_0402_5% 2 UMA@ 1 R269 APU_LCD_CLK
    APU_LCD_CLK <5>
    I2CC_SDA 0_0402_5% 2 1 R271 APU_LCD_DATA
    APU_LCD_DATA <5>
    UMA@

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    LVDS/CAMERA
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 10 of 46
    5 4 3 2 1
    5 4 3 2 1

    @ R521
    0_0603_5%

    +3VS
    1 2 W=40mils HDMI connector
    +HDMI_5V_OUT
    D7 F2 JHDMI1

    2
    +3VS +HDMI_5V_OUT 2 1 +HDMI_5V 1 2 HDMI_HPD 19
    +5VS HP_DET
    R965 1 +HDMI_5V_OUT 18 +5V

    0_0402_5%
    CH491DPT_SOT23-3 1.1A_6V_SMD1812P110TF 17
    C690 HDMI_SDATA DDC/CEC_GND
    16 SDA

    2
    R522 R161 Change P/N SCS00002000 0.1U_0402_16V4Z HDMI_SCLK 15

    1
    2 SCL

    2K_0402_5%

    2K_0402_5%
    4.7K_0402_5%

    4.7K_0402_5%
    14
    Reserved

    1
    R966 R968 13
    HDMI_R_CK- CEC
    12 20
    D UMA@ CK- GND D
    11 21

    1
    CK_shield GND

    2
    G
    R970 2 1 0_0402_5% HDMI_R_CK+ 10 22
    <5> APU_HDMI_CLK HDMI_R_D0- CK+ GND
    9 23

    2
    R971 2 DISO@ 1 0_0402_5% HDMI_SCLK D0- GND
    3 1 8
    <19> VGA_HDMI_SCLK HDMI_R_D0+ D0_shield

    D
    7
    UMA@ Q86 HDMI_R_D1- D0+
    6
    D1-

    2
    G
    R972 2 1 0_0402_5% BSH111 1N_SOT23-3 5
    <5> APU_HDMI_DATA HDMI_R_D1+ D1_shield
    4
    R973 2 DISO@ 1 0_0402_5% HDMI_SDATA HDMI_R_D2- D1+
    3 1 3
    D2-
    <19> VGA_HDMI_SDATA

    D
    2
    Q128 HDMI_R_D2+ D2_shield
    1
    BSH111 1N_SOT23-3 D2+
    SUYIN_100042MR019S153ZL
    2 @ 1 CONN@
    R172 0_0402_5%
    <NAV70 use>
    2 @ 1
    R816 0_0402_5%

    Place closed to JHDMI1 SM070001310 400ma 90ohm@100mhz DCR 0.3

    HDMI_C_CLK- R514 1 2 0_0402_5% HDMI_R_CK-

    1 1 2 2
    L68
    WCM-2012-900T_0805
    @ 4 3
    4 3
    C HDMI_C_CLK+ R513 1 0_0402_5% HDMI_R_CK+ C
    2

    HDMI_C_TX0- R516 1 2 0_0402_5% HDMI_R_D0-

    1 1 2 2
    L69
    WCM-2012-900T_0805
    @ 4 3
    4 3
    R524 HDMI_C_TX0+ R515 1 2 0_0402_5% HDMI_R_D0+
    1 2

    0_0402_5% HDMI_C_TX1- R518 1 2 0_0402_5% HDMI_R_D1-


    +3VS @
    1 2
    L54 1 2
    WCM-2012-900T_0805

    2
    @ 4 3
    R527 4 3
    0_0402_5% HDMI_C_TX1+ R517 1 2 0_0402_5% HDMI_R_D1+

    Use common via on related pair

    1 1
    HDMI_C_TX2- R520 1 2 0_0402_5% HDMI_R_D2-
    C
    2 1 2 HDMI_HPD 1 2
    R974 DISO@2 0_0402_5% HDMI_C_TX2-_R B R525 150K_0402_5% L70 1 2
    <19> VGA_HDMI_TXD2- 1
    R975 1 DISO@2 0_0402_5% HDMI_C_TX2+_R E WCM-2012-900T_0805
    <19> VGA_HDMI_TXD2+

    1
    R976 1 DISO@2 0_0402_5% HDMI_C_TX1-_R 2 DISO@ 1 Q34 @ 4 3
    <19> VGA_HDMI_TXD1- <19> VGA_HDMI_DET 4 3
    R978 1 DISO@2 0_0402_5% HDMI_C_TX1+_R R977 0_0402_5% MMBT3904_NL_SOT23-3 R528
    <19> VGA_HDMI_TXD1+
    R979 DISO@2 0_0402_5% HDMI_C_TX0-_R HDMI_C_TX2+ R519 1 0_0402_5% HDMI_R_D2+
    B From VGA <19> VGA_HDMI_TXD0-
    R980
    1
    1 DISO@2 0_0402_5% HDMI_C_TX0+_R
    <5> APU_HDMI_HPD 2 UMA@ 1
    365K_0402_1%
    @
    2
    B
    <19> VGA_HDMI_TXD0+ HDMI_C_CLK-_R
    R982 1 DISO@2 0_0402_5% R981 0_0402_5%
    <19> VGA_HDMI_TXC-

    2
    1
    R983 1 DISO@2 0_0402_5% HDMI_C_CLK+_R
    <19> VGA_HDMI_TXC+
    R530

    R984 1 UMA@2 0_0402_5% HDMI_C_TX2-_R 10K_0402_5%


    <5> APU_HDMI_TX2N
    R985 1 UMA@2 0_0402_5% HDMI_C_TX2+_R
    <5> APU_HDMI_TX2P

    2
    R986 1 UMA@2 0_0402_5% HDMI_C_TX1-_R
    <5> APU_HDMI_TX1N HDMI_C_TX1+_R
    R987 1 UMA@2 0_0402_5%
    <5> APU_HDMI_TX1P
    R988 UMA@2 0_0402_5% HDMI_C_TX0-_R
    From APU <5> APU_HDMI_TX0N
    R989
    1
    1 UMA@2 0_0402_5% HDMI_C_TX0+_R
    <5> APU_HDMI_TX0P
    R990 1 UMA@2 0_0402_5% HDMI_C_CLK-_R
    <5> APU_HDMI_CLKN HDMI_C_CLK+_R
    R991 1 UMA@2 0_0402_5%
    <5> APU_HDMI_CLKP

    Place closed to JHDMI1

    HDMI_C_TX2-_R C508 2 1 0.1U_0402_16V7K HDMI_C_TX2- R509 1 2 499_0402_1%


    HDMI_C_TX2+_R C509 2 1 0.1U_0402_16V7K HDMI_C_TX2+ R508 1 2 499_0402_1%

    HDMI_C_TX1-_R C510 2 1 0.1U_0402_16V7K HDMI_C_TX1- R506 1 2 499_0402_1%


    HDMI_C_TX1+_R C511 2 1 0.1U_0402_16V7K HDMI_C_TX1+ R505 1 2 499_0402_1%

    HDMI_C_TX0-_R C512 2 1 0.1U_0402_16V7K HDMI_C_TX0- R503 1 2 499_0402_1%


    HDMI_C_TX0+_R C513 2 1 0.1U_0402_16V7K HDMI_C_TX0+ R502 1 2 499_0402_1%
    A HDMI_C_CLK-_R A
    C514 2 1 0.1U_0402_16V7K HDMI_C_CLK- R501 1 2 499_0402_1%
    HDMI_C_CLK+_R C515 2 1 0.1U_0402_16V7K HDMI_C_CLK+ R500 1 2 499_0402_1%
    1

    D
    +HDMI_5V_OUT 2 2N7002_SOT23
    G Q87
    1

    S
    3

    R512
    Security Classification Compal Secret Data Compal Electronics, Inc.
    100K_0402_5% Issued Date 2010/08/20 2011/08/20 Title
    Deciphered Date
    HDMI Connector
    2

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 11 of 46
    5 4 3 2 1
    A B C D E

    W=40mils
    +5VS +R_CRT_VCC +CRT_VCC

    CRT Connector

    2
    D14 F1 W=40mils
    2 1 1 2

    CH491DPT_SOT23-3 1.1A_6VDC_FUSE
    1
    D32 D33 Change P/N SCS00002000
    PJDLC05C_SOT23-3 PJDLC05C_SOT23-3 C691
    1 @ @ 0.1U_0402_16V4Z 1
    2

    1
    CRT_R L57 1 2 FCM2012CF-800T06_2P CRT_R_1 JCRT1
    6
    T95PAD 11
    CRT_G L58 1 2 FCM2012CF-800T06_2P CRT_G_1 1
    7
    12
    CRT_B L59 1 2 FCM2012CF-800T06_2P CRT_B_1 2
    8

    10P_0402_50V8J

    10P_0402_50V8J

    10P_0402_50V8J
    13

    1
    150_0402_1%

    150_0402_1%

    150_0402_1%
    1 1 1 1 1 1 3

    C692

    C693

    C694
    C697 C695 C696 9

    R531

    R532

    R533
    14 G 16
    4 G 17
    2 2 2 2 2 2
    10
    2

    2
    10P_0402_50V8J 10P_0402_50V8J 15
    10P_0402_50V8J 1 T97PAD 5
    C698
    C-H_13-12201513CP
    100P_0402_50V8J CONN@
    2
    +CRT_VCC
    P/N : DC060003V00
    L60 1 2 CRT_HSYNC_2
    C699 1
    F/P : SUYIN_070546HR015M21MZR_15P-T
    2 0.1U_0402_16V4Z R537 2 1 10K_0402_5% FCM2012CF-800T06_2P DSUB_12
    2 2
    L81 1 2 CRT_VSYNC_2 1
    5

    U23 FCM2012CF-800T06_2P 1 1
    OE#
    P

    CRT_HSYNC 2 4 CRT_HSYNC_1 C700 C702 DSUB_15


    A Y 10P_0402_50V8J 10P_0402_50V8J C703 2
    G

    2 2 68P_0402_50V8J 1
    74AHCT1G125GW _SOT353-5
    3

    C704
    +CRT_VCC 68P_0402_50V8J
    2
    C701 1 2 0.1U_0402_16V4Z
    5

    U19
    OE#
    P

    CRT_VSYNC 2 4 CRT_VSYNC_1
    A Y
    G

    74AHCT1G125GW _SOT353-5
    3

    Close to Conn side


    +CRT_VCC
    3 3

    +3VS

    Use common via on related pair

    1
    R549 R548
    APU_CRT_R R995 2 UMA@ 1 0_0402_5% CRT_R 4.7K_0402_5% 4.7K_0402_5%
    <5> APU_CRT_R
    APU_CRT_G R996 2 UMA@ 1 0_0402_5% CRT_G
    <5> APU_CRT_G

    2
    G
    APU_CRT_B R997 2 UMA@ 1 0_0402_5% CRT_B
    <5> APU_CRT_B
    DSUB_12 1 3 CRT_DATA
    APU_CRT_HSYNC R998 2 UMA@ 1 0_0402_5% CRT_HSYNC
    From APU

    S
    <5> APU_CRT_HSYNC
    Q89

    2
    APU_CRT_VSYNC R999 2 UMA@ 1 0_0402_5% CRT_VSYNC BSH111 1N_SOT23-3

    G
    <5> APU_CRT_VSYNC
    APU_CRT_DDC_SDA R1000 2 UMA@ 1 0_0402_5% CRT_DATA DSUB_15 1 3 CRT_CLK
    <5> APU_CRT_DDC_SDA

    S
    <5> APU_CRT_DDC_SCL APU_CRT_DDC_SCL R1001 2 UMA@ 1 0_0402_5% CRT_CLK Q129
    BSH111 1N_SOT23-3

    2 @ 1
    R1009 0_0402_5%

    VGA_CRT_R R1002 2 DISO@ 1 0_0402_5% CRT_R


    <19> VGA_CRT_R
    2 @ 1
    VGA_CRT_G R1003 2 DISO@ 1 0_0402_5% CRT_G R1010 0_0402_5%
    <19> VGA_CRT_G
    4 4
    VGA_CRT_B R1004 2 DISO@ 1 0_0402_5% CRT_B
    <19> VGA_CRT_B
    From VGA VGA_CRT_HSYNC R1005 2 DISO@ 1 0_0402_5% CRT_HSYNC
    <19> VGA_CRT_HSYNC
    VGA_CRT_VSYNC R1006 2 DISO@ 1 0_0402_5% CRT_VSYNC
    <19> VGA_CRT_VSYNC

    <19> VGA_CRT_DATA
    VGA_CRT_DATA R1007 2 DISO@ 1 0_0402_5% CRT_DATA Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title
    VGA_CRT_CLK R1008 2 DISO@ 1 0_0402_5% CRT_CLK
    <19> VGA_CRT_CLK
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    CRT Connector
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 12 of 46
    A B C D E
    A B C D E

    For PCIE device reset on FS1 (GFX,GLAN,WLAN,LVDS Travis)

    For DVT 1011 U31E


    PCIE_RST# P1 W2 PAD T96
    PCIE_RST_L PCICLK0

    PCI CLKS
    A_RST# L1 W1
    <31> A_RST# A_RST_L PCICLK1/GPO36 PCI_CLK1 <17>
    PCICLK2/GPO37 W3 PCI_CLK2 <17>
    C53 1 2 0.1U_0402_16V7K UMI_RX0P_C AD26 W4
    <6> UMI_RX0P UMI_RX0N_C UMI_TX0P PCICLK3/GPO38 PCI_CLK3 <17>
    C54 1 2 0.1U_0402_16V7K AD27 Y1
    <6> UMI_RX0N UMI_RX1P_C UMI_TX0N PCICLK4/14M_OSC/GPO39 PCI_CLK4 <17>
    C55 1 2 0.1U_0402_16V7K AC28
    <6> UMI_RX1P UMI_TX1P
    C56 1 2 0.1U_0402_16V7K UMI_RX1N_C AC29 V2
    1 <6> UMI_RX1N UMI_RX2P_C UMI_TX1N PCIRST_L +3VALW 1
    C57 1 2 0.1U_0402_16V7K AB29 PAD T92
    <6> UMI_RX2P UMI_RX2N_C UMI_TX2P
    C58 1 2 0.1U_0402_16V7K AB28 C1234
    <6> UMI_RX2N UMI_RX3P_C UMI_TX2N
    C59 1 2 0.1U_0402_16V7K AB26 AA1 1 2
    <6> UMI_RX3P UMI_TX3P AD0/GPIO0
    C60 1 2 0.1U_0402_16V7K UMI_RX3N_C AB27 AA4
    <6> UMI_RX3N UMI_TX3N AD1/GPIO1

    PCI EXPRESS I/F


    AA3 0.1U_0402_16V4Z
    AD2/GPIO2

    5
    <6> UMI_TX0P AE24 AB1
    UMI_RX0P AD3/GPIO3
    <6> UMI_TX0N AE23 AA5 2

    P
    UMI_RX0N AD4/GPIO4 A_RST# R175 1 B
    <6> UMI_TX1P AD25
    UMI_RX1P AD5/GPIO5
    AB2 2 33_0402_5% Y 4 PLT_RST# <18,26,29>
    <6> UMI_TX1N AD24 AB6 1 A
    UMI_RX1N AD6/GPIO6

    G
    2
    <6> UMI_TX2P AC24 AB5 1 1 @ 2 PCIE_RST#
    UMI_RX2P AD7/GPIO7 R174 R582 0_0402_5%
    <6> UMI_TX2N AC25 AA6

    3
    UMI_RX2N AD8/GPIO8 C1233 @ 8.2K_0402_5% U28
    <6> UMI_TX3P AB25 UMI_RX3P AD9/GPIO9 AC2
    <6> UMI_TX3N AB24 AC3 150P_0402_50V8J NC7SZ08P5X_NL_SC70-5
    UMI_RX3N AD10/GPIO10 2
    AC4

    1
    R560 590_0402_1% AD11/GPIO11
    2 1 AD29 PCIE_CALRP AD12/GPIO12 AC1
    +PCIE_VDDAN R561 2 1 2K_0402_1% AD28 AD1
    PCIE_CALRN AD13/GPIO13
    AD14/GPIO14 AD2
    AA28 GPP_TX0P AD15/GPIO15 AC6 Need to check material?
    AA29 GPP_TX0N AD16/GPIO16 AE2
    Y29 AE1 +1.8VS +3VS
    GPP_TX1P AD17/GPIO17
    Y28 GPP_TX1N AD18/GPIO18 AF8

    1
    C61 1 2 0.1U_0402_16V7K PCIE_FTX_DRX_P2 Y26 AE3
    <26> PCIE_FTX_C_DRX_P2 PCIE_FTX_DRX_N2 GPP_TX2P AD19/GPIO19
    C62 0.1U_0402_16V7K R164
    LAN <26> PCIE_FTX_C_DRX_N2
    C717
    1
    1
    2
    2 0.1U_0402_16V7K PCIE_FTX_DRX_P3
    Y27
    W28
    GPP_TX2N AD20/GPIO20 AF1
    AG1 10K_0402_5%
    <29> PCIE_FTX_C_DRX_P3 PCIE_FTX_DRX_N3 GPP_TX3P AD21/GPIO21
    WLAN C63 1 2 0.1U_0402_16V7K W29 AF2
    <29> PCIE_FTX_C_DRX_N3 GPP_TX3N AD22/GPIO22

    2
    G
    AE9 PCI_AD23 <17>

    2
    AD23/GPIO23
    AA22 GPP_RX0P AD24/GPIO24 AD9 PCI_AD24 <17>

    PCI I/F
    Y21 AC11 APU_PWRGD 3 1
    GPP_RX0N AD25/GPIO25 PCI_AD25 <17> H_PWRGD_L <44>

    D
    AA25 GPP_RX1P AD26/GPIO26 AF6 PCI_AD26 <17>
    AA24 GPP_RX1N AD27/GPIO27 AF4 PCI_AD27 <17>
    W23 AF3 FDV301N_NL_SOT23-3
    <26> PCIE_FRX_DTX_P2 GPP_RX2P AD28/GPIO28
    V24 AH2 Q90
    2 <26> PCIE_FRX_DTX_N2 GPP_RX2N AD29/GPIO29 2
    <29> PCIE_FRX_DTX_P3 W24 GPP_RX3P AD30/GPIO30 AG2
    <29> PCIE_FRX_DTX_N3 W25 GPP_RX3N AD31/GPIO31 AH3
    CBE0_L AA8
    CBE1_L AD5
    AD8 +3VALW
    CBE2_L C1199
    CBE3_L AA10
    FRAME_L AE8 1 2
    AB9
    DEVSEL_L
    close to FCH within 1" M23
    PCIE_RCLKP/NB_LNK_CLKP IRDY_L
    AJ3 0.1U_0402_16V4Z

    5
    P23 AE7 U33
    PCIE_RCLKN/NB_LNK_CLKN TRDY_L
    AC5 2 B

    P
    R564 1 APU_DISP_CLKP_R PAR VGA_PWRGD VGA_PWRGD_R
    <5> APU_DISP_CLKP 2 0_0402_5% U29 AF5 <24,43> VGA_PWRGD 4 1 @ 2
    R565 1 APU_DISP_CLKN_R NB_DISP_CLKP STOP_L Y
    <5> APU_DISP_CLKN 2 0_0402_5% U28
    NB_DISP_CLKN PERR_L
    AE6 1
    A
    R830 0_0402_5%

    G
    AE4
    SERR_L NC7SZ08P5X_NL_SC70-5
    T26 AE11

    3
    NB_HT_CLKP REQ0_L @
    T27 AH5 1 2
    NB_HT_CLKN REQ1_L/GPIO40 R838 100K_0402_5%
    AH4
    R162 1 APU_CLKP_R REQ2_L/CLK_REQ8_L/GPIO41
    <5> APU_CLKP 2 0_0402_5% V21 AC12
    R163 1 APU_CLKN_R CPU_HT_CLKP REQ3_L/CLK_REQ5_L/GPIO42
    <5> APU_CLKN 2 0_0402_5% T21
    CPU_HT_CLKN GNT0_L
    AD12 1 2
    AJ5 R839 0_0402_5%
    CLK_PCIE_VGA_R GNT1_L/GPO44 PE_GPIO0 <18>
    <18> CLK_PCIE_VGA
    R569 1 2 0_0402_5% V23
    SLT_GFX_CLKP GNT2_L/GPO45
    AH6 PE_GPIO1 <24,35> For DVT 1011
    R570 1 2 0_0402_5% CLK_PCIE_VGA#_R T23 AB12
    <18> CLK_PCIE_VGA# SLT_GFX_CLKN GNT3_L/CLK_REQ7_L/GPIO46
    AB11 1 2
    R571 1 CLK_PCIE_LAN_R CLKRUN_L
    <26> CLK_PCIE_LAN 2 0_0402_5% L29 AD7 R99 10K_0402_5%
    R572 1 CLK_PCIE_LAN#_R GPP_CLK0P LOCK_L
    LAN <26> CLK_PCIE_LAN# 2 0_0402_5% L28
    GPP_CLK0N
    CLOCK GENERATOR

    AJ6 VGA_PWRGD_R
    R573 1 CLK_PCIE_MINI1_R INTE_L/GPIO32
    <29> CLK_PCIE_MINI1 2 0_0402_5% N29 AG6
    R574 1 CLK_PCIE_MINI1#_R GPP_CLK1P INTF_L/GPIO33
    WLAN <29> CLK_PCIE_MINI1# 2 0_0402_5% N28
    GPP_CLK1N INTG_L/GPIO34
    AG4
    RTC BATT Conn.
    AJ4
    INTH_L/GPIO35 +RTCBATT
    M29
    GPP_CLK2P
    M28
    GPP_CLK2N

    1
    CONN@
    3 R853 1 3
    T25 2 0_0402_5% JBATT2

    +
    GPP_CLK3P LPC_CLK0 <17>
    V25 H24 R575 1 2 22_0402_5%
    GPP_CLK3N LPCCLK0 LPC_CLK0_EC <31>
    LPC
    H25 LPC_CLK1 <17>
    LPCCLK1
    L24 J27 LPC_AD0 <31>
    GPP_CLK4P LAD0
    L23 J26 LPC_AD1 <31>
    GPP_CLK4N LAD1
    H29 LPC_AD2 <31>
    LAD2
    P25 H28 LPC_AD3 <31>
    GPP_CLK5P LAD3
    M25 G28 LPC_FRAME# <31>
    GPP_CLK5N LFRAME_L
    J25
    LDRQ0_L
    P29 AA18
    GPP_CLK6P LDRQ1_L/CLK_REQ6_L/GPIO49
    P28 AB19 SERIRQ <31>
    GPP_CLK6N SERIRQ/GPIO48 SUYIN_060003HA002G202ZL

    -
    N26 P/N: SP07000OU00

    2
    GPP_CLK7P
    N27
    GPP_CLK7N F/P: SUYIN_060003HA002G202ZL_2P
    G21 ALLOW_STOP# <5>
    ALLOW_LDTSTP/DMA_ACTIVE_L
    CPU

    T29 H21 FCH_PROCHOT# <5>


    GPP_CLK8P PROCHOT_L +RTCBATT
    T28 K19 APU_PWRGD <5>
    GPP_CLK8N LDT_PG
    G22
    LDT_STP_L
    Follow result by vender 10/11 LDT_RST_L
    J24 APU_RST# <5>
    <29> CLK_SD_48M L25
    14M_25M_48M_OSC

    1
    1 2
    C1 RTC_32KHI R179
    32K_X1
    1

    C66 1K_0402_5%
    RTC

    27P_0402_50V8J 1M_0603_5% 25M_CLK_X1 L26 C2 RTC_32KHO


    Y3 R576 25M_X1 32K_X2 +RTCVCC
    D23

    2
    C67 D2 RTC_CLK <17,31>
    2

    27P_0402_50V8J RTCCLK
    B2 2
    25M_CLK_X2 INTRUDER_ALERT_L
    1 2 L27 B1 1 2 1
    25M_X2 VDDBT_RTC_G R864 510_0402_5%
    25MHZ_20PF_7A25000012 3 +CHGRTC

    0.1U_0402_16V4Z
    21807-A11-HUDSON-M1_FCBGA605 C1272 1 1 C1271 W=20mils

    2
    0.1U_0402_16V4Z

    1U_0402_6.3V4Z

    1 DAN202UT106_SC70-3
    FCH : SA000046H60 (S IC 218-0792001 A12 HUDSON-M1 FCBGA 605P) R865 C1270
    4 4
    Close to FCH 2 2
    @
    FCH : SA000046H70 (S IC 218-0792006 A13 HUDSON-M1 FCBGA 605P) for Clear CMOS 0_0603_5%
    2
    C64 1 2 RTC_32KHI

    1
    22P_0402_50V8J Y4
    1

    4 OSC NC 3
    R563
    20M_0603_5% 1 2
    OSC NC
    32.768KHZ_12.5PF_Q13MC14610050_10PPM
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title
    2

    C65 1 2 RTC_32KHO
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    FCH PCIE/PCI/ACPI/LPC/RTC
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    22P_0402_50V8J Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 13 of 46
    A B C D E
    A B C D E

    +3VALW

    1 2 USB_OC2# 1 2 USB_OC7#
    R870 10K_0402_5% R929 10K_0402_5% U31A
    1 2 USB_OC1# 1 @ 2 EC_LID_OUT#

    USB MISC
    R871 10K_0402_5% R930 10K_0402_5%
    1 2 USB_OC0# 1 2 USB_OC5# J2 A10
    <31> EC_SWI# PCI_PME_L/GEVENT4_L USBCLK/14M_25M_48M_OSC

    ACPI/WAKE UP EVENTS
    R872 10K_0402_5% R931 10K_0402_5% K1 R578
    FCH_SIC ODD_DA#_FCH RI_L/GEVENT22_L USB_RCOMP 1
    1 2 1 2 D3 G19 2
    R603 10K_0402_5% R932 10K_0402_5% SPI_CS3_L/GBE_STAT1/GEVENT21_L USB_RCOMP 11.8K_0402_1%
    <31> SLP_S3# F1 SLP_S3_L
    1 2 FCH_SID 1 2 ODD_DETECT# H1
    <31> SLP_S5# SLP_S5_L
    R604 10K_0402_5% R933 10K_0402_5%
    <31> PBTN_OUT# F2
    PWR_BTN_L
    10mils and <1"
    1 2 FCH_PCIE_WAKE# FCH_PWRGD H5
    PWR_GOOD

    USB 1.1
    R605 10K_0402_5% G6 J10
    1 LAN_CLKREQ# SUS_STAT_L USB_FSD1P/GPIO186 1
    1 2 T82PAD B3
    TEST0 USB_FSD1N
    H11
    R817 10K_0402_5% T83PAD C4
    TEST1/TMS
    T84PAD F6
    TEST2 USB_FSD0P/GPIO185
    H9 USB_HSD[13:0]P/N:
    +3VS AD21 J8
    <31> EC_GA20 GA20IN/GEVENT0_L USB_FSD0N USB P/N pairs with trace lengths up to
    <31> EC_KBRST# AE21
    K2
    KBRST_L/GEVENT1_L
    B12
    10" and have a decoupling 5.6-pF capacitor
    <31> EC_SCI# LPC_PME_L/GEVENT3_L USB_HSD13P footprint placed near the USB connector or device.
    <31> EC_SMI# J29 A12
    MINI1_CLKREQ# LPC_SMI_L/GEVENT23_L USB_HSD13N
    1 2 H2
    GEVENT5_L
    R818 10K_0402_5% +3VALW R579 1 @ 2 10K_0402_5% J1 F11
    NB_PWRGD SYS_RESET_L/GEVENT19_L USB_HSD12P
    1 2 <26,29> FCH_PCIE_WAKE# H6 E11
    R597 4.7K_0402_5% WAKE_L/GEVENT8_L USB_HSD12N
    1 2 FCH_SMCLK0
    <5> H_THERMTRIP#
    F3
    J6
    IR_RX1/GEVENT20_L
    THRMTRIP_L/SMBALERT_L/GEVENT2_L USB_HSD11P E14 Root
    R598 2.2K_0402_5% NB_PWRGD AC19 E12
    FCH_SMDAT0 NB_PWRGD USB_HSD11N
    1 2
    R599 2.2K_0402_5% G1 J12
    <31> EC_RSMRST# RSMRST_L USB_HSD10P
    USB_HSD10N J14
    R580 2 @ 1 0_0402_5% AD19 CLK_REQ4_L/SATA_IS0_L/GPIO64
    AA16 CLK_REQ3_L/SATA_IS1_L/GPIO63 USB_HSD9P A13
    R581 2 1 0_0402_5% AB21 B13
    SMARTVOLT1/SATA_IS2_L/GPIO50 USB_HSD9N
    <26> LAN_CLKREQ# AC18 CLK_REQ0_L/SATA_IS3_L/GPIO60
    +3VS @ AF20 D13
    SATA_IS4_L/FANOUT3/GPIO55 USB_HSD8P USB20_P8 <29>
    C111 0.1U_0402_16V7K AE19 C13 MINI1-WLAN
    SATA_IS5_L/FANIN3/GPIO59 USB_HSD8N USB20_N8 <29>
    1 2 <27> FCH_SPKR AF19 SPKR_GPIO66

    GPIO

    USB 2.0
    <8,9,29> FCH_SMCLK0 AD22 SCL0_GPIO43 USB_HSD7P G12 USB20_P7 <33>
    5

    BT
    2
    <8,9,29> FCH_SMDAT0
    FCH_SMCLK1
    AE22
    F5
    SDA0_GPIO47 USB_HSD7N G14 USB20_N7 <33> Root
    P

    B EC_PWROK <31> FCH_SMDAT1 SCL1_GPIO227


    <44> FCH_PWRGD 4 Y F4 SDA1_GPIO228 USB_HSD6P G16 USB20_P6 <29> EHCI CTL
    A 1 VGATE <31,44> AH21 CLK_REQ2_L/FANIN4_GPIO62 USB_HSD6N G18 USB20_N6 <29> CardReader DEV 19, Fn 2
    G

    2 <29> MINI1_CLKREQ# AB18 CLK_REQ1_L/FANOUT4_GPIO61


    @ NC7SZ08P5X_NL_SC70-5 E1 D16 USB20_P5 <10>
    3

    C112 IR_LED_L/LLB_L/GPIO184 USB_HSD5P


    U30 @ AJ21 SMARTVOLT2/SHUTDOWN_L/GPIO51 USB_HSD5N C16 USB20_N5 <10> Camera
    0.1U_0402_16V7K H4
    2 1 VRAM_SEL DDR3_RST_L/GEVENT7_L 2
    D5 GBE_LED0/GPIO183 USB_HSD4P B14
    D7 GBE_LED1/GEVENT9_L USB_HSD4N A14
    G5 GBE_LED2/GEVENT10_L
    K3 GBE_STAT0/GEVENT11_L USB_HSD3P E18
    VGA_CLKREQ#_R AA20 E16
    @ VRAM_SEL CLK_REQG_L/GPIO65_OSCIN USB_HSD3N
    +3VS 1 2
    R626 2.2K_0402_5% VRAM_Freq : 1->900Hz J16
    0-> 800Hz* USB_HSD2P USB20_P2 <33>
    @ USB_OC7# USB/B (Right)
    1 2 H3
    BLINK/USB_OC7_L/GEVENT18_L USB_HSD2N
    J18 USB20_N2 <33> Root

    USB OC
    R404 100K_0402_5% D1
    <31> EC_LID_OUT# USB_OC5# USB_OC6_L/IR_TX1/GEVENT6_L
    E4
    USB_OC5_L/IR_TX0/GEVENT17_L USB_HSD1P
    B17 USB20_P1 <33> EHCI CTL
    ODD_DA#_FCH D4 A17 USB/B (Right) DEV 18, Fn 2
    <30> ODD_DA#_FCH USB_OC4_L/IR_RX0/GEVENT16_L USB_HSD1N USB20_N1 <33>
    ODD_DETECT# E8
    <30> ODD_DETECT# USB_OC3_L/AC_PRES/TDO/GEVENT15_L
    1 @ 2 VGA_CLKREQ#_R USB_OC2# F7 A16 <Support Wakeup>
    <33> USB_OC2# USB_OC2_L/TCK/GEVENT14_L USB_HSD0P USB20_P0 <33>
    R173 10K_0402_5% USB_OC1# E7 B16 USB Conn (Left)
    FCH_SMCLK1 <33> USB_OC1# USB_OC1_L/TDI/GEVENT13_L USB_HSD0N USB20_N0 <33>
    1 2 <33> USB_OC0# F8
    USB_OC0_L/TRST_L/GEVENT12_L
    R587 10K_0402_5%
    1 2 FCH_SMDAT1
    R588 10K_0402_5%

    HD AUDIO
    1 2 EC_RSMRST# R583 1 2 33_0402_5% HDA_BITCLK M3 D25 GPIO193 R584 2 1 10K_0402_5%
    <27> HDA_BITCLK_AUDIO HDA_SDOUT AZ_BITCLK SCL2/GPIO193 GPIO194
    R606 2.2K_0402_5% R165 1 2 33_0402_5% N1 F23 R586 2 1 10K_0402_5%
    HDA_BITCLK <27> HDA_SDOUT_AUDIO HDA_SDIN0 AZ_SDOUT SDA2/GPIO194
    1 @ 2 L2 B26
    <27> HDA_SDIN0 AZ_SDIN0/GPIO167 SCL3_LV/GPIO195 FCH_SIC <5>
    R607 10K_0402_5% M2 E26
    AZ_SDIN1/GPIO168 SDA3_LV/GPIO196 FCH_SID <5>
    1 @ 2 HDA_SDIN0 M1 F25
    R608 10K_0402_5% AZ_SDIN2/GPIO169 EC_PWM0/EC_TIMER0/GPIO197
    M4 E22
    HDA_SDOUT AZ_SDIN3/GPIO170 EC_PWM1/EC_TIMER1/GPIO198
    1 2 <27> HDA_SYNC_AUDIO
    R589 1 2 33_0402_5% HDA_SYNC N2 F22 EC_PWM2
    EC_PWM2 <17>
    AZ_SYNC EC_PWM2/EC_TIMER2/GPIO199
    R609 10K_0402_5%
    <27> HDA_RST_AUDIO#
    R590 1 2 33_0402_5% HDA_RST# P2 E21 EC_PWM3
    EC_PWM3 <17>
    AZ_RST_L EC_PWM3/EC_TIMER3/GPIO200
    Pull-down for enable high performance mode
    20100527 (required for M1) G24
    R5911 KSI_0/GPIO201
    2 10K_0402_5% T1
    GBE_COL KSI_1/GPIO202
    G25
    R5921 2 10K_0402_5% T4 E28
    GBE_CRS KSI_2/GPIO203

    EMBEDDED CTRL
    L6 E29
    R593 GBE_MDCK KSI_3/GPIO204
    +3VALW 1 2 10K_0402_5% L5 D29
    3 GBE_MDIO KSI_4/GPIO205 3
    T9 D28
    +3VALW +3VALW +3VALW GBE_RXCLK KSI_5/GPIO206

    GBE LAN
    U1 C29
    GBE_RXD3 KSI_6/GPIO207
    U3 C28
    GBE_RXD2 KSI_7/GPIO208
    T2
    GBE_RXD1
    U2 B28
    GBE_RXD0 KSO_0/GPIO209
    1

    PX@ VGA@ T5 A27


    R912 R911 R910 R596 GBE_RXCTL/RXDV KSO_1/GPIO210
    1 2 10K_0402_5% V5 B27
    10K_0402_5% 10K_0402_5% GBE_RXERR KSO_2/GPIO211
    P5 D26
    10K_0402_5% GBE_TXCLK KSO_3/GPIO212
    M5 A26
    GBE_TXD3 KSO_4/GPIO213
    P9 C26
    2

    GBE_TXD2 KSO_5/GPIO214
    T7 A24
    GBE_TXD1 KSO_6/GPIO215
    P7 B25
    GPIO189 GBE_TXD0 KSO_7/GPIO216
    M7 A25
    GPIO190 GBE_TXCTL/TXEN KSO_8/GPIO217
    P4 D24
    GPIO191 GBE_PHY_PD KSO_9/GPIO218
    M9 B24
    R600 GBE_PHY_RST_L KSO_10/GPIO219
    +3VALW 1 2 10K_0402_5% V7 C24
    GBE_PHY_INTR KSO_11/GPIO220
    B23
    KSO_12/GPIO221
    1

    BACO@ WOPX@ WOVGA@ GPIO187 E23 A23


    T85 PAD PS2_DAT/SDA4/GPIO187 KSO_13/GPIO222
    R915 R914 R913 GPIO188 E24 D22
    T86 PAD PS2_CLK/SCL4/GPIO188 KSO_14/GPIO223
    10K_0402_5% 10K_0402_5% F21 C22
    10K_0402_5% SPI_CS2_L/GBE_STAT2/GPIO166 KSO_15/GPIO224
    G29 A22
    FC_RST_L/GPO160 KSO_16/GPIO225
    B22
    2

    GPIO189 KSO_17/GPIO226
    D27
    GPIO190 PS2KB_DAT/GPIO189
    F28
    GPIO191 PS2KB_CLK/GPIO190
    F29
    PS2M_DAT/GPIO191
    E27
    PS2M_CLK/GPIO192
    21807-A11-HUDSON-M1_FCBGA605

    SKU_ID SKU_ID : 1->VGA*


    4 0->UMA 4
    (GPIO189) GPIO 189 190 191

    PX_FN PX_Function : 1->PX Enable* UMA 0 0 1


    0->PX Disable DISO 1 0 1
    (GPIO190) PX3.0 1 1 1
    PX4.0 1 1 0
    PX_SEL PX_SEL : 1->PX 3.0*

    (GPIO191)
    0->PX 4.0 Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    FCH HDA/USB/ACPI
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 14 of 46
    A B C D E
    A B C D E

    1 1

    U31B
    C656 1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_P0 AH9 AH28
    <30> SATA_ITX_DRX_P0 SATA_ITX_C_DRX_N0 AJ9 SATA_TX0P FC_CLK
    C658 1 2 0.01U_0402_16V7K AG28
    <30> SATA_ITX_DRX_N0 SATA_TX0N FC_FBCLKOUT
    HDD FC_FBCLKIN AF26
    <30> SATA_DTX_C_IRX_N0 AJ8 SATA_RX0N
    <30> SATA_DTX_C_IRX_P0 AH8 SATA_RX0P FC_OE_L/GPIOD145 AF28
    FC_AVD_L/GPIOD146 AG29
    C648 1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_P1 AH10 AG26
    <30> SATA_ITX_DRX_P1 SATA_ITX_C_DRX_N1 AJ10 SATA_TX1P FC_WE_L/GPIOD148
    C649 1 2 0.01U_0402_16V7K AF27
    <30> SATA_ITX_DRX_N1 SATA_TX1N FC_CE1_L/GPIOD149
    ODD FC_CE2_L/GPIOD150 AE29
    <30> SATA_DTX_C_IRX_N1 AG10 SATA_RX1N FC_INT1/GPIOD144 AF29
    <30> SATA_DTX_C_IRX_P1 AF10 SATA_RX1P FC_INT2/GPIOD147 AH27

    GPIOD
    AG12 SATA_TX2P FC_ADQ0/GPIOD128 AJ27
    AF12 SATA_TX2N FC_ADQ1/GPIOD129 AJ26
    FC_ADQ2/GPIOD130 AH25
    AJ12 SATA_RX2N FC_ADQ3/GPIOD131 AH24

    SERIAL ATA
    2 2
    AH12 SATA_RX2P FC_ADQ4/GPIOD132 AG23
    FC_ADQ5/GPIOD133 AH23
    AH14 SATA_TX3P FC_ADQ6/GPIOD134 AJ22
    AJ14 SATA_TX3N FC_ADQ7/GPIOD135 AG21
    FC_ADQ8/GPIOD136 AF21
    AG14 SATA_RX3N FC_ADQ9/GPIOD137 AH22
    AF14 SATA_RX3P FC_ADQ10/GPIOD138 AJ23
    AF23
    FC_ADQ11/GPIOD139
    AG17 AJ24
    SATA_TX4P FC_ADQ12/GPIOD140
    AF17 AJ25
    SATA_TX4N FC_ADQ13/GPIOD141
    AG25
    FC_ADQ14/GPIOD142
    AJ17 AH26
    SATA_RX4N FC_ADQ15/GPIOD143
    AH17
    SATA_RX4P
    AJ18
    SATA_TX5P

    HW MONITOR
    AH18 W5
    SATA_TX5N FANOUT0/GPIO52 ODD_PWR
    W6 ODD_PWR <30>
    FANOUT1/GPIO53
    AH19 Y9
    SATA_RX5N FANOUT2/GPIO54
    AJ19
    SATA_RX5P
    10 mils and < 1" FANIN0/GPIO56
    W7
    V9
    R610 SATA_CALRP FANIN1/GPIO57
    1 2 1K_0402_1% AB14
    SATA_CALRP FANIN2/GPIO58
    W8
    +AVDD_SATA R611 1 2 931_0402_1% SATA_CALRN AA14
    SATA_CALRN TEMPIN0 R612 2 10K_0402_5%
    B6 1
    TEMPIN0/GPIO171 TEMPIN1 R613 2 10K_0402_5%
    A6 1
    TEMPIN1/GPIO172 TEMPIN2 R614 2 10K_0402_5%
    <32> SATA_LED# AD11 A5 1
    SATA_ACT_L/GPIO67 TEMPIN2/GPIO173 R615 2 10K_0402_5%
    B5 1
    R616 1 TEMPIN3/TALERT_L/GPIO174
    +3VS 2 10K_0402_5% TEMP_COMM
    C7

    A3 GPIO175 R617 2 1 10K_0402_5%


    25M_SATA_X1 AD16 VIN0/GPIO175 GPIO176 R618 10K_0402_5%
    1 2 SATA_X1 VIN1/GPIO176
    B4 2 1
    A4 GPIO177 R619 2 1 10K_0402_5%
    VIN2/GPIO177
    1

    3 GPIO178 3
    @ C107 @ VIN3/GPIO178
    C5 R620 2 1 10K_0402_5%
    22P_0402_50V8J 1M_0603_5% A7 GPIO179 R621 2 1 10K_0402_5% VIN6/GBE_STAT3/GPIO181
    Y7 R861 VIN4/GPIO179 GPIO180 R622 10K_0402_5%
    B7 2 1 Enable integrated pull-down/up and leave unconnected
    VIN5/GPIO180 GPIO181
    @ C106 @ B8 R623 2 @ 1 10K_0402_5%
    2

    22P_0402_50V8J 25M_SATA_X2 AC16 VIN6/GBE_STAT3/GPIO181 GPIO182 R624 10K_0402_5%


    A8 2 1
    SATA_X2 VIN7/GBE_LED3/GPIO182
    1 2
    25MHZ_20PF_7A25000012
    SPI ROM

    FCH_SI_SPI_SO J5 G27
    FCH_SO_SPI_SI SPI_DI/GPIO164 NC1
    E2 Y2
    FCH_SPICLK SPI_DO/GPIO163 NC2
    K4
    FCH_SPICS#/FSEL# SPI_CLK/GPIO162
    K9
    SPI_CS1_L/GPIO165
    T78PAD G2
    ROM_RST_L/GPIO161
    21807-A11-HUDSON-M1_FCBGA605

    @
    +3VS 1 @ 2 C784 1 2 0.1U_0402_16V4Z
    R504 0_0603_5%

    FCH_+SPI_VCC

    U32
    FCH_SPICS#/FSEL# 1 8
    FCH_SPI_WP# CS# VCC FCH_SPICLK_R
    R507 1 @ 2 4.7K_0402_5% 3
    WP# SCLK
    6 R510 1 @ 2 0_0402_5% FCH_SPICLK
    R491 1 @ 2 4.7K_0402_5% FCH_SPI_HOLD# 7 5 FCH_SO_SPI_SI
    4 +3VS HOLD# SI 4
    4 2 FCH_SI_SPI_SO
    GND SO
    MX25L1605DM2I-12G SOP 8P
    SA00002TO00
    @

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    FCH-SATA/SPI
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 15 of 46
    A B C D E
    A B C D E

    Change 0603 size


    +3VS For DVT 42mA U31C POWER 979.4mA

    10U_0603_6.3V6M
    0.1U_0402_16V7K

    0.1U_0402_16V7K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    AH1 VDDIO_33_PCIGP_1 VDDCR_11_1 N13 +1.1VS +1.1VS

    CORE S0
    10U_0603_6.3V6M

    10U_0603_6.3V6M

    0.1U_0402_16V7K

    0.1U_0402_16V7K

    0.1U_0402_16V7K
    2 2 2 2 2 V6 VDDIO_33_PCIGP_2 VDDCR_11_2 R15 1 1 1 1 1

    PCI/GPIO I/O
    C121

    C113

    C114

    C115

    C116

    C738

    C70

    C117

    C118

    C71
    Y19 VDDIO_33_PCIGP_3 VDDCR_11_3 N17
    AE5 VDDIO_33_PCIGP_4 VDDCR_11_4 U13
    AC21 VDDIO_33_PCIGP_5 VDDCR_11_5 U17
    1 1 1 1 1 2 2 2 2 2

    330U_D2_2.5VY_R9M
    AA2 VDDIO_33_PCIGP_6 VDDCR_11_6 V12

    10U_0603_6.3V6M
    AB4 VDDIO_33_PCIGP_7 VDDCR_11_7 V18 1
    AC8 W12 VGA@ 1
    VDDIO_33_PCIGP_8 VDDCR_11_8

    C119

    C68
    AA7 W18 +
    VDDIO_33_PCIGP_9 VDDCR_11_9
    AA9
    VDDIO_33_PCIGP_10
    GPIO I/F implemented: tied to +1.8V_S0 AF7
    VDDIO_33_PCIGP_11 382.9mA 2 2

    CLKGEN I/O
    1 GPIO I/F not implemented: tied to +VDDAN_11_CLK L43 2 1
    AA19 K28 1 +1.1VS
    +1.8VS VDDIO_33_PCIGP_12 VDDAN_11_CLK_1

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    0.1U_0402_16V7K

    0.1U_0402_16V7K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    R632 +1.8V_S0 or 0 ohm to ground K29 1 1 1 1 1 1
    VDDAN_11_CLK_2

    C72

    C73

    C74

    C75

    C743

    C109
    1 @ 2 +VDDIO_18_FC J28 FBMA-L11-201209-221LMA30T_0805
    0_0603_5% VDDAN_11_CLK_3
    0.16mA VDDAN_11_CLK_4
    K26
    1

    0_0402_5%

    FLASH I/O
    0.1U_0402_16V7K

    0.1U_0402_16V7K
    4.7U_0603_6.3V6K
    2 2 2 J21
    VDDAN_11_CLK_5 2 2 2 2 2 2
    R633

    C744

    C69

    C746
    AF22
    VDDIO_18_FC_1 VDDAN_11_CLK_6
    J20 Add VGA@
    AE25 K21
    @ @ @ VDDIO_18_FC_2 VDDAN_11_CLK_7 For DVT
    AF24 J22
    1 1 1 VDDIO_18_FC_3 VDDAN_11_CLK_8
    AC22
    2

    VDDIO_18_FC_4
    Change 0603 size
    For DVT 1011 VDDRF_GBE_S
    V1
    For DVT
    22.5mA VDDIO_33_GBE_S M10

    2.2U_0603_6.3V6K
    L44

    PCI EXPRESS
    +3VS 2 1 +VDDPL33_PCIE AE28
    FBMA-L11-160808-221LMT_2P VDDPL_33_PCIE
    1

    GBE LAN
    C76
    1115.6mA
    U26 VDDAN_11_PCIE_1 VDDCR_11_GBE_S_1 L7
    V22 VDDAN_11_PCIE_2 VDDCR_11_GBE_S_2 L9
    2
    V26 VDDAN_11_PCIE_3
    +1.1VS L45 +PCIE_VDDAN V27 VDDAN_11_PCIE_4 +3VALW
    10U_0603_6.3V6M

    10U_0603_6.3V6M

    0.1U_0402_16V7K

    0.1U_0402_16V7K
    2 1 V28 VDDAN_11_PCIE_5 VDDIO_GBE_S_1 M6
    1U_0402_6.3V6K

    FBMA-L11-201209-221LMA30T_0805 V29 P8 @
    VDDAN_11_PCIE_6 VDDIO_GBE_S_2 U85
    1 1 1 2 2 W22 VDDAN_11_PCIE_7 +VDDCR_11_USB @
    C105

    C77

    C78

    C79

    C80

    W26 VDDAN_11_PCIE_8 VIN 1


    L107
    15.5mA 2 1 5 1U_0402_6.3V6K
    2 2 2 1 1 VOUT

    2.2U_0603_6.3V6K

    2.2U_0603_6.3V6K
    FBMA-L11-160808-221LMT 0603 2 1 2
    GND

    SERIAL ATA

    3.3V_S5 I/O
    +VDDPL_33_SATA AD14 49.5mA
    VDDPL_33_SATA C989
    Change 0603 size +AVDD_SATA VDDIO_33_S_1 A21 +3VALW 4 FB
    AJ20 D21 1 1 3 @
    For DVT VDDAN_11_SATA_1 VDDIO_33_S_2 EN

    C81

    C82
    AF18 VDDAN_11_SATA_4 VDDIO_33_S_3 B21
    2 2
    1345.2mA AH20 VDDAN_11_SATA_2 VDDIO_33_S_4 K10
    AG19 L10 APL5317
    VDDAN_11_SATA_3 VDDIO_33_S_5 2 2
    AE18 VDDAN_11_SATA_5 VDDIO_33_S_6 J9
    AD18 VDDAN_11_SATA_6 VDDIO_33_S_7 T6
    AE16 VDDAN_11_SATA_7 VDDIO_33_S_8 T8
    Reserve

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    +1.1VALW
    1 1

    CORE S5

    C83

    C84
    L46 F26 165.2mA
    +AVDD_USB VDDCR_11_S_1
    +3VALW 2 1 A18 G26
    VDDAN_33_USB_S_1 VDDCR_11_S_2
    A19
    VDDAN_33_USB_S_2 15.3mA 2 2
    10U_0603_6.3V6M

    10U_0603_6.3V6M

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    0.1U_0402_16V7K

    FBMA-L11-201209-221LMA30T_0805 534.5mA A20 M8 +VDDIO_AZ


    VDDAN_33_USB_S_3 VDDIO_AZ_S
    1 1 1 1 1 B18
    VDDAN_33_USB_S_4 58mA

    USB I/O

    10U_0603_6.3V6M
    C85

    C86

    C87

    C88

    C89

    0.1U_0402_16V7K

    0.1U_0402_16V7K
    B19 A11 L47
    VDDAN_33_USB_S_5 VDDCR_11_USB_S_1 +VDDCR_11_USB
    B20 B11 2 1 +1.1VALW
    VDDAN_33_USB_S_6 VDDCR_11_USB_S_2 FBMA-L11-201209-221LMA30T_0805
    C18 1 1 1
    2 2 2 2 2 VDDAN_33_USB_S_7

    C90

    C91

    C92
    C20
    VDDAN_33_USB_S_8 46.5mA
    D18 M21 +VDDPL33
    VDDAN_33_USB_S_9 VDDPL_33_SYS
    D19
    VDDAN_33_USB_S_10 65.3mA 2 2 2

    PLL
    D20 L22 +VDDPL11
    VDDAN_33_USB_S_11 VDDPL_11_SYS_S
    E19
    VDDAN_33_USB_S_12 16.1mA
    F19 +AVDD_USB
    L48 VDDPL_33_USB_S
    11.4mA
    0.1U_0402_16V7K
    2.2U_0603_6.3V6K

    2 1 +VDDAN_11_USB C11 D6
    +1.1VALW VDDAN_11_USB_S_1 VDDAN_33_HWM_S +VDDAN33_HWM
    D11 L49
    FBMA-L11-160808-221LMT_2P VDDAN_11_USB_S_2 +VDDXL_33_S
    1 2 88.6mA VDDXL_33_S
    L20 2 1 +3VS
    C93

    C94

    2.2U_0603_6.3V6K
    5mA 1

    C95
    21807-A11-HUDSON-M1_FCBGA605 FBMA-L11-160808-221LMT_2P
    2 1
    2

    3 3

    +AVDD_SATA +VDDIO_AZ +3VALW


    +VDDPL_33_SATA L50
    10U_0603_6.3V6M

    10U_0603_6.3V6M

    0.1U_0402_16V7K

    0.1U_0402_16V7K

    L51 +1.1VS 2 1 1 @ 2
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    +3VS 2 1 FBMA-L11-201209-221LMA30T_0805 R634 0_0603_5%


    FBMA-L11-160808-221LMT_2P 1 1 1 1 1 1 1 2 +3VS
    C108

    C96

    C97

    C778

    C775

    C776

    R635 0_0603_5% For DVT 1011


    1
    C777 1 2 2.2U_0603_6.3V6K
    2 2 2 2 2 2 C98
    2.2U_0603_6.3V6K
    2

    +VDDPL11 Change 0603 size +VDDAN33_HWM For 3V AZ device


    L52 L53 For DVT
    +1.1VALW 2 1 +3VALW 2 1
    FBMA-L11-160808-221LMT_2P FBMA-L11-160808-221LMT_2P
    0.1U_0402_16V7K
    2.2U_0603_6.3V6K

    C99 1 2 2.2U_0603_6.3V6K
    4
    1 2
    C100

    C782

    2 1

    +VDDPL33
    L55
    +3VS 2 1
    FBMA-L11-160808-221LMT_2P Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title
    C120 1 2 2.2U_0603_6.3V6K
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    FCH PWR
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 16 of 46
    A B C D E
    5 4 3 2 1

    U31D
    Y14
    Y16
    VSSIO_SATA_1
    VSSIO_SATA_2
    VSS_1
    VSS_2
    AJ2
    A28
    REQUIRED STRAPS Check Internal PU/PD
    AB16 VSSIO_SATA_3 VSS_3 A2
    AC14 VSSIO_SATA_4 VSS_4 E5
    AE12 VSSIO_SATA_5 VSS_5 D23 PCI_CLK2 PCI_CLK1 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 RTC_CLK EC_PWM2 EC_PWM3
    AE14 VSSIO_SATA_6 VSS_6 E25
    AF9 VSSIO_SATA_7 VSS_7 E6
    AF11 VSSIO_SATA_8 VSS_8 F24 PULL WATCHDOG ALLOW PCIE USE NON Fusion internal EC Internal S5 PLUS LPC ROM (H.L)
    AF13 N15 TIMER GEN2 DEBUG CLOCK ENABLE CLKGEN MODE
    D
    AF16
    VSSIO_SATA_9 VSS_9
    R13
    HIGH D
    VSSIO_SATA_10 VSS_10 ENABLE STRAP Mode Mode DISABLED DEFAULT
    AG8 VSSIO_SATA_11 VSS_11 R17
    AH7 T10 DEFAULT DEFAULT
    VSSIO_SATA_12 VSS_12 DEFAULT
    AH11 VSSIO_SATA_13 VSS_13 P10
    AH13 VSSIO_SATA_14 VSS_14 V11 IGNORE Fusion
    AH16 VSSIO_SATA_15 VSS_15 U15 PULL WATCHDOG FORCE PCIE DEBUG CLOCK internal EC External S5 PLUS SPI ROM(L,H)
    AJ7 M18 TIMER GEN1 DISABLE CLKGEN MODE
    AJ11
    VSSIO_SATA_16 VSS_16
    V19
    LOW STRAP Mode
    VSSIO_SATA_17 VSS_17 DISABLE Mode ENABLED
    AJ13 VSSIO_SATA_18 VSS_18 M11
    AJ16 L12 DEFAULT
    VSSIO_SATA_19 VSS_19

    GND
    L18 DEFAULT DEFAULT DEFAULT
    VSS_20
    A9 VSSIO_USB_1 VSS_21 J7
    B10 VSSIO_USB_2 VSS_22 P3
    K11 VSSIO_USB_3 VSS_23 V4
    B9 VSSIO_USB_4 VSS_24 AD6
    D10 AD4 +3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW +3VALW
    VSSIO_USB_5 VSS_25
    D12 VSSIO_USB_6 VSS_26 AB7
    D14 VSSIO_USB_7 VSS_27 AC9
    D17 VSSIO_USB_8 VSS_28 V8

    1
    E9 VSSIO_USB_9 VSS_29 W9
    F9 W10 R649 R636 R637 R638 R639 R166 R594 R550 R551
    VSSIO_USB_10 VSS_30 @ @ @ @ @
    F12 VSSIO_USB_11 VSS_31 AJ28
    F14 B29 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
    VSSIO_USB_12 VSS_32 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
    F16 U4

    2
    C VSSIO_USB_13 VSS_33 C
    C9 VSSIO_USB_14 VSS_34 Y18
    G11 VSSIO_USB_15 VSS_35 Y10
    F18 VSSIO_USB_16 VSS_36 Y12
    D9 VSSIO_USB_17 VSS_37 Y11 <13> PCI_CLK2
    H12 VSSIO_USB_18 VSS_38 AA11 <13> PCI_CLK1
    H14 VSSIO_USB_19 VSS_39 AA12 <13> PCI_CLK3
    H16 VSSIO_USB_20 VSS_40 G4 <13> PCI_CLK4
    H18 VSSIO_USB_21 VSS_41 J4 <13> LPC_CLK0
    J11 VSSIO_USB_22 VSS_42 G8 <13> LPC_CLK1
    J19 VSSIO_USB_23 VSS_43 G9 <14> EC_PWM2
    K12 VSSIO_USB_24 VSS_44 M12 <14> EC_PWM3
    K14 VSSIO_USB_25 VSS_45 AF25 <13,31> RTC_CLK
    K16 VSSIO_USB_26 VSS_46 H7
    K18 VSSIO_USB_27 VSS_47 AH29
    H19 VSSIO_USB_28 VSS_48 V10

    1
    VSS_49 P6
    N4 R650 R640 R641 R642 R643 R167 R601 R602 R625
    VSS_50 @ @ @ @
    Y4 EFUSE VSS_51 L4
    L8 10K_0402_5% 10K_0402_5% 10K_0402_5% 2.2K_0402_5%
    VSS_52 10K_0402_5% 10K_0402_5% 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
    D8

    2
    VSSAN_HWM
    M19 VSSXL VSSPL_SYS M20

    B B
    P21 H23
    P20
    M22
    VSSIO_PCIECLK_1
    VSSIO_PCIECLK_2
    VSSIO_PCIECLK_3
    VSSIO_PCIECLK_14
    VSSIO_PCIECLK_15
    VSSIO_PCIECLK_16
    H26
    AA21
    DEBUG STRAPS
    M24
    M26
    VSSIO_PCIECLK_4 VSSIO_PCIECLK_17 AA23
    AB23
    FCH M1 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
    VSSIO_PCIECLK_5 VSSIO_PCIECLK_18
    P22 VSSIO_PCIECLK_6 VSSIO_PCIECLK_19 AD23 PCI_AD23
    P24 VSSIO_PCIECLK_7 VSSIO_PCIECLK_20 AA26 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 Enable ROM Straps
    P26 VSSIO_PCIECLK_8 VSSIO_PCIECLK_21 AC26
    T20 VSSIO_PCIECLK_9 VSSIO_PCIECLK_22 Y20 USE internal <13> PCI_AD27
    T22 VSSIO_PCIECLK_10 VSSIO_PCIECLK_23 W21 PLL generated ILA AUTORUN Selects Disable I2C Required Setting <13> PCI_AD26
    T24 VSSIO_PCIECLK_11 VSSIO_PCIECLK_24 W20 PULL Disabled FC PLL ROM <13> PCI_AD25
    V20 AE26 PLL CLK
    J23
    VSSIO_PCIECLK_12 VSSIO_PCIECLK_25
    L21
    HIGH <13> PCI_AD24
    VSSIO_PCIECLK_13 VSSIO_PCIECLK_26 <13> PCI_AD23
    K20 DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
    VSSIO_PCIECLK_27

    1
    21807-A11-HUDSON-M1_FCBGA605
    PULL BYPASS ILA FC PLL Getting Value R644 R645 R646 R647 R648
    Reserved @ @ @ @ @
    LOW PCI PLL AUTORUN bypassed from I2C EPROM 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
    Enabled 2.2K_0402_5% 2.2K_0402_5%

    2
    A Check AD29,AD28 strap function check default A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    FCH-VSS/Strap
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 17 of 46
    5 4 3 2 1
    5 4 3 2 1

    GFX PCIE LANE REVERSAL add for VB support.


    D U2G R1 D
    U2A 10K_0402_5%
    PCIE_FTX_C_GRX_P[0..3] PCIE_GTX_C_FRX_P[0..3] 1 2
    <6> PCIE_FTX_C_GRX_P[0..3] PCIE_GTX_C_FRX_P[0..3] <6> VGA@
    PCIE_FTX_C_GRX_N[0..3] PCIE_GTX_C_FRX_N[0..3] LVDS CONTROL AK27
    <6> PCIE_FTX_C_GRX_N[0..3] PCIE_GTX_C_FRX_N[0..3] <6> VARY_BL VGA_INVT_PWM <10>
    AJ27 VGA_ENVDD <10>
    DIGON R2
    1 2
    PCIE_FTX_C_GRX_P0 AA38 Y33 PCIE_GTX_FRX_P0 C1 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P0 10K_0402_5%
    PCIE_FTX_C_GRX_N0 PCIE_RX0P PCIE_TX0P PCIE_GTX_FRX_N0 C2 0.1U_0402_16V7K PCIE_GTX_C_FRX_N0 VGA@
    Y37 Y32 1 2
    PCIE_RX0N PCIE_TX0N
    VGA@ AK35
    TXCLK_UP_DPF3P
    VGA@ TXCLK_UN_DPF3N AL36
    PCIE_FTX_C_GRX_P1 Y35 W33 PCIE_GTX_FRX_P1 C3 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P1
    PCIE_FTX_C_GRX_N1 PCIE_RX1P PCIE_TX1P PCIE_GTX_FRX_N1 C4 0.1U_0402_16V7K PCIE_GTX_C_FRX_N1
    W36 PCIE_RX1N PCIE_TX1N W32 1 2
    TXOUT_U0P_DPF2P AJ38
    VGA@ TXOUT_U0N_DPF2N AK37
    VGA@
    PCIE_FTX_C_GRX_P2 W38 U33 PCIE_GTX_FRX_P2 C5 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P2 AH35
    PCIE_FTX_C_GRX_N2 PCIE_RX2P PCIE_TX2P PCIE_GTX_FRX_N2 C6 0.1U_0402_16V7K PCIE_GTX_C_FRX_N2 TXOUT_U1P_DPF1P
    V37 PCIE_RX2N PCIE_TX2N U32 1 2 TXOUT_U1N_DPF1N AJ36
    VGA@
    VGA@ TXOUT_U2P_DPF0P AG38
    PCIE_FTX_C_GRX_P3 V35 U30 PCIE_GTX_FRX_P3 C7 1 2 0.1U_0402_16V7K PCIE_GTX_C_FRX_P3 AH37
    PCIE_FTX_C_GRX_N3 PCIE_RX3P PCIE_TX3P PCIE_GTX_FRX_N3 C8 0.1U_0402_16V7K PCIE_GTX_C_FRX_N3 TXOUT_U2N_DPF0N
    U36 PCIE_RX3N PCIE_TX3N U29 1 2
    VGA@ TXOUT_U3P AF35
    VGA@ TXOUT_U3N AG36
    U38 PCIE_RX4P PCIE_TX4P T33
    T37 PCIE_RX4N PCIE_TX4N T32

    PCI EXPRESS INTERFACE


    LVTMDP

    T35 T30 AP34 VGA_TXCLK+


    PCIE_RX5P PCIE_TX5P TXCLK_LP_DPE3P VGA_TXCLK- VGA_TXCLK+ <10>
    R36 PCIE_RX5N PCIE_TX5N T29 TXCLK_LN_DPE3N AR34 VGA_TXCLK- <10>
    AW37 VGA_TXOUT0+
    C TXOUT_L0P_DPE2P VGA_TXOUT0- VGA_TXOUT0+ <10> C
    R38 PCIE_RX6P PCIE_TX6P P33 TXOUT_L0N_DPE2N AU35 VGA_TXOUT0- <10>
    P37 PCIE_RX6N PCIE_TX6N P32
    AR37 VGA_TXOUT1+
    TXOUT_L1P_DPE1P VGA_TXOUT1- VGA_TXOUT1+ <10>
    TXOUT_L1N_DPE1N AU39 VGA_TXOUT1- <10>
    P35 PCIE_RX7P PCIE_TX7P P30
    N36 P29 AP35 VGA_TXOUT2+
    PCIE_RX7N PCIE_TX7N TXOUT_L2P_DPE0P VGA_TXOUT2- VGA_TXOUT2+ <10>
    TXOUT_L2N_DPE0N AR35 VGA_TXOUT2- <10>
    N38 N33 AN36
    PCIE_RX8P PCIE_TX8P TXOUT_L3P
    M37 N32 AP37
    PCIE_RX8N PCIE_TX8N TXOUT_L3N

    M35 N30
    PCIE_RX9P PCIE_TX9P
    L36 N29
    PCIE_RX9N PCIE_TX9N
    2160809000A11SEYMOU_FCBGA962
    L38 L33
    PCIE_RX10P PCIE_TX10P
    K37 L32 Seymour@
    PCIE_RX10N PCIE_TX10N

    K35 L30
    PCIE_RX11P PCIE_TX11P
    J36 L29
    PCIE_RX11N PCIE_TX11N

    J38 K33
    PCIE_RX12P PCIE_TX12P
    H37 K32
    PCIE_RX12N PCIE_TX12N

    H35 J33
    PCIE_RX13P PCIE_TX13P
    G36 J32
    PCIE_RX13N PCIE_TX13N

    B B
    G38 K30
    PCIE_RX14P PCIE_TX14P
    F37 K29
    PCIE_RX14N PCIE_TX14N

    F35 H33
    PCIE_RX15P PCIE_TX15P
    E37 H32
    PCIE_RX15N PCIE_TX15N
    +3VSG

    CLOCK
    <13> CLK_PCIE_VGA AB35
    PCIE_REFCLKP
    <13> CLK_PCIE_VGA# AA36
    PCIE_REFCLKN

    1
    AH16 R394
    CALIBRATION 2.2K_0402_5%
    Accessiable for "Test Purposes"
    Y30 1 VGA@ 2 @ U16
    Connect to GND for "Normal Operation" PCIE_CALRP

    5
    R3 1.27K_0402_1% PX@

    2
    2 VGA@ 1 AH16 Y29 1 VGA@ 2 2

    P
    +1.0VSG <13> PE_GPIO0
    R5 10K_0402_5% PWRGOOD PCIE_CALRN R6 2K_0402_1% B
    4 VGA_RST#
    Y
    <13,26,29> PLT_RST# 1
    A

    G
    VGA_RST# AA30
    PERSTB

    3
    NC7SZ08P5X_NL_SC70-5
    2160809000A11SEYMOU_FCBGA962
    1 DISO@ 2
    Seymour@ R159 0_0402_5%

    Seymour XT P/N: SA000047H10 (S IC 216-0809000 A11 SEYMOUR XT M2)


    Robson XT P/N: SA00004DR20 (S IC 216-0774211 A11 Robson XT M2 )
    A A

    U2 Robson@

    Robson XT-M2 A11 Security Classification Compal Secret Data Compal Electronics, Inc.
    Robson A11 (SA00004DR20) Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Vancouver_ PCIE / LVDS
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 18 of 46
    5 4 3 2 1
    5 4 3 2 1

    U2B

    Strap Name Pin Straps description <all internal PD> Setting


    External VGA Thermal Sensor
    VIP Device Strap Enable indicates to the software driver Don't have this strap on
    VIP_DEVICE_EN V2SYNC 0: Driver would ignore the value sampled on VHAD_0 during reset 0 AU24 +3VSG
    Whistler and Seymour TXCAP_DPA3P VGA_HDMI_TXC+ <11>
    (GENLK_VSYNC) 1: VHAD_0 to determine whether or not a VIP slave device TXCAM_DPA3N
    AV23 VGA_HDMI_TXC- <11>
    VGA Disable determines TX0P_DPA2P
    AT25 VGA_HDMI_TXD0+ <11> 1

    0.1U_0402_16V4Z
    VGA_DIS GPIO9 0: VGA Controller capacity enabled 0 MUTI GFX AR24
    DPA TX0M_DPA2N VGA_HDMI_TXD0- <11>
    1: The device will not be recognized as the system’s VGA controller HDMI C10
    AU26 VGA@
    TX1P_DPA1P VGA_HDMI_TXD1+ <11> 2
    Transmitter Power Saving Enable TX1M_DPA1N
    AV25 VGA_HDMI_TXD1- <11>
    TX_PWRS_ENB GPIO0 0: 50% Tx output swing for mobile mode 1 NC on Park, U4 VGA@
    1: full Tx output swing (Default setting for Desktop) AR8 AT27 1 8 VGA_SMB_CK2
    Robson and Seymour NC_DVPCNTL_MVP_0 TX2P_DPA0P VGA_HDMI_TXD2+ <11> VDD SCLK
    AU8 AR26 VGA_HDMI_TXD2- <11>
    NC_DVPCNTL_MVP_1 TX2M_DPA0N GPU_THERM_D+ VGA_SMB_DA2
    PCI Express Transmitter De-emphasis Enable AP8
    NC_DVPCNTL_0
    2
    D+ SDATA
    7
    TX_DEEMPH_EN GPIO1 0: Tx de-emphasis diabled for mobile mode 1 NC on Park and Robson AW8 AR30 2200P_0402_50V7K
    NC_DVPCNTL_1 TXCBP_DPB3P VGA@ 1 THM_ALERT#
    D
    1: Tx de-emphasis enabled (Defailt setting for desktop) AR3
    NC_DVPCNTL_2 TXCBM_DPB3N
    AT29 2 3
    D- ALERT#
    6 2 1 D
    AR1 C11 R7
    VRAM_ID0 NC_DVPCLK GPU_THERM_D- 0_0402_5%
    GPIO13,12,11 (config 2,1,0) : memory apertures AU1
    DVPDATA_0 TX3P_DPB2P
    AV31 4
    THERM# GND
    5
    CONFIG[2] GPIO13 a) If BIOS_ROM_EN = 1, then Config[2:0] defines VRAM_ID1 AU3 AU30 1 2
    CONFIG[3:0] VRAM_ID2 DVPDATA_1 DPB TX3M_DPB2N VGA@ +3VSG
    CONFIG[1] GPIO12 the ROM type. AW3 R8 4.7K_0402_5%
    128 MB 000 VRAM_ID3 DVPDATA_2 ADM1032ARMZ-2REEL_MSOP8 VGA@
    CONFIG[0] GPIO11 001 AP6
    DVPDATA_3 TX4P_DPB1P
    AR32
    b) If BIOS_ROM_EN = 0, then Config[2:0] defines 256 MB 001 * AW5 AT31
    DVPDATA_4 TX4M_DPB1N
    the primary memory aperture size. 64 MB 010 AU5
    DVPDATA_5 Address 1001 101X b
    AR6 AT33
    DVPDATA_6 TX5P_DPB0P
    BIOS_ROM_EN GPIO22 Enable external BIOS ROM device AW6
    DVPDATA_7 TX5M_DPB0N
    AU32
    0: Diable, 1: Enable 0 AU6
    DVPDATA_8
    AT7 AU14 +3VSG
    DVPDATA_9 TXCCP_DPC3P
    00: No audio function; 10: Audio for DisplayPort only; AV7
    DVPDATA_10 TXCCM_DPC3N
    AV13
    AUD[1] HSYNC 11 AN7 +3VSG
    01: Audio for DisplayPort and HDMI if adapter is detected; DVPDATA_11
    AUD(0) VSYNC AV9
    DVPDATA_12 TX0P_DPC2P
    AT15
    11: Audio for both DisplayPort and HDMI

    2
    AT9 AR14
    DVPDATA_13 TX0M_DPC2N R9 R10
    0= Advertises the PCI-E device as 2.5 GT/s capable at power-on AR10
    DVPDATA_14
    BIF_GEN2_EN GPIO2 1= Advertises the PCI-E device as 5.0 GT/s capable at power-on 0 AW10 DPC AU16 4.7K_0402_5% 4.7K_0402_5%
    DVPDATA_15 TX1P_DPC1P

    5
    5.0 GT/s capability will be controlled by software AU10 AV15 VGA@ VGA@
    DVPDATA_16 TX1M_DPC1N
    AP10

    1
    NC_DVPDATA_17 VGA_SMB_CK2 EC_SMB_CK2
    H2SYNC Internal use only. THIS PAD HAS AN INTERNAL AV11
    NC_DVPDATA_18 TX2P_DPC0P
    AT17 4 3 EC_SMB_CK2 <5,31>
    RESERVED (GENLK_CLK) PULL-DOWN AND MUST BE 0 V AT RESET. The AT11
    NC_DVPDATA_19 TX2M_DPC0N
    AR16
    NC on Park, AR12 Q1B VGA@
    pad may be left unconnected NC_DVPDATA_20

    2
    GPIO8 DNI AW12 AU20 DMN66D0LDW-7_SOT363-6
    Robson and Seymour NC_DVPDATA_21 NC_TXCDP_DPD3P
    GPIO21 AU12
    NC_DVPDATA_22 NC_TXCDM_DPD3N
    AT19
    GENERICC AP12 VGA_SMB_DA2 1 6 EC_SMB_DA2
    NC_DVPDATA_23 EC_SMB_DA2 <5,31>
    GPIO5 AT21 VGA@
    NC_TX3P_DPD2P Q1A DMN66D0LDW-7_SOT363-6
    AJ21 AR20
    SWAPLOCKA NC_TX3M_DPD2N
    +3VSG +3VSG
    AK21
    SWAPLOCKB DPD
    NC on Park,
    AU22
    NC_TX4P_DPD1P Robson and Seymour
    AV21
    VGA@ R11 10K_0402_5% VGA_GPIO0 R12 NC_TX4M_DPD1N
    1 2 1 VGA@ 2 4.7K_0402_5%
    VGA@ R13 1 2 10K_0402_5% VGA_GPIO1 R14 1 VGA@ 2 4.7K_0402_5% I2C AT23
    @ R15 10K_0402_5% VGA_GPIO2 NC_TX5P_DPD0P
    1 2 AR22
    @ R16 10K_0402_5% SOUT_GPIO8 VGA_LCD_CLK NC_TX5M_DPD0N
    1 2 <10> VGA_LCD_CLK AK26
    @ R17 10K_0402_5% SIN_GPIO9 VGA_LCD_DAT SCL
    1 2
    VGA_GPIO11
    <10> VGA_LCD_DAT AJ26
    SDA Not share via for other GND
    VGA@ R18 1 2 10K_0402_5%
    @ R19 1 2 10K_0402_5% VGA_GPIO12 AD39
    GENERAL PURPOSE I/O R VGA_CRT_R <12>
    C @ R20 1 2 10K_0402_5% VGA_GPIO13 GPIO_0 will use to control AD37 C
    DISO@R21
    DISO@ R21 10K_0402_5% VGA_CRT_VSYNC VGA_GPIO0 RB
    1 2 PSI in the future product AH20
    DISO@R22
    DISO@ R22 10K_0402_5% VGA_CRT_HSYNC VGA_GPIO1 GPIO_0
    1 2 AH18 AE36 VGA_CRT_G <12>
    @ R23 10K_0402_5% GENERICC VGA_GPIO2 GPIO_1 G
    @ R24
    1 2
    10K_0402_5% V2SYNC
    change VGA@ as DISO@ AN16
    GPIO_2 GB
    AD35
    1 2 AH23
    @ R25 10K_0402_5% H2SYNC For PVT GPIO_3_SMBDATA
    1 2 AJ23 AF37 VGA_CRT_B <12>
    @ R26 10K_0402_5% BB_EN_GPIO21 VGA_GPIO5 GPIO_4_SMBCLK B
    1 2 AH17 AE38
    @ R27 10K_0402_5% ROMSE_GPIO22 GPIO_5_AC_BATT DAC1 BB
    1 2 AJ17
    @ R28 10K_0402_5% VGA_GPIO5 VGA_ENBKL GPIO_6
    1 2 <10> VGA_ENBKL AK17 AC36 VGA_CRT_HSYNC <12>
    SOUT_GPIO8 GPIO_7_BLON HSYNC
    AJ13 AC38 VGA_CRT_VSYNC <12>
    SIN_GPIO9 GPIO_8_ROMSO VSYNC
    2 1 AH15
    R29 VGA@ CLK_GPIO10 GPIO_9_ROMSI
    AJ16
    10K_0402_5% VGA_GPIO11 GPIO_10_ROMSCK R30
    AK16 AB34 1 VGA@ 2 499_0402_1% L78
    VGA_GPIO12 GPIO_11 RSET BLM18AG121SN1D_0603 +3VSG
    AL16
    GPIO_12 10mil

    0.1U_0402_16V4Z

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    VGA_GPIO13 70mA +AVDD
    Check option2 need to AM16
    GPIO_13 AVDD
    AD34 2 1 +1.8VSG

    1U_0402_6.3V4Z
    AM14 AE34 VGA@
    GPU_VID0 GPIO_14_HPD2 AVSSQ VGA_CRT_CLK
    Robson (XT)/Seymour(XT) be added or not? <43> GPU_VID0
    T1
    AM13
    GPIO_15_PWRCNTL_0 +VDD1DI
    10mil 120ohm/0.3A VGA_CRT_DATA
    VGA@ R33
    VGA@ R34
    1 2 10K_0402_5%
    AK14 45mA AC33 1 1 1 1 1 2 10K_0402_5%
    GPIO_16 VDD1DI

    C12

    C13

    C14

    C52
    THM_ALERT# AG30 AC34 Change 0603 size
    GPIO_17_THERMAL_INT VSS1DI VGA_CRT_R VGA@ R35
    Location VRAM_ID3 VRAM_ID2 VRAM_ID1 VRAM_ID0 AN14 1 2 150_0402_1%
    GPIO_18_HPD3 For DVT VGA_CRT_G VGA@ R36
    VRAM AM17 1 2 150_0402_1%
    <vendor1> <pcs> 64MX16 <vendor2> <size> GPU_VID1 GPIO_19_CTF 2 2 2 2 VGA_CRT_B VGA@ R37
    <43> GPU_VID1 AL13 AC30 1 2 150_0402_1%
    BB_EN_GPIO21 GPIO_20_PWRCNTL_1 R2/NC VGA@ VGA@ VGA@ VGA@
    Samsung AJ14
    GPIO_21_BB_EN R2B/NC
    AC31
    SA00004GS10 G-die 0 0 1 1 ROMSE_GPIO22 AK13 L79 BLM18AG121SN1D_0603
    GPIO_22_ROMCSB

    0.1U_0402_16V4Z

    10U_0603_6.3V6M
    K4W1G1646G-BC11 T2 AN13 AD30 2 1 +1.8VSG
    GPIO_23_CLKREQB G2/NC

    1U_0402_6.3V4Z
    <4 pcs> T3 AM23 AD31 VGA@
    T4 JTAG_TRSTB G2B/NC
    Hynix AN23
    JTAG_TDI 120ohm/0.3A
    SA000032420 Orion-die 1 1 0 0 T5 AK23 AF30 1 1 1 NC on Whistler and Seymour
    JTAG_TCK B2/NC

    C15

    C16

    C17
    H5TQ1G63BFR-12C T6 AL24 AF31
    <4 pcs> T7 JTAG_TMS B2B/NC
    AM24
    JTAG_TDO
    Hynix AJ19
    GENERICA
    SA000041S40 Vega-die 2 2 2
    1 1 1 0 AK19
    GENERICB C/NC
    AC32
    H5TQ1G63DFR-11C GENERICC AJ20 AD32 VGA@ VGA@ VGA@
    <4 pcs> GENERICC Y/NC
    AK20 AF32
    GENERICD COMP/NC
    AJ24
    GENERICE_HPD4

    0.1U_0402_16V4Z

    10U_0603_6.3V6M
    DAC2
    AH26
    NC_GENERICF_HPD5 +3VSG In Whistler and Seymour, change to

    1U_0402_6.3V4Z
    +1.8VSG NC on Park AH24 AD29 H2SYNC
    NC_GENERICG_HPD6 H2SYNC/GENLK_CLK V2SYNC GENLK_CLK, GENLK_VSYNC for
    AC29
    B V2SYNC/GENLK_VSYNC B
    1 1 1 Global Swap Lock on multiple GPUs
    1

    1
    10K_0402_5%
    R38

    10K_0402_5%
    R39

    10K_0402_5%
    R40

    10K_0402_5%
    R41

    C18

    C19

    C20
    VGA_HDMI_DET AK24 10mil
    <11> VGA_HDMI_DET HPD1
    100mAVDD2DI/NC AG31 +VDD1DI
    AG32
    @ @ @ @ VSS2DI/NC 2 2 2
    +1.8VSG R42 1 VGA@ 2 499_0402_1% 10mil VGA@ VGA@ VGA@
    2

    VRAM_ID0 Internal PD 130mAA2VDD/NC AG33 +A2VDD Except A2VSSQ change to TSVSSQ,


    VRAM_ID1 R43 1 VGA@ 2 249_0402_1% 15mil 10mil
    VRAM_ID2 PD-Reset 2mAA2VDDQ/NC AD33 +A2VDDQ VGA@ VGA@ VGA@ +1.8VSG
    others are NC on Whistler and Seymour
    VRAM_ID3 1 2 VGA@ +VGA_VREF AH13 1 1 1
    VREFG

    1U_0402_6.3V4Z
    C22

    0.1U_0402_16V4Z
    C24

    10U_0603_6.3V6M
    C23
    C21 0.1U_0402_16V4Z AF33
    A2VSSQ/TSVSSQ
    1

    1
    10K_0402_5%
    R44

    10K_0402_5%
    R45

    10K_0402_5%
    R46

    10K_0402_5%
    R47

    R48
    +1.8VSG L3 715_0402_1%
    BLM18AG121SN1D_0603
    10mil 2 2 2
    AA29 1 2
    @ @ @ @ +DPLL_PVDD R2SET/NC VGA@
    2 1 AM32
    DPLL_PVDD
    10U_0603_6.3V6M

    0.1U_0402_16V4Z

    1U_0402_6.3V4Z

    VGA@ 1 1 1 AN32 75mA


    2

    DPLL_PVSS
    C25

    C26

    C27

    470ohm/1A DDC/AUX VGA_HDMI_SCLK


    10mil PLL/CLOCK DDC1CLK
    AM26
    VGA_HDMI_SDATA
    VGA_HDMI_SCLK <11>
    2 2 2
    AN31
    DPLL_VDDC DDC1DATA
    AN26 VGA_HDMI_SDATA <11> HDMI
    FLASH ROM 125mA
    VGA@ VGA@ VGA@ AM27
    U5 +1.0VSG L4 27MCLK AUX1P
    AV33 AL27
    SIN_GPIO9 SOUT_GPIO8 BLM18AG121SN1D_0603 XTALOUT XTALIN AUX1N
    5 2 AU34
    D Q +DPLL_VDDC XTALOUT
    2 1 AM19
    DDC2CLK
    10U_0603_6.3V6M

    0.1U_0402_16V4Z

    1U_0402_6.3V4Z

    CLK_GPIO10 6 VGA@ 1 1 1 AL19


    C DDC2DATA
    C28

    C29

    C30

    ROMSE_GPIO22
    470ohm/1A 1
    R49 @
    2 AW34
    0_0402_5% XO_IN
    1 AN20
    S TYPE 1 AUX2P
    1 2 AW35 AM20
    2 2 2 R50 @ 0_0402_5% XO_IN2 AUX2N
    +3VSG 7
    R51 0_0402_5% HOLD VGA@ VGA@ VGA@ AL30
    @ DDCCLK_AUX3P
    2 1 3 AM30
    W DDCDATA_AUX3N
    @
    NC on Park,
    2 1 8 4 AL29
    R52 0_0402_5% 2 VCC VSS GPU_THERM_D+ NC_DDCCLK_AUX4P Robson and Seymour
    AF29 AM29
    M25P10-AVMN6P GPU_THERM_D- DPLUS THERMAL NC_DDCDATA_AUX4N
    AG29
    C31 @ DMINUS VGA_CRT_CLK
    AN21 VGA_CRT_CLK <12>
    @ DDCCLK_AUX5P VGA_CRT_DATA
    1
    0.1U_0402_16V4Z AL31 Manhattan/Vancouver is NC, Boardway is DDCDATA_AUX5N
    AM21 VGA_CRT_DATA <12> CRT
    A AK32 A
    ADC input(0-1V) use measure regulator current or temperature TS_FDO
    AJ30
    DDC6CLK
    AL31 AJ31
    VGA@ +1.8VSG L5 TS_A/NC DDC6DATA
    XTALOUT 27MCLK BLM18AG121SN1D_0603 10mil AK30
    1M_0603_5% R53 +TSVDD NC_DDCCLK_AUX7P
    2
    VGA@
    1 AJ32
    TSVDD NC_DDCDATA_AUX7N
    AK29 NC on Park,
    1 1 1 AJ33
    TSVSS 20mA Robson and Seymour
    10U_0603_6.3V6M
    C32

    1U_0402_6.3V4Z
    C33

    0.1U_0402_16V4Z
    C34

    120ohm/0.3A
    Y1 VGA@
    2 2 2 2160809000A11SEYMOU_FCBGA962
    2 1
    VGA@ VGA@ VGA@
    Security Classification Compal Secret Data Compal Electronics, Inc.
    27MHZ_16PF_X5H027000FG1H Seymour@ 2010/08/20 2011/08/20 Title
    Issued Date Deciphered Date
    C35 C36
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Vancouver_Strape/DP/HDMI//CRT
    VGA@ VGA@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    18P_0402_50V8J 18P_0402_50V8J Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 19 of 46
    5 4 3 2 1
    5 4 3 2 1

    Robson,Seymour only support single channel


    memory (channel B only)
    D D

    U2D
    DDR2 DDR2
    U2C GDDR3/GDDR5 GDDR5/GDDR3 MAB[0..12]
    DDR2 DDR2 MDB[0..63] DDR3 DDR3 MAB[0..12] <23>
    GDDR3/GDDR5 GDDR5/GDDR3 <23> MDB[0..63]
    MDB0 C5 P8 MAB0
    DDR3 DDR3 MDB1 DQB0_0/DQB_0 MAB0_0/MAB_0 MAB1
    C3 DQB0_1/DQB_1 MAB0_1/MAB_1 T9
    C37 G24 MDB2 E3 P9 MAB2
    NC_DQA0_0/DQA_0 NC_MAA0_0/MAA_0 MDB3 DQB0_2/DQB_2 MAB0_2/MAB_2 MAB3
    C35 NC_DQA0_1/DQA_1 NC_MAA0_1/MAA_1 J23 E1 DQB0_3/DQB_3 MAB0_3/MAB_3 N7
    A35 H24 MDB4 F1 N8 MAB4
    NC_DQA0_2/DQA_2 NC_MAA0_2/MAA_2 MDB5 DQB0_4/DQB_4 MAB0_4/MAB_4 MAB5

    MEMORY INTERFACE B
    E34 NC_DQA0_3/DQA_3 NC_MAA0_3/MAA_3 J24 F3 DQB0_5/DQB_5 MAB0_5/MAB_5 N9
    MDB6 MAB6

    MEMORY INTERFACE A
    G32 NC_DQA0_4/DQA_4 NC_MAA0_4/MAA_4 H26 F5 DQB0_6/DQB_6 MAB0_6/MAB_6 U9
    D33 J26 MDB7 G4 U8 MAB7
    NC_DQA0_5/DQA_5 NC_MAA0_5/MAA_5 MDB8 DQB0_7/DQB_7 MAB0_7/MAB_7 MAB8
    F32 NC_DQA0_6/DQA_6 NC_MAA0_6/MAA_6 H21 H5 DQB0_8/DQB_8 MAB1_0/MAB_8 Y9
    E32 G21 MDB9 H6 W9 MAB9
    NC_DQA0_7/DQA_7 NC_MAA0_7/MAA_7 MDB10 DQB0_9/DQB_9 MAB1_1/MAB_9 MAB10
    D31 NC_DQA0_8/DQA_8 NC_MAA1_0/MAA_8 H19 J4 DQB0_10/DQB_10 MAB1_2/MAB_10 AC8
    F30 H20 MDB11 K6 AC9 MAB11
    NC_DQA0_9/DQA_9 NC_MAA1_1/MAA_9 MDB12 DQB0_11/DQB_11 MAB1_3/MAB_11 MAB12 B_BA[0..2]
    C30 NC_DQA0_10/DQA_10 NC_MAA1_2/MAA_10 L13 K5 DQB0_12/DQB_12 MAB1_4/MAB_12 AA7 B_BA[0..2] <23>
    A30 G16 MDB13 L4 AA8 B_BA2
    NC_DQA0_11/DQA_11 NC_MAA1_3/MAA_11 MDB14 DQB0_13/DQB_13 MAB1_5/BA2 B_BA0
    F28 NC_DQA0_12/DQA_12 NC_MAA1_4/MAA_12 J16 M6 DQB0_14/DQB_14 MAB1_6/BA0 Y8
    C28 H16 MDB15 M1 AA9 B_BA1
    NC_DQA0_13/DQA_13 NC_MAA1_5/MAA_13_BA2 MDB16 DQB0_15/DQB_15 MAB1_7/BA1 DQMB#[0..7]
    A28 NC_DQA0_14/DQA_14 NC_MAA1_6/MAA_14_BA0 J17 M3 DQB0_16/DQB_16 DQMB#[0..7] <23>
    E28 H17 MDB17 M5 H3 DQMB#0
    +1.5VSG NC_DQA0_15/DQA_15 NC_MAA1_7/MAA_A15_BA1 MDB18 DQB0_17/DQB_17 WCKB0_0/DQMB_0 DQMB#1
    D27 NC_DQA0_16/DQA_16 N4 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 H1
    F26 A32 MDB19 P6 T3 DQMB#2
    NC_DQA0_17/DQA_17 NC_WCKA0_0/DQMA_0 MDB20 DQB0_19/DQB_19 WCKB0_1/DQMB_2 DQMB#3
    C26 NC_DQA0_18/DQA_18 NC_WCKA0B_0/DQMA_1 C32 P5 DQB0_20/DQB_20 WCKB0B_1/DQMB_3 T5
    A26 D23 MDB21 R4 AE4 DQMB#4
    NC_DQA0_19/DQA_19 NC_WCKA0_1/DQMA_2 DQB0_21/DQB_21 WCKB1_0/DQMB_4
    1

    F24 E22 MDB22 T6 AF5 DQMB#5


    R54 NC_DQA0_20/DQA_20 NC_WCKA0B_1/DQMA_3 MDB23 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 DQMB#6
    C24 NC_DQA0_21/DQA_21 NC_WCKA1_0/DQMA_4 C14 T1 DQB0_23/DQB_23 WCKB1_1/DQMB_6 AK6
    VGA@ A24 A14 +1.5VSG MDB24 U4 AK5 DQMB#7
    40.2_0402_1% NC_DQA0_22/DQA_22 NC_WCKA1B_0/DQMA_5 MDB25 DQB0_24/DQB_24 WCKB1B_1/DQMB_7 QSB[0..7]
    E24 NC_DQA0_23/DQA_23 NC_WCKA1_1/DQMA_6 E10 V6 DQB0_25/DQB_25 QSB[0..7] <23>
    C MDB26 GDDR5/DDR2/GDDR3 QSB0 C
    C22 D9 V1 F6
    2

    MVREFDA NC_DQA0_24/DQA_24 NC_WCKA1B_1/DQMA_7 MDB27 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 QSB1


    A22 NC_DQA0_25/DQA_25 V3 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 K3

    1
    GDDR5/DDR2/GDDR3 MDB28 QSB2
    F22 NC_DQA0_26/DQA_26 NC_EDCA0_0/QSA_0/RDQSA_0 C34 Y6 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 P3
    1

    1 D21 D29 R56 MDB29 Y1 V5 QSB3


    NC_DQA0_27/DQA_27 NC_EDCA0_1/QSA_1/RDQSA_1 DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3
    0.1U_0402_16V4Z

    R55 C37 A20 D25 VGA@ MDB30 Y3 AB5 QSB4


    VGA@ NC_DQA0_28/DQA_28 NC_EDCA0_2/QSA_2/RDQSA_2 40.2_0402_1% MDB31 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 QSB5
    F20 NC_DQA0_29/DQA_29 NC_EDCA0_3/QSA_3/RDQSA_3 E20 Y5 DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5 AH1
    100_0402_1% VGA@ D19 E16 MDB32 AA4 AJ9 QSB6

    2
    2 NC_DQA0_30/DQA_30 NC_EDCA1_0/QSA_4/RDQSA_4 MVREFDB MDB33 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 QSB7
    E18 E12 AB6 AM5
    2

    NC_DQA0_31/DQA_31 NC_EDCA1_1/QSA_5/RDQSA_5 MDB34 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7 QSB#[0..7]


    C18 NC_DQA1_0/DQA_32 NC_EDCA1_2/QSA_6/RDQSA_6 J10 AB1 DQB1_2/DQB_34 QSB#[0..7] <23>

    0.1U_0402_16V4Z
    A18 D7 MDB35 AB3 G7 QSB#0
    NC_DQA1_1/DQA_33 NC_EDCA1_3/QSA_7/RDQSA_7 R57 MDB36 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 QSB#1
    F18 NC_DQA1_2/DQA_34 1 AD6 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 K1
    D17 A34 VGA@ C38 MDB37 AD1 P1 QSB#2
    NC_DQA1_3/DQA_35 NC_DDBIA0_0/QSA_0B/WDQSA_0 100_0402_1% MDB38 DQB1_5/DQB_37 DDBIB0_2/QSB_2B/WDQSB_2 QSB#3
    A16 NC_DQA1_4/DQA_36 NC_DDBIA0_1/QSA_1B/WDQSA_1 E30 AD3 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 W4
    +1.5VSG F16 E26 VGA@ MDB39 AD5 AC4 QSB#4

    2
    NC_DQA1_5/DQA_37 NC_DDBIA0_2/QSA_2B/WDQSA_2 2 MDB40 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/WDQSB_4 QSB#5
    D15 NC_DQA1_6/DQA_38 NC_DDBIA0_3/QSA_3B/WDQSA_3 C20 AF1 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5 AH3
    E14 C16 MDB41 AF3 AJ8 QSB#6
    NC_DQA1_7/DQA_39 NC_DDBIA1_0/QSA_4B/WDQSA_4 MDB42 DQB1_9/DQB_41 DDBIB1_2/QSB_6B/WDQSB_6 QSB#7
    F14 NC_DQA1_8/DQA_40 NC_DDBIA1_1/QSA_5B/WDQSA_5 C12 AF6 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7 AM3
    1

    D13 J11 MDB43 AG4


    R58 NC_DQA1_9/DQA_41 NC_DDBIA1_2/QSA_6B/WDQSA_6 MDB44 DQB1_11/DQB_43 ODTB0
    F12 NC_DQA1_10/DQA_42 NC_DDBIA1_3/QSA_7B/WDQSA_7 F8 AH5 DQB1_12/DQB_44 ADBIB0/ODTB0 T7 ODTB0 <23>
    VGA@ A12 +1.5VSG MDB45 AH6 W7 ODTB1
    NC_DQA1_11/DQA_43 DQB1_13/DQB_45 ADBIB1/ODTB1 ODTB1 <23>
    40.2_0402_1% D11 J21 MDB46 AJ4
    NC_DQA1_12/DQA_44 NC_ADBIA0/ODTA0 MDB47 DQB1_14/DQB_46 CLKB0
    F10 G19 AK3 L9 CLKB0 <23>
    2

    MVREFSA NC_DQA1_13/DQA_45 NC_ADBIA1/ODTA1 MDB48 DQB1_15/DQB_47 CLKB0 CLKB0#


    A10 NC_DQA1_14/DQA_46 AF8 DQB1_16/DQB_48 CLKB0B L8 CLKB0# <23>

    1
    C10 H27 MDB49 AF9
    NC_DQA1_15/DQA_47 NC_CLKA0 DQB1_17/DQB_49
    1

    1 G13 G27 R60 MDB50 AG8 AD8 CLKB1


    NC_DQA1_16/DQA_48 NC_CLKA0B DQB1_18/DQB_50 CLKB1 CLKB1 <23>
    0.1U_0402_16V4Z
    C39

    R59 H13 VGA@ MDB51 AG7 AD7 CLKB1#


    NC_DQA1_17/DQA_49 DQB1_19/DQB_51 CLKB1B CLKB1# <23>
    VGA@ J13 J14 40.2_0402_1% MDB52 AK9
    100_0402_1% NC_DQA1_18/DQA_50 NC_CLKA1 MDB53 DQB1_20/DQB_52 RASB0#
    H11 H14 AL7 T10 RASB0# <23>

    2
    2 VGA@ NC_DQA1_19/DQA_51 NC_CLKA1B MVREFSB MDB54 DQB1_21/DQB_53 RASB0B RASB1#
    G10 AM8 Y10 RASB1# <23>
    2

    NC_DQA1_20/DQA_52 MDB55 DQB1_22/DQB_54 RASB1B


    G8 NC_DQA1_21/DQA_53 NC_RASA0B K23 AM7 DQB1_23/DQB_55

    1
    K9 K19 1 MDB56 AK1 W10 CASB0#
    NC_DQA1_22/DQA_54 NC_RASA1B DQB1_24/DQB_56 CASB0B CASB0# <23>

    0.1U_0402_16V4Z
    K10 R61 C40 MDB57 AL4 AA10 CASB1#
    B NC_DQA1_23/DQA_55 DQB1_25/DQB_57 CASB1B CASB1# <23> B
    G9 K20 VGA@ MDB58 AM6
    NC_DQA1_24/DQA_56 NC_CASA0B 100_0402_1% VGA@ MDB59 DQB1_26/DQB_58 CSB0#_0
    A8 NC_DQA1_25/DQA_57 NC_CASA1B K17 AM1 DQB1_27/DQB_59 CSB0B_0 P10 CSB0#_0 <23>
    2 MDB60
    C8 AN4 L10

    2
    NC_DQA1_26/DQA_58 MDB61 DQB1_28/DQB_60 CSB0B_1
    E8 NC_DQA1_27/DQA_59 NC_CSA0B_0 K24 AP3 DQB1_29/DQB_61
    A6 K27 MDB62 AP1 AD10 CSB1#_0
    NC_DQA1_28/DQA_60 NC_CSA0B_1 DQB1_30/DQB_62 CSB1B_0 CSB1#_0 <23>
    C6 MDB63 AP5 AC10
    NC_DQA1_29/DQA_61 DQB1_31/DQB_63 CSB1B_1
    E6 NC_DQA1_30/DQA_62 NC_CSA1B_0 M13
    A5 K16 U10 CKEB0
    NC_DQA1_31/DQA_63 NC_CSA1B_1 CKEB0 CKEB0 <23>
    MVREFDB Y12 AA11 CKEB1
    MVREFDB CKEB1 CKEB1 <23>
    MVREFDA L18 K21 MVREFSB AA12
    +1.5VSG MVREFSA NC_MVREFDA NC_CKEA0 MVREFSB WEB0#
    L20 NC_MVREFSA NC_CKEA1 J20 WEB0B N10 WEB0# <23>
    AB11 WEB1#
    WEB1B WEB1# <23>
    R62 2 VGA@ 1 243_0402_1% L27 K26
    R63 NC_MEM_CALRN0 NC_WEA0B
    2 VGA@ 1 243_0402_1% N12 MEM_CALRN1 NC_WEA1B L15
    R64 2 VGA@ 1 243_0402_1% AG12 2 VGA@ 1 TESTEN AD28 T8 MAB13 is for 128M*16 VRAM
    NC_MEM_CALRN2 TESTEN MAB0_8 MAB13 <23>
    R65 5.11K_0402_1% W8
    R66 MAB1_8
    2 VGA@ 1 243_0402_1% M12 H23 TEST_MCLK AK10 R68 VGA@ VGA@ R70

    GDDR5
    R67 MEM_CALRP1 NC_MAA0_8 TEST_YCLK CLKTESTA
    2 VGA@ 1 243_0402_1% M27 NC_MEM_CALRP0 NC_MAA1_8 J19 AL10 CLKTESTB DRAM_RST AH11 1 2 1 2 VRAM_RST# <23>
    R69 2 VGA@ 1 243_0402_1% AH12 NC_MEM_CALRP2
    GDDR5

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    5.11K_0402_1%
    R71

    120P_0402_50V8
    10_0402_5% 51.1_0402_1%

    C43
    2 2 1

    C41

    C42

    VGA@
    VGA@
    1 1 2

    VGA@

    VGA@
    2160809000A11SEYMOU_FCBGA962

    2
    1

    1
    2160809000A11SEYMOU_FCBGA962 Seymour@

    Seymour@ R72 R73


    VGA@ VGA@
    2

    51.1_0402_1% 2 51.1_0402_1%
    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Vancouver_Memory
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 20 of 46
    5 4 3 2 1
    5 4 3 2 1

    U2E

    MEM I/O
    PCIE FBMA-L11-201209-221LMA30T_0805
    2800mA 504mA +PCIE_VDDR
    +1.5VSG AC7 VDDR1#1 PCIE_VDDR#1 AA31 2 1 +1.8VSG
    1 AD11 AA32 L34 VGA@
    VDDR1#2 PCIE_VDDR#2

    1U_0402_6.3V4Z
    C323 VGA@

    1U_0402_6.3V4Z
    C338 VGA@

    1U_0402_6.3V4Z
    C339 VGA@

    1U_0402_6.3V4Z
    C324 VGA@

    1U_0402_6.3V4Z
    C340 VGA@

    1U_0402_6.3V4Z
    C325 VGA@

    1U_0402_6.3V4Z
    C341 VGA@

    1U_0402_6.3V4Z
    C342 VGA@

    0.1U_0402_16V4Z
    C326 VGA@

    0.1U_0402_16V4Z
    C343 VGA@

    1U_0402_6.3V4Z
    C327 VGA@

    1U_0402_6.3V4Z
    C328 VGA@

    1U_0402_6.3V4Z
    C344 VGA@

    1U_0402_6.3V4Z
    C345 VGA@

    1U_0402_6.3V4Z
    C346 VGA@

    10U_0603_6.3V6M
    C347 VGA@
    C322 +
    1 1 1 1 1 1 1 1 AF7 VDDR1#3 PCIE_VDDR#3 AA33 1 1 1 1 1 1 1 1 220ohm/2A
    AG10 VDDR1#4 PCIE_VDDR#4 AA34
    VGA@ AJ7 V28
    390U_2.5V_10M VDDR1#5 PCIE_VDDR#5
    AK8 VDDR1#6 PCIE_VDDR#6 W29
    2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
    D
    AL9 VDDR1#7 PCIE_VDDR#7 W30 Change 0603 size D
    G11 Y31
    G14
    VDDR1#8 PCIE_VDDR#8
    AB37 For DVT
    VDDR1#9 PCIE_VDDR/PCIE_PVDD
    G17 VDDR1#10 2A
    390U ESR:10m H:5.7 G20 VDDR1#11 PCIE_VDDC#1 G30 +1.0VSG

    1U_0402_6.3V4Z
    C348VGA@

    1U_0402_6.3V4Z
    C349VGA@

    1U_0402_6.3V4Z
    C329VGA@

    1U_0402_6.3V4Z
    C330VGA@

    1U_0402_6.3V4Z
    C331VGA@

    1U_0402_6.3V4Z
    C350VGA@

    1U_0402_6.3V4Z
    C351VGA@

    1U_0402_6.3V4Z
    C352VGA@
    1 1 1 1 1 1 1 1 G23 G31 1
    P/N:SF000002O00 VDDR1#12 PCIE_VDDC#2

    1U_0402_6.3V4Z
    C353 VGA@

    1U_0402_6.3V4Z
    C332 VGA@

    1U_0402_6.3V4Z
    C354 VGA@

    1U_0402_6.3V4Z
    C333 VGA@

    1U_0402_6.3V4Z
    C334 VGA@

    1U_0402_6.3V4Z
    C355 VGA@

    1U_0402_6.3V4Z
    C356 VGA@

    10U_0603_6.3V6M
    C357 VGA@
    G26 VDDR1#13 PCIE_VDDC#3 H29 1 1 1 1 1 1 1 1
    G29 H30 C686 +
    VDDR1#14 PCIE_VDDC#4 VGA@
    H10 VDDR1#15 PCIE_VDDC#5 J29
    2 2 2 2 2 2 2 2 390U_2.5V_10M
    J7 VDDR1#16 PCIE_VDDC#6 J30
    2 2 2 2 2 2 2 2 2
    J9 VDDR1#17 PCIE_VDDC#7 L28
    K11 VDDR1#18 PCIE_VDDC#8 M28
    K13 VDDR1#19 PCIE_VDDC#9 N28
    K8 VDDR1#20 PCIE_VDDC#10 R28 Change 0603 size
    10U_0603_6.3V6M
    C335 MAN@

    10U_0603_6.3V6M
    C358 VGA@

    10U_0603_6.3V6M
    C336 VGA@

    10U_0603_6.3V6M
    C359 VGA@

    10U_0603_6.3V6M
    C360 VGA@

    1U_0402_6.3V4Z
    C361 VGA@

    1U_0402_6.3V4Z
    C337 VGA@

    1U_0402_6.3V4Z
    C362 VGA@

    1U_0402_6.3V4Z
    C363 VGA@
    1 1 1 1 1 1 1 1 1 L12 T28
    L16
    VDDR1#21 PCIE_VDDC#11
    U28 For DVT
    VDDR1#22 PCIE_VDDC#12

    2 2 2 2 2 2 2 2 2
    L21
    L23
    L26
    VDDR1#23
    VDDR1#24
    AA15
    FOR XT DDR3 13 A (RMS)/14.2 A(Peak)
    VDDR1#25 VDDC#1 +VGA_CORE

    1U_0402_6.3V4Z
    C364 VGA@

    1U_0402_6.3V4Z
    C365 VGA@

    1U_0402_6.3V4Z
    C366 VGA@

    1U_0402_6.3V4Z
    C367 VGA@

    1U_0402_6.3V4Z
    C368 VGA@

    1U_0402_6.3V4Z
    C369 VGA@

    1U_0402_6.3V4Z
    C370 VGA@

    1U_0402_6.3V4Z
    C371 VGA@

    1U_0402_6.3V4Z
    C372 VGA@

    1U_0402_6.3V4Z
    C373 VGA@
    L7 CORE AA17 1 1 1 1 1 1 1 1 1 1
    VDDR1#26 VDDC#2
    M11 VDDR1#27 VDDC#3 AA20
    N11 VDDR1#28 VDDC#4 AA22
    Change 0603 size P7 VDDR1#29 VDDC#5 AA24
    2 2 2 2 2 2 2 2 2 2
    R11 AA27
    For DVT U11
    VDDR1#30 VDDC#6
    AB16
    VDDR1#31 VDDC#7
    U7 VDDR1#32 VDDC#8 AB18
    Y11 VDDR1#33 VDDC#9 AB21
    Y7 VDDR1#34 VDDC#10 AB23

    1U_0402_6.3V4Z
    C374 VGA@

    1U_0402_6.3V4Z
    C375 VGA@

    1U_0402_6.3V4Z
    C376 VGA@

    1U_0402_6.3V4Z
    C377 VGA@

    1U_0402_6.3V4Z
    C378 VGA@

    1U_0402_6.3V4Z
    C379 VGA@

    1U_0402_6.3V4Z
    C380 VGA@

    1U_0402_6.3V4Z
    C381 VGA@

    1U_0402_6.3V4Z
    C382 VGA@

    1U_0402_6.3V4Z
    C383 VGA@
    VDDC#11 AB26 1 1 1 1 1 1 1 1 1 1
    VDDC#12 AB28
    +1.8VSG 2 1 +VDD_CT AC17
    L35 VGA@ VDDC#13
    1 1 1 VDDC#14 AC20
    10U_0603_6.3V6M 2 2 2 2 2 2 2 2 2 2
    C384 VGA@

    1U_0402_6.3V4Z
    C385 VGA@

    0.1U_0402_16V4Z
    C386 VGA@
    BLM18AG121SN1D_0603 LEVEL AC22
    C TRANSLATION VDDC#15 C
    120ohm/0.3A 219mA VDDC#16 AC24

    POWER
    AF26 VDD_CT#1 VDDC#17 AC27
    2 2 2
    AF27 VDD_CT#2 VDDC#18 AD18

    10U_0603_6.3V6M
    C387 VGA@

    10U_0603_6.3V6M
    C388 VGA@

    10U_0603_6.3V6M
    C389 VGA@

    10U_0603_6.3V6M
    C390 VGA@

    10U_0603_6.3V6M
    C391 VGA@

    10U_0603_6.3V6M
    C392 VGA@

    10U_0603_6.3V6M
    C393 VGA@
    AG26 VDD_CT#3 VDDC#19 AD21 1 1 1 1 1 1 1 1 1
    AG27 VDD_CT#4 VDDC#20 AD23
    AD26 + C394 + C395
    VDDC#21 VGA@ VGA@
    VDDC#22 AF17
    I/O 2 2 2 2 2 2 2 390U_2.5V_10M 330U_D2_2V_Y
    +VDDR3
    60mA VDDC#23 AF20
    2 2
    +3VSG AF23 VDDR3#1 VDDC#24 AF22
    1 1 1 AF24 VDDR3#2 VDDC#25 AG16
    10U_0603_6.3V6M
    C397 VGA@

    1U_0402_6.3V4Z
    C398 VGA@

    0.1U_0402_16V4Z
    C399 VGA@

    Removed bead on ref137-12 AG23 VDDR3#3 VDDC#26 AG18


    AG24 VDDR3#4 VDDC#27 AG21 Change 0603 size
    2 2 2 VDDC#28 AH22
    For DVT 330U ESR:10m H:5.7
    AH27
    AF13
    VDDC#29
    AH28 P/N:SF000002O00
    VDDR4#4 VDDC#30
    AF15 VDDR4#5 VDDC#31 M26
    AG13 VDDR4#7 VDDC#32 N24 55mA
    L36 VGA@
    170mA AG15 VDDR4#8 VDDC/BIF_VDDC#33 N27 +BIF_VDDC
    VDDC#34 R18
    +1.8VSG 2 1 +VDDR4 R21
    VDDC#35
    AD12 VDDR4#1 VDDC#36 R23
    10U_0603_6.3V6M
    C400 VGA@

    1U_0402_6.3V4Z
    C401 VGA@

    0.1U_0402_16V4Z
    C402 VGA@

    BLM18AG601SN1D_2P 1 1 1 AF11 R26


    VDDR4#2 VDDC#37
    120ohm/0.3A AF12 VDDR4#3 VDDC#38 T17
    AG11 VDDR4#6 VDDC#39 T20
    VDDC#40 T22
    2 2 2
    VDDC#41 T24
    VDDC/BIF_VDDC#42 T27
    VDDC#43 U16
    M20 NC_VDDRHA VDDC#44 U18
    M21 NC_VSSRHA VDDC#45 U21
    VDDC#46 U23
    BLM18AG121SN1D_0603 U26
    B VDDC#47 B
    +1.8VSG 2 1 V12 NC_VDDRHB VDDC#48 V17
    L37 VGA@ U12 V20
    NC_VSSRHB VDDC#49
    470ohm/1A 1 1 1 1 1 VDDC#50 V22
    10U_0603_6.3V6M
    C403 VGA@

    1U_0402_6.3V4Z
    C404 VGA@

    0.1U_0402_16V4Z
    C405 VGA@

    1U_0402_6.3V4Z
    C406 VGA@

    0.1U_0402_16V4Z
    C407 VGA@

    VDDC#51 V24
    VDDC#52 V27
    VDDC#53 Y16
    2 2 2 2 2 PLL
    VDDC#54 Y18
    VDDC#55 Y21
    VDDC#56 Y23

    +MPV_18
    75mA H7 MPV18#1 VDDC#57 Y26
    H8 MPV18#2 VDDC#58 Y28

    BLM18AG121SN1D_0603 75mA 4A
    +1.8VSG 2 1 +SPV_18 AM10 L39 VGA@ J7
    L38 VGA@ SPV18 +VDDCI
    120mA VDDCI#1 AA13 2 1 2 2 1 1 +VGA_CORE

    0.1U_0402_16V4Z
    120ohm/0.3A 1 1 1 +1.0VSG 2 1 +SPV10 AN9 AB13 FBMA-L11-201209-121LMA50T_0805
    SPV10 VDDCI#2
    10U_0603_6.3V6M
    C409 VGA@

    1U_0402_6.3V4Z
    C410 VGA@

    0.1U_0402_16V4Z
    C411 VGA@

    1U_0402_6.3V4Z

    1U_0402_6.3V4Z
    C416 VGA@

    1U_0402_6.3V4Z
    C417 VGA@

    1U_0402_6.3V4Z
    C418 VGA@

    1U_0402_6.3V4Z
    C419 VGA@

    1U_0402_6.3V4Z
    C420 VGA@
    L40 VGA@ AC12 1 1 1 1 1 1 1 @ JUMP_43X118
    VDDCI#3
    10U_0603_6.3V6M
    C408 VGA@

    1U_0402_6.3V4Z
    C412 VGA@

    0.1U_0402_16V4Z
    C413 VGA@

    C414 VGA@

    C415 VGA@
    BLM18AG121SN1D_0603 1 1 1 AN10 AC15 L41 VGA@
    SPVSS VDDCI#4
    2 2 2 470ohm/1A VDDCI#5 AD13 2 1
    FBMA-L11-201209-121LMA50T_0805
    VDDCI#6 AD16
    2 2 2 2 2 2 2
    VDDCI#7 M15
    2 2 2
    VDDCI#8 M16
    VOLTAGE M18
    SENESE VDDCI#9
    VDDCI#10 M23
    VDDCI#11 N13
    GCORE_SEN AF28 N15
    <43> GCORE_SEN FB_VDDC VDDCI#12
    VDDCI#13 N17
    VDDCI#14 N20
    1U_0402_6.3V4Z
    C422 VGA@

    1U_0402_6.3V4Z
    C423 VGA@

    1U_0402_6.3V4Z
    C424 VGA@

    1U_0402_6.3V4Z
    C425 VGA@

    1U_0402_6.3V4Z
    C426 VGA@

    10U_0603_6.3V6M
    C421 VGA@

    10U_0603_6.3V6M
    C427 VGA@

    10U_0603_6.3V6M
    C428 VGA@
    AG28 FB_VDDCI N22 1 1 1 1 1 1 1 1
    ISOLATED VDDCI#15 R12
    CORE I/O VDDCI#16 R13
    VDDCI#17
    1 R375 2 FB_GND AH29
    FB_GND VDDCI#18 R16
    A VGA@ 0_0402_5% 2 2 2 2 2 2 2 2 A
    VDDCI#19 T12
    VDDCI#20 T15
    VDDCI#21 V15
    VDDCI#22 Y13
    Change 0603 size
    For DVT
    2160809000A11SEYMOU_FCBGA962
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Seymour@ Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Vancouver_Power/GND
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Monday, November 01, 2010 Sheet 21 of 46
    5 4 3 2 1
    5 4 3 2 1

    U2F

    AB39 PCIE_VSS#1 GND#1 A3


    E39 PCIE_VSS#2 GND#2 A37
    F34 PCIE_VSS#3 GND#3 AA16
    F39 PCIE_VSS#4 GND#4 AA18
    G33 PCIE_VSS#5 GND#5 AA2
    G34 PCIE_VSS#6 GND#6 AA21
    H31 PCIE_VSS#7 GND#7 AA23
    H34 AA26
    PCIE_VSS#8 GND#8 U2H
    H39 AA28
    PCIE_VSS#9 GND#9
    J31 AA6
    D PCIE_VSS#10 GND#10 DP C/D POWER DP A/B POWER D
    J34 AB12
    PCIE_VSS#11 GND#11 L42 VGA@ L63 VGA@
    K31 AB15
    PCIE_VSS#12 GND#12 BLM18AG121SN1D_0603 BLM18AG121SN1D_0603
    K34
    PCIE_VSS#13 GND#13
    AB17 150mA +DPCD_VDD18
    AP20
    DPCD/DPC_VDD18#1 DPAB/DPA_VDD18#1
    AN24
    +DPAB_VDD18
    300mA
    K39 AB20 +1.8VSG 2 1 AP21 AP24 2 1 +1.8VSG
    PCIE_VSS#14 GND#14 DPCD/DPC_VDD18#2 DPAB/DPA_VDD18#2
    L31
    PCIE_VSS#15 GND#15
    AB22 470ohm/1A 470ohm/1A
    L34 AB24 1 1 1 1 1 1
    PCIE_VSS#16 GND#16

    10U_0603_6.3V6M
    C429 VGA@

    0.1U_0402_16V4Z
    C430 VGA@

    1U_0402_6.3V4Z
    C431 VGA@

    10U_0603_6.3V6M
    C432 VGA@

    0.1U_0402_16V4Z
    C433 VGA@

    1U_0402_6.3V4Z
    C434 VGA@
    M34 AB27
    PCIE_VSS#17 GND#17
    M39 AC11 AP13 AP31
    PCIE_VSS#18 GND#18 +DPCD_VDD10 DPCD/DPC_VDD10#1 DPAB/DPA_VDD10#1 +DPAB_VDD10
    N31 AC13 AT13 AP32
    PCIE_VSS#19 GND#19 2 2 2 DPCD/DPC_VDD10#2 DPAB/DPA_VDD10#2 2 2 2
    N34 AC16
    PCIE_VSS#20 GND#20
    P31 AC18
    PCIE_VSS#21 GND#21
    P34 PCIE_VSS#22 GND#22 AC2 AN17 DP/DPC_VSSR#1 DP/DPA_VSSR#1 AN27
    P39 PCIE_VSS#23 GND#23 AC21 AP16 DP/DPC_VSSR#2 DP/DPA_VSSR#2 AP27
    R34 PCIE_VSS#24 GND#24 AC23 AP17 DP/DPC_VSSR#3 DP/DPA_VSSR#3 AP28
    T31 PCIE_VSS#25 GND#25 AC26 AW14 DP/DPC_VSSR#4 DP/DPA_VSSR#4 AW24
    T34 PCIE_VSS#26 GND#26 AC28 AW16 DP/DPC_VSSR#5 DP/DPA_VSSR#5 AW26
    T39 PCIE_VSS#27 GND#27 AC6
    U31 PCIE_VSS#28 GND#28 AD15
    U34 PCIE_VSS#29 GND#29 AD17
    V34 PCIE_VSS#30 GND#30 AD20 AP22 DPCD/DPD_VDD18#1 DPAB/DPB_VDD18#1 AP25
    V39 AD22 +DPCD_VDD18 AP23 AP26 +DPAB_VDD18
    PCIE_VSS#31 GND#31 DPCD/DPD_VDD18#2 DPAB/DPB_VDD18#2
    W31 PCIE_VSS#32 GND#32 AD24
    W34 AD27 L64 VGA@ L66 VGA@
    PCIE_VSS#33 GND#33 BLM18AG121SN1D_0603 BLM18AG121SN1D_0603
    Y34 PCIE_VSS#34 GND#34 AD9 110mA +DPCD_VDD10 +DPAB_VDD10
    220mA
    Y39 PCIE_VSS#35 GND#35 AE2 +1.0VSG 2 1 AP14 DPCD/DPD_VDD10#1 DPAB/DPB_VDD10#1 AN33 2 1 +1.0VSG
    GND#36 AE6 470ohm/1A AP15 DPCD/DPD_VDD10#2 DPAB/DPB_VDD10#2 AP33 470ohm/1A

    0.1U_0402_16V4Z
    C438

    1U_0402_6.3V4Z
    C439

    10U_0603_6.3V6M
    C440
    GND#37 AF10 1 1 1

    10U_0603_6.3V6M
    C435 VGA@

    0.1U_0402_16V4Z
    C436 VGA@

    1U_0402_6.3V4Z
    C437 VGA@
    GND#38 AF16 1 1 1
    GND#39 AF18
    AF21 AN19 AN29
    GND GND#40 2 2 2 DP/DPD_VSSR#1 DP/DPB_VSSR#1

    VGA@

    VGA@

    VGA@
    GND#41 AG17 AP18 DP/DPD_VSSR#2 DP/DPB_VSSR#2 AP29
    F15 AG2 AP19 AP30 2 2 2
    C GND#100 GND#42 DP/DPD_VSSR#3 DP/DPB_VSSR#3 C
    F17 GND#101 GND#43 AG20 AW20 DP/DPD_VSSR#4 DP/DPB_VSSR#4 AW30
    F19 GND#102 GND#44 AG22 AW22 DP/DPD_VSSR#5 DP/DPB_VSSR#5 AW32
    F21 GND#103 GND#45 AG6
    F23 AG9 R376 R377
    GND#104 GND#46 150_0402_1% 150_0402_1%
    F25 GND#105 GND#47 AH21
    F27 GND#106 GND#48 AJ10 2 VGA@ 1 AW18 DPCD_CALR DPAB_CALR AW28 1 VGA@ 2
    F29 GND#107 GND#49 AJ11
    F31 AJ2 L67 VGA@
    GND#108 GND#50 BLM18AG121SN1D_0603
    F33
    GND#109 GND#51
    AJ28 440mA +DPEF_VDD18
    DP E/F POWER DP PLL POWER
    +DPAB_VDD18
    F7 AJ6 +1.8VSG 2 1 AH34 AU28
    GND#110 GND#52 DPEF/DPE_VDD18#1 DPAB_VDD18/DPA_PVDD
    F9
    GND#111 GND#53
    AK11 470ohm/1A AJ34
    DPEF/DPE_VDD18#2 DP_VSSR/DPA_PVSS
    AV27
    G2 AK31 1 1 1
    GND#112 GND#54

    10U_0603_6.3V6M
    C441

    0.1U_0402_16V4Z
    C442

    1U_0402_6.3V4Z
    C443
    G6 AK7
    GND#113 GND#55
    H9 AL11
    GND#114 GND#56 +DPEF_VDD10 +DPAB_VDD18
    J2 AL14 AL33 AV29
    GND#115 GND#57 2 2 2 DPEF/DPE_VDD10#1 DPAB_VDD18/DPB_PVDD
    J27 AL17 AM33 AR28
    GND#116 GND#58 DPEF/DPE_VDD10#2 DP_VSSR/DPB_PVSS

    VGA@

    VGA@

    VGA@
    J6 AL2
    GND#117 GND#59 R378
    J8 AL20
    GND#118 GND#60
    K14 AL21 1 2 PX_EN <24>
    GND#119 GND/PX_EN#61 BACO@ 0_0402_5% +DPCD_VDD18
    K7 AL23 AN34 AU18
    GND#120 GND#62 DP/DPE_VSSR#1 DPCD_VDD18/DPC_PVDD
    L11 AL26 AP39 AV17
    GND#121 GND#63 DP/DPE_VSSR#2 DP_VSSR/DPC_PVSS
    L17 AL32 AR39
    GND#122 GND#64 DP/DPE_VSSR#3
    L2 AL6 AU37
    GND#123 GND#65 DP/DPE_VSSR#4
    L22 AL8
    GND#124 GND#66 +DPCD_VDD18
    L24 AM11 AV19
    GND#125 GND#67 DPCD_VDD18/DPD_PVDD
    L6 AM31 AR18
    GND#126 GND#68 DP_VSSR/DPD_PVSS
    M17 AM9
    GND#127 GND#69
    M22 AN11 AF34
    GND#128 GND#70 +DPEF_VDD18 DPEF/DPF_VDD18#1
    M24 AN2 AG34
    GND#129 GND#71 DPEF/DPF_VDD18#2 +DPEF_VDD18
    N16 AN30 AM37
    GND#130 GND#72 L80 VGA@ DPEF_VDD18/DPE_PVDD
    N18 AN6 AN38
    GND#131 GND#73 BLM18AG121SN1D_0603 DP_VSSR/DPE_PVSS
    B
    N2
    GND#132 GND#74
    AN8 240mA +DPEF_VDD10 B
    N21 AP11 +1.0VSG 2 1 AK33
    GND#133 GND#75 DPEF/DPF_VDD10#1
    N23
    GND#134 GND#76
    AP7 470ohm/1A AK34
    DPEF/DPF_VDD10#2 +DPEF_VDD18
    N26 AP9 1 1 1 AL38
    GND#135 GND#77 DPEF_VDD18/DPF_PVDD
    10U_0603_6.3V6M
    C444 VGA@

    0.1U_0402_16V4Z
    C445 VGA@

    1U_0402_6.3V4Z
    C446 VGA@

    N6 AR5 AM35
    GND#136 GND#78 DP_VSSR/DPF_PVSS
    R15 B11
    GND#137 GND#79
    R17 B13 AF39
    GND#138 GND#80 2 2 2 DP/DPF_VSSR#1
    R2 B15 AH39
    GND#139 GND#81 DP/DPF_VSSR#2
    R20 B17 AK39
    GND#140 GND#82 DP/DPF_VSSR#3
    R22 B19 AL34
    GND#141 GND#83 DP/DPF_VSSR#4
    R24 B21 AM34
    GND#142 GND#84 DP/DPF_VSSR#5
    R27 B23
    GND#143 GND#85
    R6 B25
    GND#144 GND#86 R379
    T11 B27
    GND#145 GND#87
    T13 B29 2 VGA@ 1 AM39
    GND#146 GND#88 DPEF_CALR
    T16 B31
    GND#147 GND#89 150_0402_1%
    T18 B33
    GND#148 GND#90
    T21 B7
    GND#149 GND#91 2160809000A11SEYMOU_FCBGA962
    T23 B9
    GND#150 GND#92 Seymour@
    T26 C1
    GND#151 GND#93
    U15 C39
    GND#153 GND#94
    U17 E35
    GND#154 GND#95
    U2 E5
    GND#155 GND#96
    U20 F11
    GND#156 GND#97
    U22 F13
    GND#157 GND#98
    U24
    GND#158
    U27
    GND#159
    U6
    GND#160
    V11
    GND#161
    V16
    GND#163
    V18
    GND#164
    V21
    GND#165
    V23 GND#166
    A A
    V26 GND#167
    W2 GND#168
    W6 GND#169
    Y15 GND#170
    Y17 GND#171
    Y20 GND#172
    Y22 GND#173 VSS_MECH#1 A39
    Y24 AW1
    Y27
    GND#174
    GND#175
    VSS_MECH#2
    VSS_MECH#3 AW39
    Security Classification Compal Secret Data Compal Electronics, Inc.
    U13 GND#152 Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title
    @
    1 2 V13
    R455 0_0603_5% GND#162
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Vancouver_Power/GND
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    2160809000A11SEYMOU_FCBGA962 Custom 0.3
    Seymour@
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 22 of 46
    5 4 3 2 1
    5 4 3 2 1

    U6 U7 U8 U9

    VREFCB_A1 M8 E3 MDB26 VREFCB_A2 M8 E3 MDB22 VREFCB_A3 M8 E3 MDB35 VREFCB_A4 M8 E3 MDB55


    VREFDB_Q1 H1 VREFCA DQL0 MDB28 VREFDB_Q2 H1 VREFCA DQL0 MDB20 VREFDB_Q3 H1 VREFCA DQL0 MDB37 VREFDB_Q4 H1 VREFCA DQL0 MDB49
    VREFDQ DQL1 F7 VREFDQ DQL1 F7 VREFDQ DQL1 F7 VREFDQ DQL1 F7
    F2 MDB27 F2 MDB21 F2 MDB34 F2 MDB52
    MAB0 DQL2 MDB31 MAB0 DQL2 MDB18 MAB0 DQL2 MDB39 MAB0 DQL2 MDB50
    N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
    MAB1 P7 H3 MDB25 MAB1 P7 H3 MDB19 MAB1 P7 H3 MDB33 MAB1 P7 H3 MDB53
    MAB2 A1 DQL4 MDB30 MAB2 A1 DQL4 MDB17 MAB2 A1 DQL4 MDB38 MAB2 A1 DQL4 MDB48
    P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8
    MAB3 N2 G2 MDB24 MAB3 N2 G2 MDB23 MAB3 N2 G2 MDB32 MAB3 N2 G2 MDB54
    MAB4 A3 DQL6 MDB29 MAB4 A3 DQL6 MDB16 MAB4 A3 DQL6 MDB36 MAB4 A3 DQL6 MDB51
    P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7
    MAB5 P2 MAB5 P2 MAB5 P2 MAB5 P2
    MAB6 A5 MAB6 A5 MAB6 A5 MAB6 A5
    R8 A6 R8 A6 R8 A6 R8 A6
    MAB7 R2 D7 MDB15 MAB7 R2 D7 MDB1 MAB7 R2 D7 MDB44 MAB7 R2 D7 MDB56
    MAB8 A7 DQU0 MDB10 MAB8 A7 DQU0 MDB6 MAB8 A7 DQU0 MDB43 MAB8 A7 DQU0 MDB59
    T8 C3 T8 C3 T8 C3 T8 C3
    MAB9 A8 DQU1 MDB12 MAB9 A8 DQU1 MDB0 MAB9 A8 DQU1 MDB47 MAB9 A8 DQU1 MDB63
    R3 C8 R3 C8 R3 C8 R3 C8
    D MAB10 A9 DQU2 MDB11 MAB10 A9 DQU2 MDB4 MAB10 A9 DQU2 MDB41 MAB10 A9 DQU2 MDB62 D
    L7 C2 L7 C2 L7 C2 L7 C2
    MAB11 A10/AP DQU3 MDB13 MAB11 A10/AP DQU3 MDB3 MAB11 A10/AP DQU3 MDB45 MAB11 A10/AP DQU3 MDB57
    R7 A7 R7 A7 R7 A7 R7 A7
    MAB12 A11 DQU4 MDB9 MAB12 A11 DQU4 MDB7 MAB12 A11 DQU4 MDB40 MAB12 A11 DQU4 MDB61
    N7 A2 N7 A2 N7 A2 N7 A2
    MAB13 A12 DQU5 MDB14 MAB13 A12 DQU5 MDB2 MAB13 A12 DQU5 MDB46 MAB13 A12 DQU5 MDB58
    T3 B8 T3 B8 T3 B8 T3 B8
    A13 DQU6 MDB8 A13 DQU6 MDB5 A13 DQU6 MDB42 A13 DQU6 MDB60
    T7 A3 T7 A3 T7 A3 T7 A3
    A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
    M7 M7 M7 M7
    A15/BA3 +1.5VSG A15/BA3 +1.5VSG A15/BA3 +1.5VSG A15/BA3 +1.5VSG

    M2 B2 B_BA0 M2 B2 B_BA0 M2 B2 B_BA0 M2 B2


    <20> B_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
    N8 D9 B_BA1 N8 D9 B_BA1 N8 D9 B_BA1 N8 D9
    <20> B_BA1 BA1 VDD B_BA2 BA1 VDD B_BA2 BA1 VDD B_BA2 BA1 VDD
    <20> B_BA2 M3 G7 M3 G7 M3 G7 M3 G7
    BA2 VDD BA2 VDD BA2 VDD BA2 VDD
    VDD K2 VDD K2 VDD K2 VDD K2
    MDB[0..63] K8 K8 K8 K8
    <20> MDB[0..63] VDD VDD VDD VDD
    VDD N1 VDD N1 VDD N1 VDD N1
    CLKB0 J7 N9 CLKB0 J7 N9 CLKB1 J7 N9 CLKB1 J7 N9
    CLKB0# CK VDD CLKB0# CK VDD CLKB1# CK VDD CLKB1# CK VDD
    K7 CK VDD R1 K7 CK VDD R1 K7 CK VDD R1 K7 CK VDD R1
    K9 R9 CKEB0 K9 R9 K9 R9 CKEB1 K9 R9
    <20> CKEB0 CKE/CKE0 VDD +1.5VSG CKE/CKE0 VDD +1.5VSG <20> CKEB1 CKE/CKE0 VDD +1.5VSG CKE/CKE0 VDD +1.5VSG
    <20> MAB[13..0] ODTB0_1 ODTB0_1 ODTB1_1 ODTB1_1
    K1 ODT/ODT0 VDDQ A1 K1 ODT/ODT0 VDDQ A1 K1 ODT/ODT0 VDDQ A1 K1 ODT/ODT0 VDDQ A1
    L2 A8 CSB0#_0 L2 A8 L2 A8 CSB1#_0 L2 A8
    <20> CSB0#_0 CS/CS0 VDDQ RASB0# CS/CS0 VDDQ <20> CSB1#_0 CS/CS0 VDDQ RASB1# CS/CS0 VDDQ
    <20> RASB0# J3 RAS VDDQ C1 J3 RAS VDDQ C1 <20> RASB1# J3 RAS VDDQ C1 J3 RAS VDDQ C1
    K3 C9 CASB0# K3 C9 K3 C9 CASB1# K3 C9
    <20> CASB0# CAS VDDQ WEB0# CAS VDDQ <20> CASB1# CAS VDDQ WEB1# CAS VDDQ
    <20> DQMB#[7..0] <20> WEB0# L3 WE VDDQ D2 L3 WE VDDQ D2 <20> WEB1# L3 WE VDDQ D2 L3 WE VDDQ D2
    VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
    VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
    QSB3 F3 H2 QSB2 F3 H2 QSB4 F3 H2 QSB6 F3 H2
    QSB1 DQSL VDDQ QSB0 DQSL VDDQ QSB5 DQSL VDDQ QSB7 DQSL VDDQ
    C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
    <20> QSB[7..0]
    DQMB#3 E7 A9 DQMB#2 E7 A9 DQMB#4 E7 A9 DQMB#6 E7 A9
    DQMB#1 DML VSS DQMB#0 DML VSS DQMB#5 DML VSS DQMB#7 DML VSS
    D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3
    C C
    VSS E1 VSS E1 VSS E1 VSS E1
    <20> QSB#[7..0] VSS G8 VSS G8 VSS G8 VSS G8
    QSB#3 G3 J2 QSB#2 G3 J2 QSB#4 G3 J2 QSB#6 G3 J2
    QSB#1 DQSL VSS QSB#0 DQSL VSS QSB#5 DQSL VSS QSB#7 DQSL VSS
    B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8
    VSS M1 VSS M1 VSS M1 VSS M1
    VSS M9 VSS M9 VSS M9 VSS M9
    VSS P1 VSS P1 VSS P1 VSS P1
    VRAM_RST# T2 P9 VRAM_RST# T2 P9 VRAM_RST# T2 P9 VRAM_RST# T2 P9
    <20> VRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
    T1 T1 T1 T1
    VSS VSS VSS VSS
    L8 T9 L8 T9 L8 T9 L8 T9
    ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
    1

    1
    J1 B1 J1 B1 J1 B1 J1 B1
    R79 NC/ODT1 VSSQ R80 NC/ODT1 VSSQ R81 NC/ODT1 VSSQ R82 NC/ODT1 VSSQ
    L1 B9 L1 B9 L1 B9 L1 B9
    VGA@ NC/CS1 VSSQ VGA@ NC/CS1 VSSQ VGA@ NC/CS1 VSSQ VGA@ NC/CS1 VSSQ
    J9 D1 J9 D1 J9 D1 J9 D1
    243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ
    L9 D8 L9 D8 L9 D8 L9 D8
    NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
    E2 E2 E2 E2
    2

    2
    VSSQ VSSQ VSSQ VSSQ
    E8 E8 E8 E8
    VSSQ VSSQ VSSQ VSSQ
    F9 F9 F9 F9
    VSSQ VSSQ VSSQ VSSQ
    G1 G1 G1 G1
    VSSQ VSSQ VSSQ VSSQ
    G9 G9 G9 G9
    VSSQ VSSQ VSSQ VSSQ
    96-BALL 96-BALL 96-BALL 96-BALL
    SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
    K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
    X76@ X76@ X76@ X76@
    +1.5VSG +1.5VSG +1.5VSG +1.5VSG +1.5VSG
    +1.5VSG +1.5VSG +1.5VSG +1.5VSG
    1

    1
    ODTB0_1

    1
    R84 R85 R86
    R92 VGA@ R83 VGA@ VGA@ VGA@ R87 R88 R89 R90
    B VGA@ 56_0402_1% VGA@ 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% VGA@ VGA@ VGA@ VGA@ B
    ODTB0 R91 1 2 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
    <20> ODTB0
    2

    2
    0_0402_5% VREFCB_A1 VREFDB_Q1 VREFCB_A2 VREFDB_Q2
    R94 VGA@ 1 1 1 1 VREFCB_A3 VREFDB_Q3 VREFCB_A4 VREFDB_Q4
    1

    1
    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    VGA@ 56_0402_1% 1 1 1 1

    1
    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    ODTB1 R93 1 2 C169 R96 C170 R97 C171 R98 C172
    <20> ODTB1
    0_0402_5% R95 VGA@ VGA@ VGA@ R78 C173 R100 C174 R101 C175 R102 C176
    VGA@ VGA@ 2 4.99K_0402_1% VGA@ 2 4.99K_0402_1% VGA@ 2 4.99K_0402_1% VGA@ 2 VGA@ VGA@ VGA@ VGA@
    ODTB1_1 4.99K_0402_1% 4.99K_0402_1% VGA@ 2 4.99K_0402_1% VGA@ 2 4.99K_0402_1% VGA@ 2 4.99K_0402_1% VGA@ 2
    2

    2
    R103 VGA@
    56_0402_1%
    1 2 +1.5VSG +1.5VSG
    <20> CLKB0
    +1.5VSG
    R104 VGA@ +1.5VSG
    56_0402_1%
    1U_0402_6.3V6K
    C178 VGA@

    1U_0402_6.3V6K
    C179 VGA@

    1U_0402_6.3V6K
    C180 VGA@

    1U_0402_6.3V6K
    C181 VGA@

    1U_0402_6.3V6K
    C182 VGA@

    1U_0402_6.3V6K
    C183 VGA@

    1U_0402_6.3V6K
    C184 VGA@

    1U_0402_6.3V6K
    C185 VGA@

    1U_0402_6.3V6K
    C186 VGA@

    1U_0402_6.3V6K
    C187 VGA@

    <20> CLKB0# 1 2 1 1 1 1 1 1 1 1 1 1
    0.01U_0402_25V7K
    C177 VGA@

    1U_0402_6.3V6K
    C188 VGA@

    1U_0402_6.3V6K
    C189 VGA@

    1U_0402_6.3V6K
    C190 VGA@

    1U_0402_6.3V6K
    C191 VGA@

    1U_0402_6.3V6K
    C192 VGA@
    1 1 1 1 1 1

    1U_0402_6.3V6K
    C193 VGA@

    1U_0402_6.3V6K
    C194 VGA@

    1U_0402_6.3V6K
    C195 VGA@

    1U_0402_6.3V6K
    C196 VGA@

    1U_0402_6.3V6K
    C197 VGA@
    1 1 1 1 1
    2 2 2 2 2 2 2 2 2 2
    2 2 2 2 2 2
    2 2 2 2 2
    R105 VGA@
    56_0402_1% +1.5VSG
    1 2 +1.5VSG
    <20> CLKB1
    VRAM P/N :
    R106 VGA@
    Samsung : SA00004GS10 (S IC D3 64M16 K4W1G1646G-BC11 FBGA) 900MHz
    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    56_0402_1% 1 1 1 1
    C203 VGA@

    C204 VGA@

    C205 VGA@

    C206 VGA@
    <20> CLKB1# 1 2 1 1 1 1 Hynix : SA000032420 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )800MHz
    0.01U_0402_25V7K
    C198 VGA@

    10U_0603_6.3V6M
    C199 VGA@

    10U_0603_6.3V6M
    C200 VGA@

    10U_0603_6.3V6M
    C201 VGA@

    10U_0603_6.3V6M
    C202 VGA@

    A A
    1
    Hynix : SA000041S40 ( S IC D3 64MX16 H5TQ1G63DFR-11C FBGA )900MHz
    2 2 2 2
    2 2 2 2
    2

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    VRAM_DDR3 / Channel B
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 23 of 46
    5 4 3 2 1
    5 4 3 2 1

    VGA Muxless and Dis only Status Mapping table


    Power Sequence of Granville Power Sequence of Whistler and Seymour Dis only Muxless High performance GPU Muxless Power-saving GPU
    VGA_PWR_ON 1 1 0
    FCH_PWRGD 38ms SUSP# 1.5_VDDC_PWREN 1 1 0
    Ref CLK +3VSG +3.3VSG ON ON OFF
    (JUMP form +3VS) +1.8VSG ON ON OFF
    INT_VGAPWR_ON +1.0VSG ON
    50ms VGA_ON 10ms ON OFF
    D VGA_PWR_ON +VGA_CORE ON ON OFF D
    VGA_PWR_ON
    +1.5VSG ON ON OFF
    +3VSG
    1.5_VDDC_PWREN +BIF_VDDC +VGA_CORE +VGA_CORE OFF
    +VGA_CORE
    +VGA_CORE VGA Muxless with BACO Status Mapping table VGA Power Enable Signal Mapping table
    VDDCI Normal mode BACO mode Graville Whistler and Seymour
    +1.5VSG
    PX_EN 0 1 VGA_PWR_ON source signal INT_VGAPWR_ON VGA_ON
    +1.5VSG
    +1.0VSG 1.5_VDDC_PWREN 1 0 +3.3VSG VGA_PWR_ON SUSP#
    +1.0VSG VDDC_EN 1 0 +1.8VSG VGA_PWR_ON VGA_PWR_ON
    +1.8VSG 20ms 1.0_EN 0 1 +1.0VSG VGA_PWR_ON VGA_PWR_ON
    +1.8VSG 20ms +3.3VSG ON ON +VDDCI VGA_PWR_ON Combine with +VGA_CORE
    +1.8VSG ON ON +VGA_CORE VGA_PWR_ON 1.5_VDDC_PWREN
    For PX sequence, >1mS delay is required between +1.0VSG ON ON +1.5VSG VGA_PWR_ON 1.5_VDDC_PWREN
    PE_GPIO1 and VGA_PWR_ON +VGA_CORE ON OFF
    +1.5VSG ON OFF WOBACO@
    R107 1 2 0_0402_5%
    +BIF_VDDC +VGA_CORE +1.0VSG +3VS C207 BACO@
    PE_GPIO1 0.1U_0402_10V7K
    1 2
    C C

    VGA_PWR_ON >1ms U10

    5
    BACO@
    VGA_PWR_ON 2

    P
    B 1.5_VDDC_PWREN
    Y 4 1.5_VDDC_PWREN <35,43>
    +3VS R108 1 2 10K_0402_5% 1 A

    G
    BACO@
    NC7SZ08P5X_NL_SC70-5
    VGA Power ON Circuit

    3
    1
    D

    <22> PX_EN 1 BACO@ 2 2


    R77 0_0402_5% G Q2

    1
    +3VALW +3VALW S BACO@

    3
    R110 2N7002_SOT23
    VGA@ VGA@ 5.11K_0402_1%
    U11A U11B BACO@ +5VS +5VS
    SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
    14

    14

    2
    Delay SUSP# 10ms
    P

    2
    <31,35> VGA_ON 1 VAN@ 2 1
    I O
    2 3
    I O
    4 1 VAN@ 2
    R111 0_0402_5% 2 R170 0_0402_5% R112 R113
    G

    C208 BACO@ BACO@


    VGA@ For DVT 1011 1K_0402_5% 1K_0402_5%
    7

    0.1U_0402_16V4Z

    1
    1 VAN_GPIO1_DELAY VDDC_EN
    C209 BACO@ +3VS
    0.1U_0402_10V7K 1.0_EN
    2 1

    6
    DMN66D0LDW-7_SOT363-6
    Q3B

    DMN66D0LDW-7_SOT363-6
    Q3A
    U12

    5
    +3VALW +3VALW BACO@
    B 1.5_VDDC_PWREN B
    1 BACO@ 2 2

    P
    R114 0_0402_5% B
    4 5 2
    Y

    BACO@

    BACO@
    VGA@ VGA@ 1
    <13,43> VGA_PWRGD A

    G
    U11C U11D
    14

    14

    1
    Delay EC_PWROK 50ms SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 From +VGA_CORE regulator

    3
    NC7SZ08P5X_NL_SC70-5
    P

    <31> INT_VGAPWR_ON 1 MAN@ 2 5 6 9 8 1 MAN@ 2


    R115 0_0402_5% I O I O R171 0_0402_5%
    2
    G

    C210
    VGA@ For DVT 1011
    7

    0.1U_0402_16V4Z
    1 MAN_GPIO1_DELAY
    Q4 Q5 +BIF_VDDC +VGA_CORE
    2

    +1.0VSG AO3416_SOT23-3 AO3416_SOT23-3


    R116 20mil 30mil WOBACO@
    +3VS

    D
    +3VALW +3VALW 0_0402_5% 3 1 1 3 1 2

    S
    DISO@ BACO@ BACO@ R117 0_0805_5%
    C211
    VGA@ 1 1
    1
    1

    1 2 0.1U_0402_16V4Z C212 C239

    G
    2

    2
    R118 VGA@ VGA@ BACO@ BACO@
    31.6K_0402_1% U11E U11F 1.0_EN 10U_0603_6.3V6M
    14

    14

    R119 PX@ @ SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 2 2 10U_0603_6.3V6M


    10K_0402_1%
    For VGA Power on control
    P

    P
    2

    <13,35> PE_GPIO1 1 2 11
    I O
    10 13
    I O
    12 1 PX@ 2
    VGA_PWR_ON <25,35> Change 0603 size
    R120 VDDC_EN
    For DVT
    G

    2 0_0402_5% 2
    1

    D Q6 C213 C214
    7

    2
    G
    PX@ 2 PX@ VGA@ 0.1U_0402_16V4Z

    G
    <35> PE_GPIO1# 1 2
    R121 0_0402_5% G 0.1U_0402_16V4Z @ 30mil AO3416 NMOS
    2N7002_SOT23 1 1
    S 3 1 1 3 Vgs(th)(Max)= 1V
    3

    BACO@ BACO@

    S
    A Rds(on)(Max)= 22m ohm @Vgs=4.5V A
    +VGA_CORE Q7 Q8
    1

    D Q9 AO3416_SOT23-3 AO3416_SOT23-3
    VAN_GPIO1_DELAY 1 VAN@2 2 PX@
    R122 0_0402_5% G
    MAN_GPIO1_DELAY 1 MAN@ 2 2N7002_SOT23
    S
    3

    R123 0_0402_5%
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    VGA power sequence and BACO
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 24 of 46
    5 4 3 2 1
    5 4 3 2 1

    +3.3VS TO +3.3VSG 1.05VS TO +1.0VSG Change P/N SB00000GV00


    +1.05VS +1.0VSG
    +3VS +3VSG U13 VGA@
    SI4800BDY-T1-GE3_SO8
    1 VAN@ 2 8 1
    R124 0_0805_5% Change 0603 size 7 2

    2
    D Q10 6 3 1 1 D
    SI2301CDS-T1-GE3_SOT23-3 For DVT 1 1 5 C215 R125
    MAN@ Change 0603 size C216 C218 VGA@ VGA@

    S
    3 1 10U_0603_6.3V6M C217 470_0603_5%

    D
    For DVT

    4
    VGA@ VGA@ 2 2 VGA@

    1
    2

    2
    C219 1 2 2 1U_0402_6.3V4Z
    1
    MAN@ R126 MAN@ C220 R127 10U_0603_6.3V6M 10U_0603_6.3V6M

    G
    2
    D

    1
    MAN@ 470_0603_5% Change 0603 size

    3VSG_GATE
    0.1U_0603_25V7K 100K_0402_5% 10U_0603_6.3V6M MAN@ 2 VGA_PW R_ON#
    2 2 For DVT G

    1
    3VSG_GATE 1 2 +VSB 2 VGA@ 1 1.0VSG_GATE S Q11 VGA@

    3
    R128 33K_0402_5% R129 10K_0402_5% 2N7002_SOT23
    D

    1
    MAN@ MAN@
    D 2 VGA_PW R_ON# VGA_PW R_ON# <35> D 1

    1
    MAN@ MAN@ G C221
    VGA_PW R_ON 1 Q13 S Q12 VGA_PW R_ON# 2 VGA@ 1 VGA@

    510K_0402_5%
    <24,35> VGA_PW R_ON 2 2 2

    1
    @ R132
    10K_0402_5% R130 1 G 2N7002_SOT23 R131 100K_0402_5% G 0.1U_0603_25V7K
    S Q14 S 2
    1

    3
    C222 SSM3K7002FU_SC70-3 2N7002_SOT23
    MAN@ C223 VGA@
    2
    0.1U_0603_25V7K VGA@

    2
    2
    0.1U_0603_25V7K
    D

    1
    2N7002_SOT23
    ACIN 2 VGA@
    <31,35,37> ACIN
    G Q15
    S

    3
    C C

    +1.5V TO +1.5VSG +1.8VS TO +1.8VSG Change P/N SB00000GV00


    +1.8VS +1.8VSG
    U15 VGA@
    +1.5V +1.5VSG SI4800BDY-T1-GE3_SO8
    U14 VGA@ 8 1
    SI4800BDY-T1-GE3_SO8 Change 0603 size 7 2

    2
    8 1 6 3 1 1
    Change 0603 size 7 2
    For DVT 1 1 5 C227 R134

    2
    6 3 1 1 C226 C229 VGA@ VGA@
    For DVT 1 1 5 C224 C225 R133 10U_0603_6.3V6M C228 470_0603_5%

    4
    C230 C231 VGA@ VGA@ VGA@ VGA@ VGA@ 2 2 VGA@

    1
    VGA@ 10U_0603_6.3V6M 1U_0402_6.3V4Z 470_0603_5% 2 2 1U_0402_6.3V4Z
    4

    VGA@ 2 2 10U_0603_6.3V6M 10U_0603_6.3V6M

    1
    D

    1
    2 2
    Change 0603 size
    10U_0603_6.3V6M 10U_0603_6.3V6M 2 VGA_PW R_ON#
    Change 0603 size
    D
    1
    For DVT G
    2 1.5_VDDC_PW REN# 1.5_VDDC_PW REN# <35> +VSB 2 VGA@ 1 1.8VSG_GATE S Q16 VGA@
    For DVT

    3
    G R135 100K_0402_5% 2N7002_SOT23
    +VSB 1 VGA@ 2 1.5VSG_GATE S Q17
    3

    R136 100K_0402_5% 2N7002_SOT23

    510K_0402_5%
    D 1

    1
    @ R138
    VGA@ C232
    B VGA_PW R_ON# 2 VGA@ 1 VGA@ B
    D 1 2
    1

    VGA@ R140 C233 R137 100K_0402_5% G 0.1U_0603_25V7K


    1.5_VDDC_PW REN# 2 VGA@ 1 VGA@ VGA@ Q18 S 2
    2 1

    3
    R139 47K_0402_5% G 510K_0402_5% 0.1U_0603_25V7K 2N7002_SOT23

    2
    Q19 S 2 C234 VGA@
    3

    1 2N7002_SOT23 VGA@
    2

    1
    C235 2
    0.1U_0603_25V7K Q20
    VGA@ ACIN 2 VGA@
    D
    1

    0.1U_0603_25V7K Q21 G 2N7002_SOT23


    2 ACIN 2 VGA@ S

    3
    G 2N7002_SOT23
    S
    3

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    VGA DC Interface
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 25 of 46
    5 4 3 2 1
    5 4 3 2 1

    R1138 5.1K_0402_5% Pin23 Function:


    U70 1 2 1.CLKREQ Close LAN chip 1 overclocking
    C907 1 2 0.1U_0402_16V4Z PCIE_FRX_C_DTX_N0 29 38 LAN_ACTIVITY 2.AR8152L revA PH: R1140 49.9_0402_1% LAN_ACTIVITY
    <13> PCIE_FRX_DTX_N2 TX_N LED_0 LAN_LINK# LAN_MDI0+ 1@ 2 C1466 1000P_0402_50V7K 0* Un-overclocking
    C908 1 2 0.1U_0402_16V4Z PCIE_FRX_C_DTX_P0 30
    Atheros LED_1 39
    23 LED2_CKR# 1 2 LAN_CLKREQ#
    1 2
    R1142 49.9_0402_1%
    <13> PCIE_FRX_DTX_P2 TX_P LED_2
    8151-AL1A R1139 8152@ 0_0402_5% LAN_MDI0- 1 2 1 2 C1467 0.1U_0402_16V4Z 1* SWR mod
    36 R1145 49.9_0402_1% LAN_LINK#
    <13> PCIE_FTX_C_DRX_N2 RX_N LAN_MDI0- LAN_MDI1+
    TRXN0 12 1 2 1@ 2 C1468 1000P_0402_50V7K 0 LDO mode
    35 11 LAN_MDI0+ R1147 49.9_0402_1% * default
    <13> PCIE_FTX_C_DRX_P2 RX_P TRXP0 LAN_MDI1- LAN_MDI1-
    TRXN1 15 1 2 1 2 C1469 0.1U_0402_16V4Z
    CLK_PCIE_LAN# 32 14 LAN_MDI1+ R1149 49.9_0402_1%
    <13> CLK_PCIE_LAN# CLK_PCIE_LAN REFCLK_N TRXP1 LAN_MDI2- LAN_MDI2+
    <13> CLK_PCIE_LAN 33
    REFCLK_P TRXN2
    18 1 8151@ 2 1@ 2 C1470 1000P_0402_50V7K
    17 LAN_MDI2+ R1151 49.9_0402_1%
    R909 1 TRXP2 LAN_MDI3- LAN_MDI2-
    <13,18,29> PLT_RST# 2 0_0402_5% 2
    PERST# TRXN3
    21 1 8151@ 2 1 2 C1471 0.1U_0402_16V4Z
    D LAN_MDI3+ R1153 49.9_0402_1% D
    TRXP3
    20 8151@
    R1143 1 @ 2 0_0402_5% LAN_PME# 3 LAN_MDI3+ 1 8151@ 2 1@ 2 C1472 1000P_0402_50V7K
    <14,29> FCH_PCIE_WAKE# WAKE#
    <31> EC_PME# R1144 1 2 0_0402_5% R1146 2.37K_0402_1% R1154 49.9_0402_1%
    +3V_LAN 25 10 2 1 LAN_MDI3- 1 8151@ 2 1 2 C1473 0.1U_0402_16V4Z
    SMCLK RBIAS
    26
    SMDATA R1146 keep away other singal (25mil) 8151@
    1 @ 2 PLT_RST#
    R1148 4.7K_0402_5% 28 1 +3V_LAN
    LAN_PME# TEST_RST VDD33
    1 2 27
    TESTMODE
    R1150 4.7K_0402_5% W=40mils W=40mils
    1 2 LAN_CLKREQ# 40 LX W=40mils
    R1152 4.7K_0402_5% LAN_X2 LX L108
    7
    LAN_X1 XTLO LX +1.7V_VDDCT
    8 XTLI 1 2
    5 +1.7V_VDDCT
    8151@ VDDCT 4.7UH_PG031B-4R7MS_1.1A_20%
    <14> LAN_CLKREQ# LAN_CLKREQ# 1 R1155 2 0_0402_5% 1.8V_VDDCT_REG 4 1 1 2 1
    8152@ CLKREQ# +1.1V_DVDDL C1481 C1482 C1483 C1484
    DVDDL 24 W=30mils
    0.1U_0402_16V4Z 1 2 C1474 37
    DVDDL_REG 0.1U_0402_16V4Z 10U_0603_6.3V6M 1000P_0402_50V7K0.1U_0402_16V4Z
    13 AVDDL
    19 2 2 1 2
    AVDDL
    31 AVDDL AVDDH 16 R1156 1 8151@ 2 0_0603_5% +2.7V_AVDDH W=30mils
    +1.1_AVDDL
    W=30mils 34 AVDDL AVDDH 22
    6 AVDDL_REG AVDDH_REG 9

    1 1 1 1 1 1 close to Lan pin5 close to Lan pin40


    41 U70
    C1475 C1476 C1477 C1478 C1479 C1480 GND

    2
    8151@ 2 8151@ 2 2 2 2 AR8151-AL1A_QFN40_5X5 W=30mils W=30mils
    8152@
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V6K 8151@ +2.7V_AVDDH +1.1V_DVDDL
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z AR8151-AL1B PN:SA00003LE30 AR8152-AL1E C1494
    AR8152-AL1E PN:SA00003JW10

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    C
    1 1 1 1 1 1 1 C
    close to pin13 close to pin31 C1495 C1487 C1488 C1489
    SA00003JW10 C1496 C1497
    close to pin19 close to pin34 close to pin6 1U_0402_6.3V6K 8151@ 1U_0402_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    2 2 2 2 2 2 2

    Y6 0.1U_0402_16V4Z
    LAN_X11 2 LAN_X2

    25MHZ_20PF_7A25000012
    W=40mils close to Lan pin9 close to Lan pin22 close to Lan pin16 close to Lan pin37 close to Lan pin24
    2

    C1485 C1486
    33P_0402_50V8K 33P_0402_50V8K
    1

    +3V_LAN

    R1157 1
    1A
    +3VALW 2 0_0603_5%
    Change Y6 P/N as SJ100003300
    C1490 C1491 C1492 C1493
    Follow result by vender 10/11 1 1 1 1

    JRJ45
    2 2 2 2 R1158 1
    +3V_LAN 2 0_0402_5% 9
    10U_0603_6.3V6M 1U_0402_6.3V6K Green LED+
    T25 10U_0603_6.3V6M 0.1U_0402_16V4Z LAN_LINK# 2 1 10
    R1159 511_0402_1% Green LED-
    RJ45_MDI0+ 1 14
    8152@ PR1+ SHLD1
    1 13
    C1498 RJ45_MDI0- SHLD2
    close to Pin 1 2
    PR1-
    @
    BOTH_TST1284 470P_0402_50V7K RJ45_MDI1+ 3
    2 PR2+
    B RJ45_MDI2+ B
    SP050001X10 T25
    4
    PR3+
    0_0603_5% RJ45_MDI2- 5
    +1.7V_VDDCT PR3-
    1 2 1 24
    R1160 LAN_MDI3+ TCT1 MCT1 RJ45_MDI3+ RJ45_MDI1-
    2 23 6
    LAN_MDI3- TD1+ MX1+ RJ45_MDI3- PR2-
    3 22
    TD1- MX1- RJ45_MDI3+ 7
    PR4+
    4 21
    LAN_MDI2+ TCT2 MCT2 RJ45_MDI2+ RJ45_MDI3-
    5 20 8
    LAN_MDI2- TD2+ MX2+ RJ45_MDI2- PR4-
    6 19
    TD2- MX2- LAN_ACTIVITY 2 1 11
    LAN_ACTIVITY Yellow LED+
    7 18
    LAN_MDI1+ TCT3 MCT3 RJ45_MDI1+ LAN_LINK# LANGND R1161 511_0402_1%
    8 17 1 12
    LAN_MDI1- TD3+ MX3+ RJ45_MDI1- C1499 Yellow LED-
    9 16
    TD3- MX3- @
    470P_0402_50V7K SANTA_130451-K
    10 15
    LAN_MDI0+ TCT4 MCT4 RJ45_MDI0+ 2 CONN@
    11 14
    TD4+ MX4+
    3

    2
    LAN_MDI0- 12 13 RJ45_MDI0-
    TD4- MX4- D47 D51
    PJDLC05C_SOT23-3 PJDLC05C_SOT23-3
    @ RJ45_GND 1 2 LANGND 40mil
    @
    350UH_IH-037-2
    8151@ C940

    2
    1000P_1206_2KV7K
    R819 75_0402_1% L109
    1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 75_0402_1% R820 100UH +-20% SSC0301101MCF 0.18A
    1

    1
    1

    1 1 1 1 1 1 1 1 1 8151@
    C1503 C1504 C1505 C1506 C1507 C1508 C1509 C1510 C1511
    @ @ 8151@ @ 8151@ @ @ R821 R822 D49 @

    1
    1U_0402_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 75_0402_1% 75_0402_1% B88069X9231T203_4P5X3P2-2
    2 2 2 2 2 2 2 2 2 8151@
    2

    A RJ45_GND
    40mil A
    close to pin1 close to pin4 close to pin7 close to pin10
    8151@ Populate when AR8151-AL1A
    2

    2 8152@ Populate when AR8152-AL1E For EMI Request


    Place close to TCT pin C941
    1000P_1206_2KV7K
    @
    @ 1
    D48
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title
    1

    B88069X9231T203_4P5X3P2-2
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    LAN AR8151 / AR8152
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    Custom LA-7092P P5WE6/H6/S6 0.3
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    For EMI Request Date: Friday, October 29, 2010 Sheet 26 of 46

    5 4 3 2 1
    A B C D E F G H

    +3VS +5VS_AVDD

    1
    1

    1
    R783
    D38 20K_0402_1%
    R789
    CH751H-40PT_SOD323-2 10K_0402_5%

    2
    C936

    2
    1 2 MONO_IN
    1U_0402_6.3V4Z
    1 1
    1 R786 2
    15.4K_0402_1%

    1
    C
    R787
    C952 1 2 1 2 2 Q72 Dos Beep issue for PVT 10/28
    <31> BEEP#
    1U_0402_6.3V4Z
    560_0402_5%
    B
    E
    HD Audio Codec

    3
    2SC2411KT146_SOT23-3

    C946 1 R788
    2 1 2
    <14> FCH_SPKR 1U_0402_6.3V4Z

    1
    560_0402_5%
    D37
    CH751H-40PT_SOD323-2

    Change 0603 size Layout Note: Path from +5V to LPWR_5.0 and

    2
    RPWR_5.0 must be very low resistance ( <0.01 ohms).
    For DVT Place bypass caps very close to device.
    20mil
    R1093 0_0603_5% 80mil R1162 0_0603_5%
    +3VS 1 2 +3VS_DVDD +5VS_AVDD 1 2 +5VS
    1 1 1 Change 0603 size 1 1
    +MIC2_BIASC
    C1512 0.1U_0402_16V4Z C1210 C1211
    For DVT

    1
    C1513 C1514 1 2
    10U_0603_6.3V6M 0.1U_0402_16V4Z R1163 10U_0603_6.3V6M 0.1U_0402_16V4Z R1164 0_0603_5%
    +3VS_AUX 2 2 2 2 2
    10mil

    1
    0.1_1206_1%
    1 2 +3VS_AUX R585
    +3VS

    2
    R1165 0_0402_5% 80mil 2.2K_0402_5%
    1 1 +CLASSD_5V
    C1515 C1517 1 1

    2
    0.1U_0402_16V4Z 10U_0603_6.3V6M C1516 C1518 1 1 1 1 1 Close to Conn
    2 C1519 C1520 C1521 C1522 C1523 INT_MIC 2
    2 2 1U_0402_6.3V6K 0.1U_0402_16V4Z
    2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0603_6.3V6M
    +3VS_AUX 2 2 2 2 2 1
    Change 0603 size
    +CLASSD_REF 0.1U_0402_16V4Z 10U_0603_6.3V6M C808
    For DVT 40mil 220P_0402_50V7K
    2
    Change 0603 size

    21

    29

    31

    15

    18

    20
    For DVT

    9
    U82

    VDD_IO
    VAUX_3.3

    DVDD_3.3

    LPWR5.0

    RPWR5.0

    CLASSDREF
    AVDD_HP

    AVDD_5V
    HP_LEFT 25
    <28> HP_LEFT PORTA_L
    JMIC2
    HP_RIGHT 26 INT_MIC 1
    <28> HP_RIGHT PORTA_R 1
    15mil 2
    2
    27
    PORTD_L SPKL+
    14 SPKL+ <28> 1 1
    SPK_OUT_L+ 220P_0402_50V7K 220P_0402_50V7K
    28 3
    PORTD_R SPKL- @ @ G1
    16 SPKL- <28> 4
    SPK_OUT_L- G2

    2
    33 C979 C980
    PORTE_L SPKR+ 2 2 ACES_88266-02001
    19 SPKR+ <28>
    SPK_OUT_R+ CONN@
    34
    PORTE_R SPKR-
    17 SPKR- <28>
    SPK_OUT_R- C794 4.7U_0603_6.3V6K
    41
    PORTF_L MIC2_C_L
    39 1 2
    PORTB_L INT_MIC_22 INT_MIC
    42 1
    PORTF_R MIC2_C_R R523 1K_0402_1%
    40 1 2
    +3VS_AUX PORTB_R C797 4.7U_0603_6.3V6K Change 0603 D27 @
    1 2 22

    1
    C1524 1U_0402_6.3V6K FLY_P PJDLC05C_SOT23-3
    38 +MIC2_BIASC
    Change 0603 B_BIAS size For DVT
    23 8 1 2 HDA_SDIN0 <14>
    size For DVT FLY_N SDATA_IN
    1

    R793 33_0402_5%
    R1166 4.7U_0603_6.3V6K 6 HDA_SDOUT_AUDIO
    3 SDATA_OUT HDA_SDOUT_AUDIO <14> 3
    MIC1_L C934 1 MIC1_C_L
    5.11K_0402_1% <28> MIC1_L 2 35
    PORTC_L
    SYNC
    10 HDA_SYNC_AUDIO
    HDA_SYNC_AUDIO <14>
    Port Configuration
    MIC1_R C932 1 2 MIC1_C_R 36
    <28> MIC1_R
    2

    PORTC_R HDA_RST_AUDIO#
    4.7U_0603_6.3V6K
    RESET#
    11 HDA_RST_AUDIO# <14> Port A: Headphone jack (jack shared with S/PDIF)
    37
    R1167
    +MIC1_BIASC C_BIAS
    7 HDA_BITCLK_AUDIO Port B: Internal MIC (mono or stereo)
    HP_PLUG# <28> BIT_CLK HDA_BITCLK_AUDIO <14>
    2 1 Port C: Microphone/LI/LO jack
    39.2K_0402_1%
    1 L112 2 1 2 C948
    Port D: Line Out jack (Optional)
    DMIC_3/4
    1 22P_0402_50V8J Port E: Line In jack (Optional)
    SENSE_A 2 1 MIC_PLUG# <28> MONO_IN 13 FBMA-10-100505-301T_2P
    PCBEEP Port F: Not used.
    2
    DMIC_CLK0 Port G: Internal stereo speakers
    R1168 10K_0402_5%
    <31> EC_MUTE#
    1 2 12
    EXT_MUTE# Pop For EMI 10/18
    R1169 0_0402_5% 3 Port J: Internal stereo digital mic (Optional)
    DMIC_1/2
    EC_MUTE# change as Pin12 Port H: S/PDIF (jack shared with headphone)
    Sense resistors must be
    connected same power
    that is used for VAUX_3.3 SENSE_A 44 46
    SENSE A GPIO1/SPK_MUTE#
    43 45
    SENSE B GPIO2/SPDIF2

    <31> EAPD 1 2 47
    GPIO0/EAPD#
    R796 0_0402_5% 10mil
    48 5 +FILT_1.8
    SPDIFO FILT_1.8

    1
    1 1
    +AVEE 24 32 +FILT_1.65V C1525 C1526 R1170
    AVEE FILT_1.65
    1 1 10mil
    C1528 C1529 49 30 +3VS_LDO_OUT 1 1 0.1U_0402_16V4Z 10U_0603_6.3V6M 10K_0402_5%
    EP_GND AVDD_3.3 2 2
    10mil C1527 C1530

    2
    0.1U_0402_16V4Z 10U_0603_6.3V6M CX20584-11Z_QFN48_7X7 1 1 R1170 only needed if supply to VAUX_3.3 is
    2 2 C1531 C1532 1U_0603_10V6K 0.1U_0402_16V4Z removed during system re-start.
    J4 2 2
    4
    J1 Change 0603 size 4
    1 2 1 2 0.1U_0402_16V4Z 10U_0603_6.3V6M
    1 2 1 2
    Change 0603 size 2 2 For DVT
    JUMP_43X39 @ JUMP_43X39 @
    J2 J5 For DVT
    1 1 2 2 1 1 2 2 Change 0603 size
    JUMP_43X39 @ JUMP_43X39 @ For DVT
    J3 J6
    1 1 2 2 1 1 2 2
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title
    JUMP_43X39 @ JUMP_43X39 @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    HD Audio Codec CX20584
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 0.3
    GND GNDA GND GNDA
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 27 of 46
    A B C D E F G H
    A B C D E

    Int. Speaker Conn.

    1 JSPK2 1

    <27> SPKL+ SPKL+ R834 1 2 0_0603_5% SPK_L+ 1


    SPKL- R833 1 SPK_L- 1
    <27> SPKL- 2 0_0603_5% 2
    2
    30mil Left

    2
    D39 3
    G1
    2 2 4
    C1533 C1534 G2
    @ @ ACES_88266-02001
    1000P_0402_50V7K CONN@
    1 1
    1000P_0402_50V7K

    1
    PJDLC05C_SOT23-3

    JSPK1
    <27> SPKR+ SPKR+ R831 1 2 0_0603_5% SPK_R+ 1
    SPKR- R832 1 SPK_R- 1
    <27> SPKR- 2 0_0603_5% 2 2
    30mil Right

    2
    D41 3 G1
    2 2 4 G2
    C1535 C1536
    @ @ ACES_88266-02001
    1000P_0402_50V7K CONN@
    1 1
    1000P_0402_50V7K

    1
    PJDLC05C_SOT23-3
    2 2

    2 2
    C779 C774
    Headphone Out
    330P_0402_50V7K 330P_0402_50V7K
    1 1 JHP1
    1
    <27> HP_LEFT 1 2 HPOUT_L_1 1 2 HPOUT_L_2 2
    R686 39_0603_1% L94 FBMA-L11-160808-700LMT_2P
    <27> HP_RIGHT 1 2 HPOUT_R_1 1 2 HPOUT_R_2 3
    R685 39_0603_1% L93 FBMA-L11-160808-700LMT_2P
    4
    HP_PLUG# 5
    <27> HP_PLUG#

    SINGA_2SJ-0960-C01
    3 CONN@ 3
    MIC_PLUG# <NAL00 use>
    HP_PLUG#

    2
    +MIC1_BIASC +MIC1_BIASC @
    D24
    PJDLC05C_SOT23-3

    2
    D43 D42
    CH751H-40PT_SOD323-2 CH751H-40PT_SOD323-2

    1 1

    1 1

    1
    MIC JACK
    R692 R693
    3.01K_0402_1% 3.01K_0402_1%
    JMIC1

    2
    1
    1 2 MIC1_L_1 L89 1 2 MIC1_L_R 2
    <27> MIC1_L
    R694 100_0603_1% FBMA-L11-160808-700LMT_2P
    1 2 MIC1_R_1 L90 1 2 MIC1_R_R 3
    <27> MIC1_R
    R695 100_0603_1% FBMA-L11-160808-700LMT_2P

    2
    1 1 @ 4
    D29
    C780 C781 MIC_PLUG# 5
    <27> MIC_PLUG#
    220P_0402_50V7K 220P_0402_50V7K
    2 2
    PJDLC05C_SOT23-3
    6
    4 4
    SINGA_2SJ-A960-C01

    1
    CONN@
    <NAL00 use>

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Amplifier & Audio Jack
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 28 of 46
    A B C D E
    A B C D E

    Mini-Express Card for WLAN


    +3VS +1.5VS

    1 1 1 1 1 1
    C705 C706 C707 C708 C709 C710

    4.7U_0603_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z


    2 2 2 2 2 2
    Change 0603 size Change 0603 size
    For DVT For DVT
    JMINI1
    FCH_PCIE_WAKE# R440 1 @ 2 0_0402_5% 1 2 +3VS
    1 <14,26> FCH_PCIE_WAKE# 1 2 1
    3 4
    3 4
    5 6 +1.5VS
    5 6
    <14> MINI1_CLKREQ# 7
    7 8
    8 Mini Card Power Rating
    9 10
    9 10
    <13> CLK_PCIE_MINI1# 11
    11 12
    12 Power Primary Power (mA) Auxiliary Power (mA)
    <13> CLK_PCIE_MINI1 13 14
    13 14
    15
    15 16
    16 Peak Normal Normal
    +3VS 1000 750
    17 18
    17 18 WL_OFF#
    19
    19 20
    20
    PLT_RST#
    WL_OFF# <31> +3V 330 250 250 (wake enable)
    21 22 PLT_RST# <13,18,26>
    21 22 +3V_WLAN
    <13> PCIE_FRX_DTX_N3 23
    23 24
    24 1 2 +3VS +1.5VS 500 375 5 (Not wake enable)
    25 26 R441 1 2 0_0603_5% +3VALW
    <13> PCIE_FRX_DTX_P3 25 26
    27 28 R442 @ 0_0603_5%
    27 28 MINI1_SMBCLK @
    29 30 1 2 FCH_SMCLK0 <8,9,14>
    29 30 MINI1_SMBDAT R443 @ 0_0603_5%
    <13> PCIE_FTX_C_DRX_N3 31 32 1 2 FCH_SMDAT0 <8,9,14>
    31 32 R444 0_0603_5%
    <13> PCIE_FTX_C_DRX_P3 33 34
    33 34
    35 36 USB20_N8 <14>
    35 36
    37 38 USB20_P8 <14>
    37 38
    +3VS 39 40
    39 40 WIMAX_LED#
    41 42 (MINI1_LED#)
    41 42 WLAN_LED#_L +3VS
    43 44
    43 44
    45 46
    0_0402_5% 45 46
    47 48
    47 48

    1
    R445 1 2 E51TXD_P80DATA_R 49 50
    <31> E51TXD_P80DATA 49 50
    E51RXD_P80CLK 51 52 0_0402_5%
    <31> E51RXD_P80CLK 51 52 R835 1 2 R848
    +3VS 100K_0402_5%

    G1
    G2
    G3
    G3

    2
    2

    ACES_88910-5204

    53
    54
    55
    56
    R492 CONN@ WIMAX_LED# 2
    100K_0402_5% 1 MINI1_LED# <31>
    1 @ 2 WLAN_LED#_L 3
    <NAV70 use> R836 10K_0402_5%
    (9~16mA)
    1

    CHP202UPT_SOT323-3
    D44 @
    2
    Height : 4mm 1 2 2
    R837 0_0402_5%

    Card Reader RTS5138 / RTS5137


    (only SD+MMC function)
    Card Reader Connector

    3 +3VS +3VS_CR 3

    R854
    30mil
    1 2 0_0805_5%

    2 1 10mil +SDPWR_MMCPWR
    C981 100P_0402_50V8J U84 5IN1_LED# 5IN1_LED# <32>
    R855 1 2 RREF 1
    6.2K_0603_1% REFE @ C982 1
    17 1 2 2 10P_0402_50V8J JCR1
    USB20_N6 GPIO0 R856 10_0402_5% @ XDD4_SDD3_MSD1
    <14> USB20_N6 2 1
    USB20_P6 DM CLK_SD_48M_R XDD2_SDCMD D3
    <14> USB20_P6 3 24 2 1 CLK_SD_48M <13> 2
    DP CLK_IN R857 22_0402_5% CMD
    3
    +3VS_CR VSS1
    4 23 4
    +CARDPWR 3V3_IN XD_D7 XDD0_SDCLK_MSD2 VDD
    30mil VREG
    5
    CARD_3V3
    5
    CLK
    1 2 6 22 6
    C984 V18 SP14 XDD5_SDD2_MS_D5 VSS2
    C983
    1
    C985
    10mil SP13
    21
    XDD4_SDD3_MSD1 +CARDPWR +SDPWR_MMCPWR XDCLE_SDD0
    7 20 7
    4.7U_0603_6.3V6K 1U_0402_6.3V6K XD_CD# SP12 XDCE#_SDD1 D0
    19 8
    2 1 XDDRY_SDWP_MSCLK SP11 XDD2_SDCMD XDD5_SDD2_MS_D5 D1
    2
    8
    SP1 SP10
    18 30mil 30mil XDDRY_SDWP_MSCLK
    9
    D2
    Change 0603 size 0.1U_0402_16V4Z 9 16 1 2 10
    XDCE#_SDD1 SP2 SP9 XDD0_SDCLK_MSD2 R858 0_0805_5% XDWE#_SDCD# WP
    10 15 11
    For DVT SP3 SP8 CD
    EPAD

    XDCLE_SDD0 11 14
    SP4 SP7
    2

    12 13 XDWE#_SDCD# @ 1 1 1
    SP5 SP6
    RTS5138-GR_QFN24_4X4 R859 C986 C987 C988
    25

    100K_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z


    2 2 2
    1

    C987, C988 close to connector 12


    GND1
    Change to RTS5137 (SA000043500) 13
    GND2

    TAITW_PSDBTC09GLBS1N14N0
    CONN@

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    MINI CARD / CardReader RTS5137
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 29 of 46
    A B C D E
    A B C D E F G H

    SATA HDD Conn.


    JHDD1

    1 GND
    <15> SATA_ITX_DRX_P0 SATA_ITX_DRX_P0 2
    SATA_ITX_DRX_N0 A+
    <15> SATA_ITX_DRX_N0 3 A-
    4
    SATA_DTX_C_IRX_N0 C657 1 SATA_DTX_IRX_N0 GND
    2 0.01U_0402_16V7K 5
    <15> SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 C659 1 SATA_DTX_IRX_P0 B-
    2 0.01U_0402_16V7K 6
    B+
    1 <15> SATA_DTX_C_IRX_P0 1
    7
    GND
    +3VS
    +3VS 8
    V33
    1 9
    C639 V33
    10
    V33
    11
    0.1U_0402_16V4Z GND
    12
    2 GND
    13
    GND
    14
    V5
    15
    R405 1 +5VS_HDD V5
    +5VS 2 0_0805_5% 16 V5
    17 GND
    18 Reserved
    10U_0603_6.3V6M 0.1U_0402_16V4Z 19 GND
    20 V12
    1 1 1 1 21 V12 GND 24
    C660 C661 C662 C663 22 23
    V12 GND

    2 2 2 2 SANTA_192301-1
    Change 0603 size CONN@
    1U_0402_6.3V4Z 1000P_0402_50V7K
    For DVT
    <NAV70 use>

    2 2

    SATA ODD FFC Conn.

    JODD1
    1
    1
    <15> SATA_ITX_DRX_P1 2
    2
    <15> SATA_ITX_DRX_N1 3
    3
    4
    C650 1 SATA_DTX_IRX_N1 4
    2 0.01U_0402_16V7K 5
    <15> SATA_DTX_C_IRX_N1 C651 1 SATA_DTX_IRX_P1 5
    2 0.01U_0402_16V7K 6
    <15> SATA_DTX_C_IRX_P1 R412 1 @ 0_0402_5% ODD_DA#_FCH_R 6
    2 7
    <14> ODD_DA#_FCH R403 1 @ 0_0402_5% 7
    <14> ODD_DETECT# 2 8
    8
    9
    9
    10
    10
    80mils +5VS_ODD
    11
    11 GND
    13
    +5VS 1 2 12 14
    R955 0_0805_5% 12 GND

    2
    R413 ACES_85201-1205N
    0_0402_5% CONN@

    1
    3 3

    +5VS
    +5VS_ODD

    +VSB
    U40 @
    SI4800BDY-T1-GE3_SO8
    8 1
    2

    1 7 2
    1U_0402_6.3V6K
    C812

    R760 6 3
    470K_0402_5% @ 5
    @
    2
    1

    ODD_EN
    1

    D
    1.5M_0402_5%
    R764

    0.1U_0402_25V6K
    C811

    1
    2 Q66
    <15> ODD_PWR
    G SSM3K7002FU_SC70-3 @
    @ S @
    3

    2
    1

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    HDD & ODD CONN
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 30 of 46
    A B C D E F G H
    5 4 3 2 1

    +3VALW For EC Tools


    L84
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 2+EC_VCCA +3VALW
    1 1 C725 1 1 2 2
    1
    BLM18AG601SN1D_2P JP7 Place on MiniCard door
    C724 1 1
    C726 C727 C728 C729 1 E51RXD_P80CLK
    2 2 E51RXD_P80CLK <29>
    1000P_0402_50V7K 1000P_0402_50V7K C730 3 E51TXD_P80DATA
    KSO[0..17] 2 2 2 2 1 1 3 E51TXD_P80DATA <29>
    KSO[0..17] <32> 4 4
    2

    ECAGND
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    KSI[0..7] ACES_85205-0400
    KSI[0..7] <32>
    @
    D D
    +3VALW

    111
    125
    22
    33
    96

    67
    U26

    9
    65W /90W # 2 1
    R458 100K_0402_5%

    VCC
    VCC
    VCC
    VCC
    VCC
    VCC

    AVCC
    VR_ON 2 1
    R459 100K_0402_5%
    3S/4S# 1 2
    EC_GA20 1 21 R460 4.7K_0402_5%
    <14> EC_GA20 EC_KBRST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F BEEP#
    <14> EC_KBRST# 2 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 23 BEEP# <27>
    SERIRQ 3 26
    <13> SERIRQ LPC_FRAME# SERIRQ# FANPWM1/GPIO12 ACOFF
    <13> LPC_FRAME# 4 LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF <36,37>
    C732 LPC_AD3 5 2 1 ECAGND
    <13> LPC_AD3 LAD3
    @ 22P_0402_50V8J @ LPC_AD2 7 PWM Output C731 0.01U_0402_16V7K
    <13> LPC_AD2 LAD2
    2 1 2 1 LPC_AD1 8 63 BATT_TEMP
    <13> LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <39>
    R461 33_0402_5% LPC_AD0
    <13> LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
    ADP_I
    Analog Project ID definition
    ADP_I/AD2/GPIO3A 65 ADP_I <37>
    LPC_CLK0_EC 12 AD Input 66 AD_BID0 +3VALW
    <13> LPC_CLK0_EC PCICLK AD3/GPIO3B
    13 75 AD_PID0
    <13> A_RST# PCIRST#/GPIO05 AD4/GPIO42 Project_ID : 0->
    37 ECRST# SELIO2#/AD5/GPIO43 76

    2
    EC_SCI# 20 1->
    <14> EC_SCI# SCI#/GPIO0E 2->
    +3VALW 2 1 38 R463
    CLKRUN#/GPIO1D
    R462 47K_0402_5%
    DAC_BRIG/DA0/GPIO3C 68 DAC_BRIG
    DAC_BRIG <10> Ra @
    2 1 70 EN_DFAN1 100K_0402_5%
    EN_DFAN1/DA1/GPIO3D EN_DFAN1 <34>
    C733 0.1U_0402_16V4Z DA Output 71 IREF
    IREF <37>

    1
    IREF/DA2/GPIO3E

    2
    +5VS KSI0 55 72 CALIBRATE# AD_PID0
    KSI0/GPIO30 DA3/GPIO3F CALIBRATE# <37>
    @ KSI1 56 KSI1/GPIO31

    2
    R489 KSI2 57 1
    KSI2/GPIO32
    1 2 TP_CLK 10K_0402_5% KSI3 58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE#
    EC_MUTE# <27> Rb R464 C734
    C R465 4.7K_0402_5% KSI4 59 84 C
    1

    TP_DATA KSI5 KSI4/GPIO34 PSDAT1/GPIO4B 8.2K_0402_5% 0.1U_0402_16V4Z


    1 2 60 KSI5/GPIO35 PSCLK2/GPIO4C 85
    R466 4.7K_0402_5% KSI6 2
    61 PS2 Interface 86

    1
    KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK
    62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK <32>
    KSO0 39 88 TP_DATA
    KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <32>
    KSO1 40
    +3VALW +3VS KSO2 KSO1/GPIO21
    41 KSO2/GPIO22
    KSO3 42 97 3S/4S#
    KSO3/GPIO23 SDICS#/GPXOA00 3S/4S# <37>
    KSO4 43 98 65W /90W # Analog Board ID definition
    KSO4/GPIO24 SDICLK/GPXOA01 65W /90W # <37>
    KSO5 VLDT_EN
    44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 VLDT_EN <35>
    2

    @ @ KSO6 45 109 LID_SW # +3VALW


    R851 R852 KSO7 KSO6/GPIO26 Matrix SDIDI/GPXID0 LID_SW # <32>
    46 KSO7/GPIO27 SPI Device Interface
    0_0402_5% 0_0402_5% KSO8 47 Board_ID : 0->
    KSO8/GPIO28

    2
    KSO9 48 119 @ 1->
    KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO <32>
    KSO10 49 120 R469
    EC_SO_SPI_SI <32>
    1

    KSO10/GPIO2A SPIDO/WR#
    EC_SPICLK <32>Ra
    1 @ 2 EC_SMB_CK2 KSO11 50 SPI Flash ROM 126 1 L1112
    R467 2.2K_0402_5% KSO12 KSO11/GPIO2B SPICLK/GPIO58 100K_0402_5%
    51 KSO12/GPIO2C SPICS# 128 EC_SPICS#/FSEL# <32>
    1 @ 2 EC_SMB_DA2 KSO13 52 FBMA-10-100505-301T_2P

    1
    R468 2.2K_0402_5% KSO14 KSO13/GPIO2D C783 AD_BID0
    53 KSO14/GPIO2E
    KSO15 54 73 33P_0402_50V8K
    KSO15/GPIO2F CIR_RX/GPIO40

    2
    +3VALW KSO16 81 74
    KSO16/GPIO48 CIR_RLC_TX/GPIO41 1
    KSO17 82 89 R470 C735
    KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG <37> Rb
    1 2 EC_SMB_CK1 90 BATT_BLUE_LED#
    BATT_CHGI_LED#/GPIO52 BATT_BLUE_LED# <32>
    R471 2.2K_0402_5% 91 INT_VGAPW R_ON 8.2K_0402_5% 0.1U_0402_16V4Z
    EC_SMB_DA1 EC_SMB_CK1 CAPS_LED#/GPIO53 BATT_AMB_LED# INT_VGAPW R_ON <24> 2
    1 2 <39> EC_SMB_CK1 77 GPIO 92

    1
    R472 2.2K_0402_5% EC_SMB_DA1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 PW R_LED BATT_AMB_LED# <32>
    <39> EC_SMB_DA1 78 SDA1/GPIO45 SUSP_LED#/GPIO55 93 PW R_LED <32>
    KSO1 EC_SMB_CK2 SYSON
    1 2 <5,19> EC_SMB_CK2 79 SCL2/GPIO46 SM Bus SYSON/GPIO56 95 SYSON <35,40,42> Reserve for EMI, close to EC
    R473 47K_0402_5% EC_SMB_DA2 80 121 VR_ON
    <5,19> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <44>
    1 2 KSO2 127 ACIN
    B R474 47K_0402_5% AC_IN/GPIO59 ACIN <25,35,37> B

    2 1 LID_SW #
    R475 100K_0402_5% SLP_S3# 6 100 EC_RSMRST#
    <14> SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <14>
    1 @ 2 EC_PME# SLP_S5# 14 101 EC_LID_OUT#
    <14> SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# <14>
    R476 10K_0402_5% EC_SMI# 15 102 EC_ON
    <14> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <34,38>
    2 @ 1 PBTN_OUT# LOCAL_DIM 16 103 EC_SW I#
    <10> LOCAL_DIM LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SW I# <14>
    R497 100K_0402_5% MINI1_LED# 17 104 EC_PW ROK_R
    <29> MINI1_LED# SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF#
    18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# <10>
    COLOY_ENG_EN 19 GPIO 106 W L_OFF#
    <10> COLOY_ENG_EN EC_PME#/GPIO0D WL_OFF#/GPXO09 W L_OFF# <29>
    For LED INV_PWM freq to 1K EC_INVT_PW M 25 107
    <10> EC_INVT_PW M EC_THERM#/GPIO11 GPXO10
    FAN_SPEED1 28 108 VGA_ON <24,35> Delay SUSP# 10ms
    ENBKL <34> FAN_SPEED1 BT_ON# FAN_SPEED1/FANFB1/GPIO14 GPXO11
    2 1 <33> BT_ON# 29 FANFB2/GPIO15
    R488 100K_0402_5% E51TXD_P80DATA 30
    LOCAL_DIM E51RXD_P80CLK EC_TX/GPIO16 VGATE
    2 1 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 VGATE <14,44>
    R844 100K_0402_5% ON/OFF 32 112 ENBKL
    <34> ON/OFF ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL <10>
    2 1 COLOY_ENG_EN <32> PW R_SUSP_LED PW R_SUSP_LED 34 114 EAPD
    PWR_LED#/GPIO19 GPXID3 EAPD <27>
    R845 100K_0402_5% W LAN_LED# 36 GPI 115 EC_THERM# EC_PW ROK_R 1 2
    <32> W LAN_LED# NUMLED#/GPIO1A GPXID4 EC_THERM# <5> EC_PW ROK <14>
    116 SUSP# R254 0_0402_5%
    GPXID5 SUSP# <35,40,41>
    For Low PWR panel use 117 PBTN_OUT#
    GPXID6 EC_PME# PBTN_OUT# <14>
    GPXID7 118 EC_PME# <26>
    EC_CRY1 122
    RTC_CLK EC_CRY2 XCLK1
    <13,17> RTC_CLK 1 2 123 XCLK0 V18R 124
    R888 0_0402_5% 1
    AGND

    @ C736
    GND
    GND
    GND
    GND
    GND

    C737 100P_0402_50V8J
    EC_CRY1 EC_CRY2 4.7U_0603_6.3V6K BATT_TEMP 2 1
    1

    KB930QF A1 LQFP 128P 2


    11
    24
    35
    94
    113

    69

    2 2 R889 20mil Change 0603 size For DVT C741 100P_0402_50V8J


    A 100K_0402_5% ACIN 2 1 A
    1

    C739 C740 @ ECAGND 2 L85 1


    X1 15P_0402_50V8J
    OSC

    OSC

    15P_0402_50V8J 1 1 BLM18AG601SN1D_2P
    NC

    NC

    32.768KHZ_12.5PF_Q13MC14610002 Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title
    2

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    EC ENE KB930
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    B 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 31 of 46
    5 4 3 2 1
    5 4 3 2 1

    To TP/B Conn. +5VS

    +3VALW 1 2 C742 1 2 0.1U_0402_16V4Z JTP1


    R479 0_0603_5% 1
    1 +5VS
    2 2 TP_CLK <31>
    +SPI_VCC 3
    3 TP_DATA <31>
    4 LEFT_BTN#
    U27 4 RIGHT_BTN# C745
    <31> EC_SPICS#/FSEL# 5 5
    D EC_SPICS#/FSEL# 1 8 6 D
    R480 1 CS# VCC 6
    2 4.7K_0402_5% SPI_W P# 3 WP# SCLK 6 EC_SPICLK_R R481 1 2 0_0402_5% EC_SPICLK <31> 7 GND
    0.1U_0402_16V4Z
    +3VALW R482 1 2 4.7K_0402_5% SPI_HOLD# 7 5 8
    HOLD# SI EC_SO_SPI_SI <31> GND
    4 GND SO 2 EC_SI_SPI_SO <31>
    ACES_85201-0605N
    MX25L1605DM2I-12G SOP 8P CONN@
    SA000041N00

    RIGHT_BTN# TP_CLK
    SW 1 SW 2
    SMT1-05-A_4P SMT1-05-A_4P LEFT_BTN# TP_DATA
    LEFT_BTN# 3 1 RIGHT_BTN# 3 1

    2
    4 2 4 2 D11 D13

    5
    6

    5
    6
    PJDLC05C_SOT23-3
    PJDLC05C_SOT23-3

    1
    C JLED1 C

    1 1 +3VALW
    2 LID_SW # LID_SW # <31>
    2 W LAN_LED#
    3

    JKB1
    INT_KBD Conn. 3
    4 4
    5
    MEDIA_LED#
    +3VS
    W LAN_LED# <31>

    5 PW R_LED#
    6 6
    KSO0 26 28 7 ON/OFFBTN#
    KSO0 G2 7 ON/OFFBTN# <34>
    KSO1 25 27 8
    KSO2 KSO1 G1 8
    24 KSO2 GND 9
    KSO3 23 KSI[0..7] 10
    KSO3 KSI[0..7] <31> GND
    KSO4 22
    KSO5 KSO4 KSO[0..17] ACES_85201-08051 +3VS
    21 KSO5 KSO[0..17] <31> Pop R486 for RTS5137
    KSO6 20 CONN@
    KSO7 KSO6
    19 KSO7

    2
    KSO8 18 +3VS
    KSO9 KSO8 R486
    17 KSO9
    KSO10 16
    KSO11 KSO10 100K_0402_5%
    15 KSO11

    5
    KSO12 14 U29

    1
    KSO13 KSO12
    13 2

    P
    KSO13 B 5IN1_LED# <29>
    KSO14 12 MEDIA_LED# 4
    KSO15 KSO14 Y
    11 KSO15 A 1 SATA_LED# <15>

    G
    KSO16 10
    KSO17 KSO16 NC7SZ08P5X_NL_SC70-5
    9

    3
    KSI0 KSO17
    8 KSI0
    KSI1 7
    KSI2 KSI1 PW R_LED#
    6 KSI2
    KSI3 5 KSI3

    6
    B KSI4 LED1 B
    4 KSI4 +3VALW 1 2
    KSI5 3 R511 750_0402_1% HT-191NB5_BLUE
    KSI6 KSI5
    2 KSI6
    KSI7 1 <31> PW R_LED 2 DMN66D0LDW -7_SOT363-6 +3VS 1 @ 2 2 1 PW R_LED#
    KSI7 Q26A R477 750_0402_1% B

    2
    KSO16 C747 1 @ 2 100P_0402_50V8J

    1
    ACES_88747-2601 R487
    CONN@ KSO17 C748 1 @ 2 100P_0402_50V8J 100K_0402_5% LED2
    HT-191UD5_AMBER
    KSO15 C749 1 @ 2 100P_0402_50V8J KSO7 C750 1 @ 2 100P_0402_50V8J
    1 +3VALW 1 2 2 1 PW R_SUSP_LED#
    KSO14 C751 1 @ 2 100P_0402_50V8J KSO6 C752 1 @ 2 100P_0402_50V8J R478 3.01K_0402_1% A
    KSO13 C753 1 @ 2 100P_0402_50V8J KSO5 C754 1 @ 2 100P_0402_50V8J
    LED3
    KSO12 C755 1 @ 2 100P_0402_50V8J KSO4 C756 1 @ 2 100P_0402_50V8J HT-191NB5_BLUE
    PW R_SUSP_LED#
    +3VALW 1 2 2 1 BATT_BLUE_LED# BATT_BLUE_LED# <31>
    3

    KSI0 C757 1 @ 2 100P_0402_50V8J KSO3 C758 1 @ 2 100P_0402_50V8J R499 750_0402_1% B


    KSO11 C759 1 @ 2 100P_0402_50V8J KSI4 C760 1 @ 2 100P_0402_50V8J
    <31> PW R_SUSP_LED 5 DMN66D0LDW -7_SOT363-6 LED4
    KSO10 C761 1 @ 2 100P_0402_50V8J KSO2 C762 1 @ 2 100P_0402_50V8J Q26B HT-191UD5_AMBER
    2

    KSI1 C763 1 @ 2 100P_0402_50V8J KSO1 C764 1 @ 2 100P_0402_50V8J R490 +3VALW 1 2 2 1 BATT_AMB_LED# BATT_AMB_LED# <31>
    100K_0402_5% R498 3.3K_0402_5% A
    KSI2 C765 1 @ 2 100P_0402_50V8J KSO0 C766 1 @ 2 100P_0402_50V8J For PEW76/86/96 LED light,
    1

    A
    KSO9 C767 1 @ 2 100P_0402_50V8J KSI5 C768 1 @ 2 100P_0402_50V8J
    R477, R499 change as 750 ohm A

    R478 change as 3.01k ohm


    KSI3 C769 1 @ 2 100P_0402_50V8J KSI6 C770 1 @ 2 100P_0402_50V8J R498 change as 3.3k ohm
    KSO8 C771 1 @ 2 100P_0402_50V8J KSI7 C772 1 @ 2 100P_0402_50V8J
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    KB/TP/LED/SPI ROM/PWRb
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    B 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 32 of 46
    5 4 3 2 1
    A B C D E

    +USB_VCCA
    +3VALW SVPE, 4.2m, 18mohm
    Change P/N SF000003I00 +USB_VCCA

    1
    +5VALW 1

    1
    +USB_VCCA + C711
    U24 80mil R446 C712
    1 8 100K_0402_5% 220U_6.3V_M

    2
    GND VOUT 2
    2 VIN VOUT 7
    Change 0603 size 3 6 470P_0402_50V7K

    2
    VIN VOUT

    W=80mils
    EPAD
    1 4 5 R447 1 2 10K_0402_5%
    For DVT C713 EN FLG USB_OC0# <14>
    1 1

    4.7U_0603_6.3V6K 1 1 2

    9
    2 C714 R448 @ 0_0402_5%
    AP2301MPG-13_MSOP8 0.1U_0402_16V4Z
    2 L83 JUSB1
    <35> SYSON#
    USB20_N0 1 2 1
    <14> USB20_N0 1 2 1
    USB20_N0_R 2
    +3VALW USB20_P0_R 2
    3 3
    USB20_P0 4 3 4 <NAL00 use>
    <14> USB20_P0 4 3 4
    +5VALW 5 GND

    1
    +USB_VCCB R449 @ WCM2012F2S-900T04_0805 6
    U25 0_0402_5% GND
    80mil R450
    7 GND
    1 GND VOUT 8 1 2 USB_OC2# <14> 8 GND
    2 7 100K_0402_5% 1 2
    VIN VOUT R451 @ 0_0402_5% SUYIN_020133MB004S580ZL-C
    Change 0603 size 3 6

    2
    VIN VOUT

    EPAD
    1 4 5 1 2 CONN@
    For DVT C715 EN FLG R452
    USB_OC1# <14>
    10K_0402_5% 1
    4.7U_0603_6.3V6K C716
    2 9
    AP2301MPG-13_MSOP8 0.1U_0402_16V4Z
    2
    SYSON# D10
    USB20_N0_R 4 3 USB20_P0_R
    SA00003XM00 S IC AP2301MPG-13 MSOP 8P PWR SW
    2 2

    +USB_VCCA 5 2

    6 1

    To USB/B Connector PJUSB208_SOT23-6


    Change P/N SC300000O00 for ESD

    +USB_VCCB

    (Port 1,2) +3VALW +3VS


    JUSB2
    1
    Bluetooth Conn.
    1
    2 2
    3 1 BT@
    3 C718 C719
    4 4
    5 BT@
    5 USB20_N1 0.1U_0402_16V4Z BT@ 1U_0402_6.3V4Z
    6 6 USB20_N1 <14>

    3
    7 USB20_P1 S Q24 2
    7 USB20_P1 <14>
    3 8 1 BT@ 2 2 3
    8 <31> BT_ON# G
    9 USB20_N2 R453 10K_0402_5%
    9 USB20_P2 USB20_N2 <14> D AO3413L_SOT23-3
    10

    1
    10 USB20_P2 <14>
    13 GND 11 11
    14 12 C720 W=40mils
    GND 12 BT@ +BT_VCC
    0.1U_0402_16V4Z
    ACES_85201-1205N 1

    1
    CONN@ C721 BT@ C722 BT@ BT@
    R454
    +BT_VCC 4.7U_0603_6.3V6K 300_0603_5%
    <NAL00 use> Change 0603 size 2 0.1U_0402_16V4Z
    JBT1 For DVT

    2
    10 GND 8 8
    7 BT@
    7

    1
    D
    6 6 USB20_P7 <14>
    5 2 Q25
    5 USB20_N7 <14>
    4 G 2N7002_SOT23
    4
    3 S

    3
    3
    2 2
    9 GND 1 1
    ACES_87213-0800G
    CONN@

    <NAL00 use>
    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    USB/BT/USBsub
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 33 of 46
    A B C D E
    ON/OFF switch Power Button FAN1 Conn
    Change 0603 size +5VS
    +5VS For DVT
    +3VALW C821 10U_0603_6.3V6M
    TOP Side

    1
    1 2
    1 2 D25

    2
    R493 @ 10K_0603_5% @ 1SS355_SOD323-2

    2
    R566
    1 2 R495 0_0603_5%

    2
    R494 @ 10K_0603_5% @ U37 @ D26 BAS16_SOT23-3
    100K_0402_5% 1 8 1 2

    1
    EN GND
    Bottom Side 2 7

    1
    SW 3 D12 +VCC_FAN1 VIN GND
    3 VOUT GND 6
    SMT1-05-A_4P 2 ON/OFF <31> <31> EN_DFAN1 1 2 4 VSET GND 5 C823 Change 0603 size
    1 3 ON/OFFBTN# 1 R567 0_0402_5% 1 10U_0603_6.3V6M
    3 C822 APL5607KI-TRG_SO8 1 2
    For DVT
    51_ON# <36>
    2 4 @
    DAN202UT106_SC70-3 0.01U_0402_25V4Z +3VS C824
    Change to SC600000B00 2 1000P_0402_50V7K
    6
    5
    2 1 2

    1
    C773
    ON/OFFBTN# <32>
    R568
    1000P_0402_50V7K 10K_0402_5%
    1
    40mil JFAN1

    2
    +VCC_FAN1 1
    Bottom Side SW 4 D 1

    1
    <31> FAN_SPEED1 2 2 G1 4
    SMT1-05-A_4P EC_ON 2 Q27 3 5
    <31,38> EC_ON 3 G2

    2
    1 3 G 1
    R496 S 2N7002_SOT23 C825 CONN@

    3
    2 4 1000P_0402_50V7K ACES_85204-03001
    10K_0402_5%
    2
    6
    5

    H1 H2 H3 H4 H5 H7 H8 H10
    H_3P0 H_4P0 H_4P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

    1
    H11 H12 H19 H24 H20 H21 H22 H23
    H_3P0 H_3P0 H_3P0 H_3P0 H_4P2 H_4P2 H_4P2 H_4P2

    1
    H14 H18 H17 H13
    H_3P0 H_3P4 H_3P0X3P5N H_3P0N

    1
    FD1 FD2 FD3 FD4

    1
    FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Other IO/USB (right)
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 34 of 46
    A B C D E

    +5VALW TO +5VS +5VALW

    +5VALW
    Change P/N SB00000GV00 +1.1VALW TO +1.1VS +5VALW
    +5VS

    2
    U38 +1.1VALW +1.1VS
    Change 0603

    2
    SI4800BDY-T1-GE3_SO8 Change 0603 U39 R1108
    size For DVT 8 1 SI4800BDY-T1-GE3_SO8 R1111 100K_0402_5%
    7 2
    size For DVT 8 1 100K_0402_5%

    2
    6 3 1 1 7 2

    1
    2
    1 1 5 C1446 R1101 6 3 1 1

    1
    1
    C1443 C1445 470_0603_5% 1 5 C1447 R1102 VLDT_EN# SYSON#
    <33> SYSON#
    10U_0603_6.3V6M C1444 R1104 C1448

    1
    10U_0603_6.3V6M 2 2 1K_0402_5% 10U_0603_6.3V6M C1449 470_0603_5% D

    1
    1 2 2
    10U_0603_6.3V6M 1U_0402_6.3V4Z 2 2 D Q52
    1
    <31,40,42> SYSON 2

    1
    2 1U_0402_6.3V4Z Q51 G 2N7002_SOT23
    <31> VLDT_EN 2

    2
    1

    1
    D 10U_0603_6.3V6M 2N7002_SOT23
    Change 0603 G S

    3
    1

    1
    D
    2 SUSP Change 0603 S R1109
    size For DVT

    3
    G 2 VLDT_EN# 100K_0402_5%
    1 2 5VS_GATE S Q53 size For DVT G R1107
    +VSB

    3
    R1103 100K_0402_5% 2N7002_SOT23 +VSB 1 2 1.1VS_GATE S Q54 10K_0402_5%

    2
    1 R1105 47K_0402_5% 2N7002_SOT23

    2
    1
    D C1450
    +5VALW

    300K_0402_5%
    SUSP 2 1

    1
    Q55 G 0.1U_0603_25V7K D C1451 +5VALW
    2

    R1106
    2N7002_SOT23 S VLDT_EN# 2
    3

    2
    Q56 G 0.1U_0603_25V7K

    2
    2N7002_SOT23 S 2 R1116

    3
    R1114 100K_0402_5%

    1 2
    100K_0402_5%
    D
    +3VALW TO +3VS

    1
    <25,31,37> ACIN ACIN 2 Q57 SUSP
    <42> SUSP

    1
    Change P/N SB00000GV00 G 2N7002_SOT23 VGA_ON#
    +3VS S

    1
    +3VALW D

    1
    U41 D Q59
    Change 0603 <31,40,41> SUSP# 2
    SI4800BDY-T1-GE3_SO8 <24,31> VGA_ON 2 Q58 G 2N7002_SOT23
    size For DVT

    1
    8 1 G 2N7002_SOT23 S

    3
    1
    7 2 S

    3
    2
    6 3 1 1 R1115
    1 1 5 C1452 R1110 R1113 10K_0402_5%
    2 C1453 C1454 470_0603_5% 10K_0402_5% 2

    2
    10U_0603_6.3V6M C1455
    4

    2
    10U_0603_6.3V6M 2 2

    1 1
    2 2
    10U_0603_6.3V6M 1U_0402_6.3V4Z
    D +5VALW
    2 SUSP
    Change 0603 G

    2
    +VSB 2 1 3VS_GATE S Q60
    size For DVT
    3

    R1112 200K_0402_5% 2N7002_SOT23 R1117


    +5VALW 100K_0402_5%
    1

    D
    1
    SUSP 2 C1456

    1
    2
    Q61 G PE_GPIO1#
    <24> PE_GPIO1#
    2N7002_SOT23 S 0.1U_0603_25V7K R1131
    3

    2 100K_0402_5%

    1
    D
    <13,24> PE_GPIO1 2 Q62

    1
    1.5_VDDC_PWREN# G 2N7002_SOT23
    <25> 1.5_VDDC_PWREN#

    1
    S

    3
    R1118
    +1.5VS

    1
    D 100K_0402_5%
    <24,43> 1.5_VDDC_PWREN 2 Q77
    Q63 G 2N7002_SOT23

    2
    1
    +1.5V SI2301CDS-T1-GE3_SOT23-3 +1.5VS S

    3
    +5VALW
    S

    Change 0603 R1134


    D

    3 1
    10K_0402_5%
    size For DVT
    2

    2
    3 3
    R1121 C1461 R1120
    G
    2

    470_0603_5% R1119
    100K_0402_5% 10U_0603_6.3V6M 100K_0402_5%
    2
    1

    1
    VGA_PWR_ON#
    <25> VGA_PWR_ON#
    1

    D
    2 SUSP
    1

    1
    R1122 D G D
    SUSP# 2 1 2 Q67 S Q65 2 Q68
    3

    200K_0402_5% 1 G 2N7002_SOT23 <24,25> VGA_PWR_ON G 2N7002_SOT23

    1
    S S
    3

    3
    C1463 SSM3K7002FU_SC70-3 R1123
    0.1U_0603_25V7K 100K_0402_5%
    2

    2
    +1.5V +0.75VS +1.1VS +VGA_CORE
    2

    R1135 R1137 R1128 R1126


    470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
    VGA@
    4 4
    1

    1
    1

    D D D D
    2 SYSON# 2 SUSP 2 VLDT_EN# 2 1.5_VDDC_PWREN#
    G G G G
    S Q78 S Q80 S Q74 S Q28
    Security Classification Compal Secret Data Compal Electronics, Inc.
    3

    2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2010/08/20 2011/08/20 Title


    VGA@
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DC Interface
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 35 of 46
    A B C D E
    5 4 3 2 1

    @ PJP1
    ACES_50305-00441-001
    PL1
    SMB3025500YA_2P
    VIN
    1 1 2
    2
    3
    4
    GND

    1
    GND PC1 PC2 PC3 PC4
    1000P_0402_50V7K 100P_0402_50V8J 100P_0402_50V8J 1000P_0402_50V7K

    2
    D D

    VIN

    2
    PD1
    LL4148_LL34-2

    1
    PD2
    LL4148_LL34-2
    2 1
    BATT+

    1
    PR1 PR2
    68_1206_5% 68_1206_5%
    PQ1 VS
    TP0610K-T1-E3_SOT23-3

    2
    N1 3 1
    0.22U_0603_25V7K
    1

    PJ1 PJ2
    1

    PR3 1 PC6
    +3VALWP 1 1 2 2 +3VALW +1.8VSP 1 1 2 2 +1.8VS
    PC5

    C 100K_0402_5% 0.1U_0603_25V7K C
    JUMP_43X118 JUMP_43X118
    2

    (4.73A,200mils ,Via NO.= 10) (3A,120mils ,Via NO.=6)


    2

    <34> 51_ON# 1 2
    PJ3 PJ4
    PR4 1 2 1 2
    22K_0402_5% +5VALWP 1 2 +5VALW +1.1VALWP 1 2 +1.1VALW
    JUMP_43X118 JUMP_43X118
    (5A,200mils ,Via NO.= 10) (3.15A,140mils ,Via NO.=7)

    PJ6
    PJ5
    1 2
    +0.75VSP 1 2 +0.75VS
    1 2
    +VSBP 1 2 +VSB JUMP_43X79
    JUMP_43X39 (3A,120mils ,Via NO.=6)
    PreCHG (120mA,40mils ,Via NO.= 2)
    PQ2
    PR5 VIN PR7 LL4148_LL34-2 TP0610K-T1-E3_SOT23-3
    0_0603_5% 1K_1206_5% PD3 B+
    +CHGRTC 1 2 1 2 2 1 3 1
    +3VLP @PJP3
    @ PJP3
    100K_0402_5%

    100K_0402_5%
    PR8 JUMP_43X118
    1K_1206_5% 1
    1 2 2
    1

    1
    PR9

    1 2 PR10

    PR11 @PJP4
    @ PJP4
    1K_1206_5% JUMP_43X118

    2
    1 2 +VGA_COREP 1
    2 2
    2

    1 +VGA_CORE
    B PR12 B

    1
    1K_1206_5% (13A,520mils ,Via NO.= 26)
    1 2 PR13
    12 100K_0402_5%
    1

    PD4
    <31,37> ACOFF 2 PJ11
    1 2 2 +1.05VSP 1
    1 2
    2 +1.05VS
    3
    <38> +5VALWP PQ4 JUMP_43X118 PJ7
    BAS40CW_SOT323-3 PQ3 PDTC115EU_SOT323-3 (6A,240mils ,Via NO.=12) +1.5VP 1
    1 2
    2 +1.5V
    PDTC115EU_SOT323-3
    3

    JUMP_43X118
    PJ13
    1 1
    2 2
    JUMP_43X118
    (7A,280mils ,Via NO.=14)

    PJ16
    +1.5VSP 1
    1 2
    2 +1.5VS1
    JUMP_43X118
    A
    (1A,40mils ,Via NO.= 2) A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/13 Deciphered Date 2011/07/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR DCIN / Pre-charge
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    P5WE0 M/B LA-6901P Schematic
    Date: Friday, October 29, 2010 Sheet 36 of 46
    5 4 3 2 1
    A B C D

    Iada=0~4.74A(90W/19V=4.736A) @ PC30
    10U_1206_25V6M PQ5
    CP = 85%*Iada ; CP = 4.07A 1 2 AO4407A_SO8
    ADP_I = 19.9*Iadapter*Rsense @ PC56 1 8
    10U_1206_25V6M 2 7
    1 2 B+ CHG_B+
    3 6
    5
    PQ6 P2 PQ7 P3 PR14 0.02_2512_1% PL17 PL22
    AO4407A_SO8 AO4407A_SO8 1.2UH_1127AS-1R2N_2.4A_30% HCB4532KF-800T90_1812

    4
    VIN 8 1 1 8 1 4 1 2 1 2
    7 2 2 7 PR16
    6 3 3 6 2 3 CSIN 47K_0402_1%
    5 5 1 2 VIN
    CSIP

    10U_1206_25V6M

    10U_1206_25V6M

    10U_1206_25V6M
    2200P_0402_25V7K
    0.1U_0603_25V7K
    @ PD9

    5600P_0402_25V7K
    VIN PreCHG

    2
    1 1

    PC8

    PC9

    PC16
    1SS355_SOD323-2

    PC10

    PC11
    PR15

    PC7
    @ 10K_0402_1% 1 2 ACOFF

    2
    1
    1
    1
    PR18

    1
    1

    191K_0402_1% @ PR357

    0.1U_0603_25V7K
    1

    2
    PR19 PR17 200K_0402_1%

    1
    PC12
    200K_0402_1% 200K_0402_1% 6251VDD 1 2 VIN

    2
    PD5 @ PD12

    2
    RB751V-40_SOD323-2 ACSETIN 1SS355_SOD323-2

    1000P_0402_25V8J
    2.2U_0603_6.3V6K
    2

    1
    PC13

    1 1
    3

    1
    2 1 2

    1
    PC14
    10_1206_5%
    47K

    PR22
    PR23
    2 47K 14.3K_0402_1%

    2
    PR24 @ PQ61

    0.1U_0603_25V7K
    2

    1
    0_0402_5% PQ9 D 2N7002W -T/R7_SOT323-3

    1
    PC253
    V1 2 1 PU1 PDTC115EU_SOT323-3 2 PACIN
    <31> FSTCHG
    1

    PC15 G
    PQ8 1 24 DCIN 2 1 S
    1

    3
    VDD DCIN
    1

    1
    PDTA144EU_SOT323-3 PR25 47K_0402_5% @

    100K_0402_1%
    6251VDD 1 2 0.1U_0603_25V7K V1 2 1

    PR26
    2 PR27 ACSETIN 2 23 ACPRN <38> PR21
    ACSET ACPRN

    1
    150K_0402_1% PR28 100K_0402_5%

    1
    PQ13 20_0402_5% D
    2

    2
    6

    1
    D PQ10 PDTC115EU_SOT323-3 6251_EN CSON ACPRN
    3 EN CSON 22 1 2 2

    2
    2 PDTC115EU_SOT323-3 PC18 G PC17
    3

    5
    6
    7
    8
    G 2 0.047U_0402_16V7K S 2200P_0402_25V7K
    <31> 3S/4S#

    2
    4 21 1 2 CSOP PQ15 PQ12

    1
    CELLS CSOP PR29 2N7002W -T/R7_SOT323-3
    S AO4466_SO8
    1

    PQ14A PQ14B PC19 6800P_0402_25V7K 20_0402_5%


    2
    DMN66D0LDW -7_SOT363-6 DMN66D0LDW -7_SOT363-6 3 1 2 5 20 2 1 2

    ICOMP CSIN
    3

    2
    D PR30 4
    PC20 PR31 PC21 20_0402_5%
    5
    G 1 2 1 2 6 19 0.1U_0603_25V7K
    1 2 TCR=50ppm / C
    <40,41>

    1
    VCOMP CSIP PR32 PL2
    S 0.01U_0402_25V7K 10K_0402_1% 2_0402_5% 10UH_PCMB104T-100MS_6A_20% BATT+
    4

    3
    2
    1
    <31> ADP_I 1 2 7 18 LX_CHG 1 2 CHG 1 4 PR34
    PR33 100_0402_1% ICM PHASE 0.02_1206_1%

    5
    6
    7
    8

    4.7_1206_5%
    1 2 2 3

    PR35
    PR38 6251VREF 8 17 DH_CHG
    47K_0402_5% PR36 PC22 .1U_0402_16V7K VREF UGATE PR37 PC23
    PACIN 80.6K_0402_1% 0_0603_5% 0.1U_0603_25V7K PQ16

    10U_1206_25V6M

    10U_1206_25V6M
    1 2
    2 1 9 16 BST_CHG 1 2 BST_CHGA 2 1 AO4466_SO8 @

    2
    <31> IREF CHLIM BOOT

    1
    4
    0.01U_0402_25V7K
    1

    1
    PC25

    PC26
    PR40 PD8

    1
    PC24

    PR39 6251VREF 6251aclim 6251VDDP RB751V-40_SOD323-2

    680P_0402_50V7K
    1 2 10 ACLIM VDDP 15

    PC27
    100K_0402_1%
    2

    2
    1

    26251VDD

    20K_0402_1%
    12.1K_0402_1%
    2.55K_0402_1%

    3
    2
    1

    2
    1
    ACOFF 2 11 14 DL_CHG @
    <31,36> ACOFF
    2

    VADJ LGATE

    2
    PR42

    PR43
    PR41
    4.7_0603_5%
    12 13 PC28
    1 2

    1
    PQ17 GND PGND 4.7U_0603_6.3V6M
    3

    PDTC115EU_SOT323-3 D
    2 ISL6251AHAZ-T_QSOP24
    <31> 65W/90W# G
    PQ18 S
    3

    2N7002W -T/R7_SOT323-3

    CP mode 1 2
    3
    <31> CALIBRATE# PR44
    3

    Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) 15.4K_0402_1%
    2

    where Vaclm=1.502V, Iinput=4.07A PR45


    31.6K_0402_1%
    6251VDD
    Charging Voltage
    1

    BATT Type CV mode CC=0.6~4.48A PR48


    (0x15) 10K_0402_1%

    1
    1 2
    IREF=0.7224*Icharge PR46 PR47
    ACIN <25,31,35>

    Normal 3S LI-ON Cells 47K_0402_5% 10K_0402_1%


    12600mV 12.60V IREF=0.43V~3.24V
    2

    2
    PACIN

    1
    Ki
    1
    Vchlim=Iref*(PR374/(PR372+PR374)) PR49
    14.3K_0402_1%
    =Iref*(100K/(80.6K+100K))
    =Iref*0.5537

    2
    Ichanrge=(165mV/PR369)*(Vchlim/3.3V) ACPRN 2
    =(165m/20m)*(1/3.3V)*Iref*0.5537
    =1.3842*Iref PQ19
    Iref=0.7224*Ichanrge =>Ki=0.7224 PDTC115EU_SOT323-3
    3

    Kv
    4 4
    Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K
    R=514K//31.6K//(15.4K+3k)=11.372K
    r=514K//514K//31.6K=28.14K
    Vcell=0.175*Vadj+3.99v
    4.2V=0.175*Vadj+3.99V =>Vadj=1.2V
    Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K))
    1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899 Security Classification Compal Secret Data Compal Electronics, Inc.
    1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv Issued Date 2010/07/13 Deciphered Date 2011/07/13 Title
    A=Vref*(R/(R+514K))=0.052
    Kv=9.451 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR-CHARGER
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    P5WE0 M/B LA-6901P Schematic
    Date: Friday, October 29, 2010 Sheet 37 of 46
    A B C D
    5 4 3 2 1

    2VREF_8205

    1U_0603_10V6K
    D D

    1
    PC29

    2
    PR50 PR51
    13K_0402_1% 30K_0402_1%
    1 2 1 2

    PR52 PR53
    RT8205_B+ 20K_0402_1% 20K_0402_1% RT8205_B+
    1 2 1 2
    PL3
    HCB4532KF-800T90_1812
    B+ 1 2 Typ: 175mA +3VLP

    ENTRIP2

    ENTRIP1
    PR54 PR55
    2200P_0402_50V7K

    2200P_0402_50V7K
    0.1U_0603_25V7K

    0.1U_0603_25V7K
    4.7U_0805_25V6-K

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K
    137K_0402_1% 154K_0402_1%
    PC31

    PC38
    1 2 1 2

    4.7U_0805_10V6K
    1

    1
    PC32

    PC33

    PC34

    PC35

    PC36

    PC37
    8
    7
    6
    5

    5
    6
    7
    8
    PU2
    2

    2
    PC39

    ENTRIP2

    FB2

    TONSEL

    FB1

    ENTRIP1
    REF
    1
    C C
    PQ20 25 PQ21
    AO4466_SO8 P PAD AO4466_SO8

    2
    4 4
    7 VO2 VO1 24
    SPOK <39,41>
    8 23 PR57 PC41
    PR56 VREG3 PGOOD 0_0603_5% 0.1U_0603_25V7K
    1
    2
    3

    3
    2
    1
    1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2
    0_0603_5% BOOT2 BOOT1
    4.7UH_PCMC063T-4R7MN_5.5A_20% PC40 UG_3V 10
    VFB=2.0V 21 UG_5V PL5
    PL4 0.1U_0603_25V7K UGATE2 UGATE1 4.7UH_PCMC063T-4R7MN_5.5A_20%
    1 2 LX_3V 11 20 LX_5V 1 2 +5VALWP
    +3VALWP PHASE2 PHASE1
    1

    8
    7
    6
    5

    1
    LG_3V LG_5V
    4.7_1206_5%

    4.7_1206_5%
    12 LGATE2 LGATE1 19

    5
    6
    7
    8
    PQ22
    @ PR58

    @ PR60
    SKIPSEL
    AO4712_SO8 PR59 @

    VREG5
    0_0402_5%

    GND

    VIN
    MAINPW ON RT8205EGQW _W QFN24_4X4

    NC
    EN
    1 2 1 1
    2

    2
    4
    PC42 + 4 PC43 +

    13

    14

    15

    16

    17

    18
    1

    1
    220U_6.3V_M PR61 220U_6.3V_M
    680P_0402_50V7K

    680P_0402_50V7K
    499K_0402_1% AO4712_SO8
    @ PC44

    @ PC45
    2 PQ23 2
    1 2
    2

    1
    2
    3

    2
    B+

    3
    2
    1
    1
    100K_0402_1%

    1U_0603_10V6K
    VL

    1
    PC46

    1
    PR62

    PC47
    Typ: 175mA

    4.7U_0805_10V6K
    B B

    2
    ENTRIP1 ENTRIP2
    2

    2
    RT8205_B+

    0.1U_0603_25V7K
    D D
    3

    2VREF_8205

    2
    PQ24B PQ24A

    PC48
    5 2
    DMN66D0LDW -7_SOT363-6 G G DMN66D0LDW -7_SOT363-6 TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
    <39> MAINPWON PR63
    0_0402_5% S S
    (2)SMPS2=375KHZ(+3VALWP)
    4

    2 1

    PR64
    100K_0402_1%
    2 1
    VL
    +3.3VALWP +5VALWP
    Ipeak=6.768A ; 1.2Ipeak=8.12A; Imax=4.738A Ipeak=7A ; 1.2Ipeak=8.4A; Imax=4.9A
    f=375KHz, L=4.7UH,Rentrip=162k ohm f=300KHz, L=4.7UH,Rentrip=154k ohm
    1

    2N7002W -T/R7_SOT323-3
    PQ26 PQ25
    Rdson=15~18m ohm Rdson=15~18m ohm
    PR65
    D
    PDTC115EU_SOT323-3 1/2Delta I = 1/2 *(19-3)*(3/19)/(375KHz*4.7UH)=0.774A 1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A
    1

    200K_0402_5% Vlimit=10*10^-6*162Kohm/10=0.162V Vlimit=10*10^-6*154Kohm/10=0.15V


    <37> ACPRN 2 1 2 1 2 2
    G VS Ilimit=0.162/(18m*1.2)~0.162/(15m*1.2)=7.5A~9A Ilimit=0.15/(18m*1.2)~0.15/(15m)=7.13~10.26A
    S PR66 Iocp=8.274A~9.774A Iocp=8.44~9.86A
    40.2K_0402_1%

    2.2U_0603_6.3V6K
    3

    A A
    1

    100K_0402_1%
    1

    1
    PR67

    PC49

    3
    2
    2

    <31,34> EC_ON 2 PQ27


    PDTC115EU_SOT323-3 Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2010/07/13 Deciphered Date 2011/07/13 Title

    3VALWP/5VALWP
    3

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    P5WE0 M/B LA-6901P Schematic
    Date: Friday, October 29, 2010 Sheet 38 of 46
    5 4 3 2 1
    5 4 3 2 1

    PJP2
    SUYIN_200275GR008G13GZR
    D D
    10
    GND
    9
    GND
    8
    8
    7
    7 EC_SMDA
    6
    6

    2
    5 EC_SMCA
    5 TH PR68
    4
    4 PI 100_0402_1%
    3
    3
    2
    2
    1 PH1 under CPU botten side :

    1
    1

    2
    PR69
    CPU thermal protection at 92 degree C
    <40,41> 100_0402_1% Recovery at 56 degree C
    EC_SMB_DA1 <31>
    VL
    VMB

    1
    1
    PL6 <40,41> EC_SMB_CK1 <31>
    SMB3025500YA_2P
    1 2 BATT+ PR70

    1
    1K_0402_5%

    2
    PR73 PC50 PR71 PR72
    1

    6.49K_0402_1% 0.1U_0603_25V7K VL 10K_0402_1% 21K_0402_1%

    2
    PC51 PC52 2 1
    0.01U_0402_25V7K +3VALWP
    1000P_0402_50V7K
    2

    2
    2
    PU3
    @ PR74 1 8
    VCC TMSNS1

    1
    100K_0402_1%
    PR75 2 7 2 1
    1K_0402_1% GND RHYST1

    1
    3 6 PR76
    OT1 TMSNS2
    C
    <38> MAINPWON 9.53K_0402_1% C

    2
    4 OT2 RHYST2 5 2 1
    BATT_TEMP <31> @ PR77
    G718TM1U_SOT23-8
    47K_0402_1%

    1
    PH2 @ PH1

    100K_0402_1%_NCP15WF104F03RC 100K_0402_1%_NCP15WF104F03RC

    2
    PQ28
    TP0610K-T1-E3_SOT23-3

    B+ 3 1 +VSBP
    100K_0402_1%

    0.22U_0603_25V7K
    1

    1
    PR78

    PC53

    PC54
    0.1U_0603_25V7K
    2

    2
    2

    PR79
    VL 22K_0402_1%
    1 2
    2

    PR80
    100K_0402_1%
    B B
    PR81
    1

    1K_0402_5% D
    1 2 2 PQ29
    <38,41> SPOK
    G 2N7002W-T/R7_SOT323-3
    1U_0402_6.3V6K

    S
    3
    1

    PC55
    2

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/13 Deciphered Date 2011/07/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PWR-BATTERY CONN/OTP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    P5WE0 M/B LA-6901P Schematic
    Date: Friday, October 29, 2010 Sheet 39 of 46
    5 4 3 2 1
    A B C D

    PU4
    SY8033BDBC_DFN10_3X3 PL7

    4
    @ PJ14 2.2UH_MSCDRI-74A-2R2M-E_6.5A_20%
    +5VALW 2 1 10 2 LX_1.8VS 1 2 +1.8VSP

    PG
    2 1 PVIN LX
    1 1

    JUMP_43X39

    68P_0402_50V8J
    9 PVIN LX 3

    1
    1

    1
    4.7_1206_5%

    PC116
    PC115 8 SVIN

    PR82
    22U_0805_6.3VAM PR83
    6 FB=0.6Volt 20K_0402_1%

    22U_0805_6.3VAM

    22U_0805_6.3VAM
    2

    2
    FB
    5

    2
    EN

    1
    NC

    NC
    TP

    PC118
    PC117
    2
    FB_1.8VS

    11

    2
    PR84

    680P_0603_50V7K
    <31,35,41> SUSP# 1 2 EN_1.8VS

    1
    PC119
    200K_0402_5%

    LX_1.8VS
    PR85

    2
    10K_0402_1%

    1
    @ PC120
    PR86

    2
    1M_0402_5% 0.22U_0402_10V6K

    2
    2
    G5603 RT8209B TPS51117 RT8209M

    Temperature
    Compensated -1180ppm/ ℃ 1600ppm/ ℃ 4500ppm/ ℃ 4800ppm/ ℃
    2 2

    Vtrip_min (SPEC) 30mV 50mV 30mV 50mV PL8


    HCB2012KF-121T50_0805
    1 2 B+

    2200P_0402_50V7K
    0.1U_0603_25V7K
    4.7U_0805_25V6-K
    4.7U_0805_25V6-K
    Vtrip_max (SPEC) 200mV 200mV 200mV 200mV

    1
    PC124

    PC125
    PC121
    5
    6
    7
    8

    PC123
    2

    2
    PR87
    255K_0402_1%
    1 2 4
    PR88
    <31,35,42> SYSON 1 2 PR89
    BST_1.5V 1 2 PQ30
    0_0402_5%
    1

    AO4466_SO8
    0_0603_5%

    3
    2
    1
    1

    PR90 PL9
    15

    14

    PC126 @
    1

    30K_0402_5% PU5 PC127 1.0UH_PCMC104T-1R0MN_20A_20%


    .1U_0402_16V7K BST_1.5V-1 1 2 2 1 +1.5VP
    EN/DEM

    NC

    BOOT
    2
    2

    2 13 DH_1.5V 0.1U_0603_25V7K
    TON UGATE
    3 12 LX_1.5V
    VOUT PHASE

    5
    6
    7
    8

    1
    PR91 PR92
    1 2 4 11 1 2 @ PR93 1
    +5VALW VDD
    VFB=0.75V CS +5VALW 4.7_1206_5%
    100_0603_5% 7.68K_0402_1%
    5 10 + PC128
    FB VDDP
    330U_6.3V_M

    2
    1

    PC129 6 9 DL_1.5V 4
    3
    PGOOD LGATE 3
    PGND

    2
    GND

    4.7U_0603_6.3V6K

    2
    2

    1
    PC131 PQ31 @ PC130
    RT8209MGQW _W QFN14_3P5X3P5 AO4726L_SO8 680P_0603_50V7K
    4.7U_0805_10V6K
    7

    3
    2
    1

    2
    Rtrip: 5KΩ~15KΩ
    Rds(on) = 5.3m ohm (typ)
    7m ohm (max)
    PR94
    1 2
    5.1K_0402_1%
    1

    PR95
    5.1K_0402_1%
    2

    <Vo=1.5V> VFB=0.75V
    Vo=0.75*(1+10K/10K)=1.5V
    Fsw=280KHz
    Cout ESR=17 mohm Rdson(max)=7 mohm Rdson(typ)=5.3 mohm
    Ipeak=9.45A, Imax=6.615A
    4
    Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=4.93A 4

    =>1/2Delta I=2.467A
    Vtrip=Rtrip*10uA=0.0768
    Iocpmin=Vtrip/(Rds(on)(max)*1.2)+Delta I/2=11.61A
    Iocpmax=Vtrip/(Rds(on)(typ)*1.2)+Delta I/2=14.54A
    Iocp=11.61A~14.54A Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2010/01/25 Deciphered Date 2009/04/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    1.8VSP/1.5VP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 29, 2010 Sheet 40 of 46
    A B C D
    A B C D

    PL10
    HCB2012KF-121T50_0805

    1.1VALW _B+ 2 1 B+

    2200P_0402_50V7K
    0.1U_0603_25V7K

    0.1U_0603_25V7K

    0.1U_0603_25V7K
    4.7U_0805_25V6-K

    4.7U_0805_25V6-K
    1

    1
    PC132

    PC133

    PC134

    PC135

    PC207

    PC208
    5
    6
    7
    8

    2
    <Vo=1.1V> VFB=0.75V
    1
    PR96 V=0.75*(1+4.7K/10K)=1.1V 1

    255K_0402_1% 4 Fsw=280KHz
    1 2
    PR97 PR98
    0_0402_5% 0_0603_5% PQ32 Cout ESR=17 mohm Rdson(max)=18 mohm Rdson(typ)=15 mohm
    1 2 1 2 AO4466_SO8
    <38,39> SPOK Ipeak=4.5A, Imax=3.15A

    3
    2
    1
    1
    BST_1.1V ALW Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=1.68A

    1
    PR99 PC136 PL11

    15

    14
    PC137 =>1/2Delta I=0.84A

    1
    30K_0402_5% .1U_0402_16V7K PU6 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
    @ @ 1 2 1 2 Vtrip=Rtrip*10uA=0.107

    EN/DEM

    NC

    BOOT
    +1.1VALW P

    2
    Iocpmin=Vtrip/(Rds(on)(max)*1.2)+Delta I/2=5.79A
    2

    2 13 DH_1.1VALW
    0.1U_0603_25V7K
    TON UGATE Iocpmax=Vtrip/(Rds(on)(typ)*1.2)+Delta I/2=6.78A

    4.7_1206_5%
    PR101 3 12 LX_1.1VALW Iocp=5.79A~6.78A
    VOUT PHASE

    5
    6
    7
    8

    @ PR100
    100_0603_1% 1
    +5VALW PQ33

    330U_6.3V_M
    +5VALW 1 2 4 VDD CS 11 1 2
    +

    PC138
    PR102 AO4712_SO8

    2
    5 10 10.7K_0402_1%
    FB VDDP
    1

    1
    DL_1.1VALW 2

    680P_0603_50V7K
    6 PGOOD LGATE 9 4

    PGND
    PC139

    GND

    @ PC141
    4.7U_0603_6.3V6K
    2

    2
    PC140
    RT8209MGQW _W QFN14_3P5X3P5 4.7U_0805_10V6K

    3
    2
    1
    PR103 Rtrip: 5KΩ~15KΩ
    4.7K_0402_1%
    1 2
    2 2
    1

    PR104
    10K_0402_1% PL12
    HCB2012KF-121T50_0805
    2

    1.05VALW _B+ 2 1 B+

    2200P_0402_50V7K
    0.1U_0603_25V7K

    0.1U_0603_25V7K

    0.1U_0603_25V7K
    4.7U_0805_25V6-K

    4.7U_0805_25V6-K
    1

    1
    PC142

    PC143

    PC144

    PC145

    PC205

    PC206
    5
    6
    7
    8

    2
    PR105
    255K_0402_1% 4
    1 2
    PR106 PR107
    200K_0402_5% 0_0603_5% PQ34
    1 2 1 2 AO4466_SO8
    <31,35,40> SUSP#

    3
    2
    1
    1

    PC146
    BST_1.05V ALW
    1

    PR108 .1U_0402_16V7K PL13


    15

    14

    PC147
    1

    30K_0402_5% PU7 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%


    @ 1 2 1 2
    EN/DEM

    NC

    BOOT

    +1.05VSP
    2
    2

    2 13 DH_1.05VALW
    0.1U_0603_25V7K
    TON UGATE

    4.7_1206_5%
    3 3

    PR110 3 12 LX_1.05VALW
    VOUT PHASE

    5
    6
    7
    8

    PR109
    100_0603_1% 1
    +5VALW PQ35

    330U_6.3V_M
    +5VALW 1 2 4 VDD CS 11 1 2
    AO4726L_SO8 +

    PC148
    PR111

    2
    5 10 8.25K_0402_1%
    FB VDDP
    1

    1
    DL_1.05VALW 2

    680P_0603_50V7K
    6 PGOOD LGATE 9 4
    PGND

    PC149
    GND

    PC151
    4.7U_0603_6.3V6K
    2

    2
    PC150
    RT8209MGQW _W QFN14_3P5X3P5 4.7U_0805_10V6K
    7

    3
    2
    1
    PR112 Rtrip: 5KΩ~15KΩ
    4.02K_0402_1%
    1 2 <Vo=1.05V> VFB=0.75V
    Rds(on) = 5.3m ohm (typ) V=0.75*(1+4.02K/10K)=1.05V
    1

    7m ohm (max) Fsw=280KHz


    PR113
    10K_0402_1%
    Cout ESR=17 mohm Rdson(max)=7 mohm Rdson(typ)=5.3 mohm
    Ipeak=8.7A, Imax=6.09A
    2

    Delta I=((19-1.05)*(1.05/19))/(L*Fsw)=1.61A
    =>1/2Delta I=0.81A
    Vtrip=Rtrip*10uA=0.0825
    G5603 RT8209B TPS51117 RT8209M Iocpmin=Vtrip/(Rds(on)(max)*1.2)+Delta I/2=10.63A
    4 Iocpmax=Vtrip/(Rds(on)(typ)*1.2)+Delta I/2=13.78A 4

    Temperature
    Compensated -1180ppm/ ℃ 1600ppm/ ℃ 4500ppm/ ℃ 4800ppm/ ℃ Iocp=10.63A~13.78A

    Vtrip_min (SPEC) 30mV 50mV 30mV 50mV Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2010/01/25 Deciphered Date 2009/04/28 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    1.1VALWP/1.05VSP
    Vtrip_max (SPEC) 200mV 200mV 200mV 200mV AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 29, 2010 Sheet 41 of 46
    A B C D
    5 4 3 2 1

    @ PL20
    HCB2012KF-121T50_0805
    1 2 B+

    2200P_0402_50V7K
    4.7U_0805_25V6-K

    0.1U_0603_25V7K
    4.7U_0805_25V6-K
    1

    1
    PC201

    PC197
    PC198
    5
    6
    7
    8

    PC204
    2

    2
    @ @ @
    @ PR180 @
    255K_0402_1%
    1 2 4
    @ PR186
    D @ PR181 D
    <31,35,40> SYSON 1 2
    BST_1.5V-2 1 2 @ PQ46
    0_0402_5%

    1
    AO4466_SO8
    0_0603_5%

    3
    2
    1
    1
    @ PR183 @ PC203 @ @ PL21

    15

    14
    1
    30K_0402_5% PU11 @ PC199 1.0UH_PCMC104T-1R0MN_20A_20%
    .1U_0402_16V7K BST_1.5V-2 1 2 2 1 +1.5VSP

    EN/DEM

    BOOT
    NC
    2
    2
    2 13 DH_1.5V-2 0.1U_0603_25V7K
    TON UGATE
    3 12 LX_1.5V-2
    VOUT PHASE

    5
    6
    7
    8

    1
    @ PR178 @
    PR185
    1 2 4 11 1 2 @ PR182
    +5VALW VDD
    VFB=0.75V CS +5VALW 4.7_1206_5%
    1
    100_0603_5% 7.68K_0402_1%
    5 10 + @ PC202
    FB VDDP
    330U_6.3V_M

    2
    1

    @ PC196 6 9 DL_1.5V-2 4
    PGOOD LGATE 2

    PGND
    4.7U_0603_6.3V6K

    GND

    2
    2

    1
    @ PC200 @ PQ39 @ PC195
    RT8209MGQW_WQFN14_3P5X3P5 AO4726L_SO8 680P_0603_50V7K
    4.7U_0805_10V6K

    3
    2
    1

    2
    Rtrip: 5KΩ~15KΩ

    PR184
    1 @ 2
    5.1K_0402_1%
    1

    C
    <Vo=1.5V> VFB=0.75V C
    @ PR179 Vo=0.75*(1+10K/10K)=1.5V
    5.1K_0402_1% Fsw=280KHz
    G5603 RT8209B TPS51117 RT8209M
    2

    Temperature
    Compensated -1180ppm/ ℃ 1600ppm/ ℃ 4500ppm/ ℃ 4800ppm/ ℃ Cout ESR=17 mohm Rdson(max)=7 mohm Rdson(typ)=5.3 mohm
    Ipeak=9.45A, Imax=6.615A
    Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=4.93A
    =>1/2Delta I=2.467A
    Vtrip_min (SPEC) 30mV 50mV 30mV 50mV Vtrip=Rtrip*10uA=0.0768
    Iocpmin=Vtrip/(Rds(on)(max)*1.2)+Delta I/2=11.61A
    Iocpmax=Vtrip/(Rds(on)(typ)*1.2)+Delta I/2=14.54A
    Iocp=11.61A~14.54A
    Vtrip_max (SPEC) 200mV 200mV 200mV 200mV

    +1.5V
    1

    PJ15
    1

    JUMP_43X39
    22

    B PU8 B
    1
    VIN NC
    8 +3VALW
    2 7
    GND NC
    2

    1
    PC153
    1

    PC152 3 6 1U_0603_10V6K
    4.7U_0805_6.3V6K PR114 VREF VCNTL
    1

    2
    1K_0402_1% 4 5
    VOUT NC
    9
    2

    TP
    APL5336KAI-TRL_SOP8P8
    .1U_0402_16V7K

    PR115
    +0.75VSP
    1

    300K_0402_5% D
    1 2 2 PR116
    <35> SUSP
    1

    1
    PC154

    G 1K_0402_1%
    S PC155
    3
    1

    PQ36 10U_0603_6.3V6M
    2

    PC156 SSM3K7002FU_SC70-3
    .1U_0402_16V7K
    2

    For shortage changed

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2009/10/02 Deciphered Date 2010/10/02 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    0.75VSP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    0.3
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 29, 2010 Sheet 42 of 46
    5 4 3 2 1
    5 4 3 2 1

    VGA@ PL14
    HCB2012KF-121T50_0805

    B+ 1 2 B+_CORE

    +3VS

    2200P_0402_25V7K

    1
    0.1U_0603_25V7K

    10U_0805_25V6K

    10U_0805_25V6K
    @ PR117

    1
    PC158
    D 10K_0402_5% D

    5
    PC157

    PC159

    PC160
    2

    2
    VGA@
    VGA@ VGA@ VGA@
    <13,24> VGA_PWRGD
    4

    VGA@ PR118 VGA@ PC161


    VGA@ PU9 0_0603_5% 0.1U_0603_25V7K VGA@ PQ37
    VGA@ PR119 1 PGOOD 10 BST_VCORE 1 2 1 2 TPCA8065-H_PPAK56-8-5

    3
    2
    1
    44.2K_0402_1% VBST
    1 2 2 9 DH_VCORE VGA@ PL15
    TRIP DRVH 0.36UH_PCMC104T-R36MN1R17_30A_20%
    +3VS 3 8 SW_VCORE 1 2
    EN SW +VGA_COREP
    4 VFB V5IN 7 +5VALW ESR=10mohm

    1
    1

    1
    1 2 5 6 DL_VCORE @ PR122 VGA@ PC163
    RF DRVL
    2

    4.7_1206_5% VGA@ PR124 + 390U_2.5V_M

    2
    @ PR121 VGA@ PR120 11 0_0402_5%
    10K_0402_5% 200K_0402_1% TP VGA@

    2
    TPS51218DSCR_SON10_3X3 PC162 2

    2
    VGA@ PR123 VFB=0.7V 1U_0603_6.3V6M 4
    1

    1
    20K_0402_1%
    1 2 @ PC164 VGA@ PR125
    <24,35> 1.5_VDDC_PWREN
    VGA@ PQ38 680P_0603_50V7K 10_0402_5%

    2
    Switch Freq. (RF pin setting) TPCA8057-H_PPAK56-8-5 2 1 GCORE_SEN GCORE_SEN <21>

    3
    2
    1
    1

    C VGA@ PC165
    47K =>450KHz C
    100K =>390KHz

    2
    .1U_0402_16V7K
    2

    200K =>350KHz
    VGA@ PR126
    470K =>290KHz Rds=2.6m/3.2mOHM 2.87K_0402_1%

    1
    +3VSG

    2
    1
    VGA_CORE VGA@ PR127

    2
    17.4K_0402_1%
    Vtrip= 0.7V VGA@ PR131 VGA@ PC166 VGA@ PR128 VGA@ PR129
    Vo=0.7*(1+Rtop/Rdown) 30.9K_0402_1% 2200P_0402_25V7K 8.87K_0402_1% 10K_0402_5%

    1
    Fsw=350KHz

    2
    +3VSG VGA@ PR130

    1
    6
    D 10K_0402_5%
    Ipeak=18.2A Imax=12.74A, 1.2*Ipeak=21.84A 2 1 2

    2
    Delta I= ((19-0.9)*(0.9/19))/(L*Fsw)=6.8A G

    2
    VGA@ PR133 DMN66D0LDW-7_SOT363-6
    Iocpmax=(66.5K*11uA)/(8*1.2*0.0026) +3.4=32.71A

    1
    10K_0402_5% VGA@ PQ40A S

    1
    Iocpmin=(66.5K*9uA)/(8*1.2*0.0032)+3.4=22.88A VGA@ PC167 @ PR132
    Iocp=22.88~32.71A VGA@ PR134 4700P_0402_25V7K 10K_0402_5%

    2
    3
    D 10K_0402_5%

    1
    5 1 2
    G
    B B

    1
    VGA@ PQ40B S

    1
    DMN66D0LDW-7_SOT363-6
    VGA@ PC168 @ PR135
    4700P_0402_25V7K 10K_0402_5% +3VSG

    2
    @ PR139
    VGA@ PR140 10K_0402_5%

    3
    D 10K_0402_5% +3VSG
    5 2 1
    GPU_VID0 <19>

    11
    GPIO 15 GPIO 20 Seymour VGA@ PQ41B G

    2
    DMN66D0LDW-7_SOT363-6 VGA@ PR141
    S 10K_0402_5% @ PR136

    4
    GPU_VID0 GPU_VID1 Core Voltage Level 10K_0402_5%

    1
    1 1 0.9V VGA@ PR137

    6
    D 10K_0402_5%
    AP 2 2 1
    GPU_VID1 <19>

    1
    0 1 1.00V VGA@PQ41A G
    DMN66D0LDW-7_SOT363-6
    S VGA@ PR138

    1
    1 0 1.05V 10K_0402_5%

    2
    0 0 1.10V
    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/07/13 Deciphered Date 2011/07/13 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    +VGA_COREP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS P5WE6/S6/H6
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 29, 2010 Sheet 43 of 46
    5 4 3 2 1
    A B C D E

    PL16
    CPU_B+ HCB2012KF-121T50_0805

    2 1 B+

    1
    4.7U_0805_25V6-K

    2200P_0402_50V7K

    220U_25V_M
    4.7U_0805_25V6-K

    0.1U_0603_25V7K

    0.1U_0603_25V7K

    0.1U_0603_25V7K

    0.1U_0603_25V7K
    PC169

    5
    6
    7
    8

    10U_1206_25V6M

    10U_1206_25V6M
    0.1U_0603_25V7K
    47P_0402_50V8J PR188 1
    2 1 220_0402_1%

    1
    PC171

    PC174

    PC209

    PC210

    PC211

    PC212

    PC175

    PC57

    PC58
    +

    PC172

    PC173
    PR189

    1 2
    2 1 2 1 0_0603_5%

    2
    UGATE_NB 1 2 UGATE_NB1 4 2
    PR142 PC170
    44.2K_0402_1% 1000P_0402_50V7K

    2
    PR143 PQ42
    1 2_0603_5% AO4466_SO8 1

    3
    2
    1
    1 2 PC176 PL18
    +5VALW 1000P_0402_50V7K 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
    2 1 PHASE_NB 1 2 +APU_CORE_NB
    PR145

    5
    6
    7
    8

    1
    PC177 PR144 2.2_0603_1%
    0.1U_0603_16V7K 22K_0402_1% BOOT_NB
    1 2 1 2 @PR146
    2 1 4.7_1206_5% 1

    2
    PR147 PC178
    10_0402_5% 0.22U_0603_10V7K PQ43 + PC179 ESR = 15 m ohm

    1 2
    1 2 +APU_CORE_NB LGATE_NB 4 AO4712_SO8 220U_6.3V_M
    1 2 PR149 @ PC180
    CPU_B+ 2
    0_0402_5% 680P_0603_50V7K
    PR148 2 1 APU_VDDNB_RUN_FB_H <5>

    2
    2_0603_5% PR150

    3
    2
    1
    +3VS +5VS +3VS 0_0402_5%

    1
    PC181 2 1 APU_VDD0_RUN_FB_L
    0.1U_0603_25V7K
    PR151 1 2

    2
    23.7K_0402_1% PR187 Rds(on) max =18 m ohm CPU_B+
    2 1 10_0402_5%PHASE_NB typ = 15 m ohm
    1

    1
    PR152 @ PR153 LGATE_NB

    2200P_0402_50V7K
    0.1U_0603_25V7K
    4.7U_0805_25V6-K

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K
    0_0402_5% 105K_0402_1%

    5
    PHASE_NB
    2

    2
    1

    1
    PC182

    PC183

    PC184

    PC185

    PC186
    UGATE_NB
    @ PR155 PR190
    PR154 10K_0402_1% 0_0603_5%

    2
    105K_0402_1% UGATE0 1 2 UGATE0-1 4 DCR = 1.1m ohm +-7%
    1

    48

    47

    46

    45

    44

    43

    42

    41

    40

    39

    38

    37
    2

    @ PR156 PU10 PL19


    2 105K_0402_1% PHASE0 PQ44 2

    FB_NB

    COMP_NB

    FSET_NB

    VSEN_NB

    RTN_NB

    OCSET_NB

    PGND_NB

    LGATE_NB

    PHASE_NB

    UGATE_NB
    VIN

    VCC
    PR158 TPCA8065-H_PPAK56-8-5 0.36UH_PCMC104T-R36MN1R17_30A_20%

    3
    2
    1
    2.2_0603_1%
    2

    1 36 BOOT_NB BOOT0 1 2 1 2 4 1
    <14,31> VGATE OFS/VFIXEN BOOT_NB +APU_CORE
    1 2
    <14> FCH_PWRGD @ PR159 100K_0402_5% 2 35 BOOT0 PC187 PQ44, PQ45 need to link 3 2
    PGOOD BOOT0

    5
    1 2 0.22U_0603_10V7K

    1
    <13> H_PWRGD_L PR157 100K_0402_5% ISL6265_PWROK 3 34 UGATE0
    PWROK UGATE0

    2
    PR161
    <5> APU_SVD 2 1 4 33 PHASE0 4.7_1206_5% PR162
    <5> APU_SVC PR160 SVD PHASE0 12.7K_0402_1%
    0_0402_5%2 1 5 32 4

    1 2
    <31> VR_ON PR163 SVC PGND0 +5VALW

    1
    PR164 PR165 0_0402_5% 6 31 LGATE0 PC188 PC189
    21.5K_0402_1% 95.3K_0402_1% ENABLE ISL6265CHRTZ-T_TQFN48_6X6 LGATE0 PQ45 680P_0603_50V7K 2 1
    2 1 2 1 7 30 TPCA8057-H 1N PPAK56-8

    3
    2
    1

    2
    RBIAS PVCC 0.1U_0603_16V7K
    8 29
    OCSET LGATE1

    1
    PC190 2 1
    9 28 1U_0603_16V6K
    VDIFF0 PGND1 LGATE0 PR166

    ISN0
    ISP0
    10 27 4.53K_0402_1%
    FB0 PHASE1
    11 26
    COMP0 UGATE1
    12 25
    VW0 BOOT1
    COMP1
    VDIFF1
    VSEN0

    VSEN1
    RTN0

    RTN1
    ISN0

    ISN1
    ISP0

    VW1

    ISP1
    FB1

    TP
    VSEN1

    13

    14

    15

    16

    17

    18

    19

    20

    21

    22

    23

    24

    3 ISP0 49 3
    ISN0
    2

    VSEN1

    PR167
    ISN0
    ISP0

    +APU_CORE 2 1 PR168
    0_0402_5%
    10_0402_1%
    PR169
    1

    0_0402_5%
    2 1 VSEN0
    <5> APU_VDD0_RUN_FB_H

    <5> APU_VDD0_RUN_FB_L PR170 0_0402_5%


    10_0402_1% PR171
    2 1 2 1 RTN0

    1K_0402_5%
    PR172
    +1.5V 2 1

    DIFF_0 VW0

    PR173 PC191
    255_0402_1% 2200P_0402_25V7K
    2 1 2 1 2 1 COMP0 2 1

    PC192 PC193
    4 220P_0402_50V8J 1000P_0402_50V7K 4

    PR174 PR176
    1K_0402_5% PR175 PC194 6.81K_0402_1%
    2 1 2 1 2 1 2 1

    54.9K_0402_1% 1200P_0402_50V7K
    Security Classification Compal Secret Data Compal Electronics, Inc.
    1

    @ PR177 Issued Date 2009/10/02 2010/10/02 Title


    36.5K_0402_1%
    Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    CPU_CORE
    Size Document Number Rev
    2

    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    0.3
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 29, 2010 Sheet 44 of 46
    A B C D E
    5 4 3 2 1

    Version change list (P.I.R. List) Page 1 of 1


    for PWR
    Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

    Change PR115 from SD028000080 to SD028300380(S RES 1/16W 300K +-5% 0402) 2010/09/24 DVT
    D
    1 0.75VSP EN RC value HW adjust timing 0.1 42 Add PC156 SE076104K80(S CER CAP .1U 16V K X7R 0402)
    D

    Change PR84 from SD028000080 to SD028200380(S RES 1/16W 200K +-5% 0402) 2010/09/24 DVT
    2 1.8VSP EN RC value HW adjust timing 0.1 40 Add PC120 SE095224K00(S CER CAP 0.22U 10V K X5R 0402)

    Change PR106 from SD028000080 to SD028200380(S RES 1/16W 200K +-5% 0402) 2010/09/24 DVT
    1.05VSP EN RC value HW adjust timing 0.1 41 Add PC146 SE076104K80(S CER CAP .1U 16V K X7R 0402)

    HW adjust timing 0.1 43 Change PR123 from SD034100280 to SD034200280(S RES 1/16W 20K +-1% 0402) 2010/09/24 DVT
    4 VGA_COREP EN RC value

    Change PU11, PL21, PQ39, PQ46, PR178, PR179, PR180, PR181, PR184, PR185,
    change BOM structure 1.5VSP change BOM structure to VGA@ for cost down of UMA 0.1 42 PR186, PC196, PC197, PC198, PC199, PC200, PC201, PC202, PC204 BOM structure 2010/10/05 DVT
    5 to VGA@
    del PL20 SM01000C000(S SUPPRE_ TAI-TECH HCB2012KF-121T50 0805)
    C C

    6 Adjust APU_CORE_NB OCP to 15A 0.1 44 Change PR151 from SD034110280 to SD034237280(S RES 1/16W 23.7K +-1% 0402) 2010/10/07 DVT
    Adjust APU_CORE_NB OCP

    7 Add input choke in charger circuit. Add input choke for EMI ISN test in charger circuit. 0.1 37 Change PL17 from SM010018710 to SH00000B100(S COIL 1.2UH +-30% 1127AS-1R2N 2.4A) 2010/10/18 DVT

    Add PR161 SD001470B80(S RES 1/4W 4.7 +-5% 1206)


    Add snubber Add snubber in CPU_COREP circuit. 0.1 44 Add PC188 SE025681K80(S CER CAP 680P 50V K X7R 0603)
    8 Add PR188 SD034220080(S RES 1/16W 220 +-1% 0402) 2010/10/18 DVT

    Add PR161 SD001470B80(S RES 1/4W 4.7 +-5% 1206)


    Add snubber and input Cup. Add snubber and input Cup. in 1.05VSP circuit. 0.1 41 Add PC188 SE025681K80(S CER CAP 680P 50V K X7R 0603) 2010/10/18 DVT
    9 Add PC205, PC206 SE042104K80(S CER CAP .1U 25V K X7R 0603)

    Add input Cup. Add input Cup. in 1.1VALWP circuit. 0.1 41 Add PC207, PC208 SE042104K80(S CER CAP .1U 25V K X7R 0603) 2010/10/18 DVT
    10
    B B

    Add PC209, PC210, PC211, PC212 SE042104K80(S CER CAP .1U 25V K X7R 0603)
    Add input Cup. Add input Cup. and H/S gate resistance in CPU_COREP 0.1 44 Add PC57, PC58 SE142106M80(S CER CAP 10U 25V M X5R 1206 H1.7) 2010/10/19 DVT
    11 circuit for EMI ISN test. Add PR189, PR190 SD013000080(S RES 1/10W 0 +-5% 0603)

    Change PR128 from SD034100280 to SD034976180(S RES 1/16W 9.76K +-1% 0402)
    Adjust VGA_COREP VID value Adjust VGA_COREP VID value 0.1 43 Change PR127 from SD034200280 to SD034147280(S RES 1/16W 14.7K +-1% 0402) 2010/10/21 DVT
    12 Change PR131 from SD000009K00 to SD034240280(S RES 1/16W 24K +-1% 0402)

    Change PU11, PL21, PQ39, PQ46, PR178, PR179, PR180, PR181, PR184, PR185,
    change BOM structure 1.5VSP change BOM structure to @ for cost down 0.1 42 PR186, PC196, PC197, PC198, PC199, PC200, PC201, PC202, PC204 BOM structure 2010/10/21 DVT
    13 to @
    del PL20 SM01000C000(S SUPPRE_ TAI-TECH HCB2012KF-121T50 0805)

    14

    15
    A A

    16

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/04/12 Deciphered Date 2010/10/12 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    PIR (PWR)
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    PEW96 LA-6552P
    Date: Friday, October 29, 2010 Sheet 45 of 46
    5 4 3 2 1
    5 4 3 2 1

    PHASE PAGE Modification list PURPOSE


    0.1 P08 First release Base on PEW96, change platform (NB,CPU-->APU,SB820-->FCH)
    C220, C336, C347, C357, C359, C360, C387, C388, C389, C390, C391, C392, C393, C421,
    0.2 P-- Follow Standard Part 0805-->0603
    C427, C428, C1461 change 0603 size
    C721 C669, C1005, C705, C708, C713, C715, C736, C794, C797, C932, C934, C983
    0.2 P-- Follow Standard Part 0805-->0603
    change 0603 size
    C215, C216, C218, C224, C226, C227, C229, C230, C231, C660, C671, C821, C823,
    D 0.2 D
    P-- C1210, C1517, C1522, C1526, C1529, C1532, C1512, C1523, C1443, C1445, C1446, C1447, Follow Standard Part 0805-->0603
    C1448, C1452, C1453, C1454 change 0603 size
    0.2 P35 R1122 change as 200k ohm, C1463 change as 0.1UF Adjust sequence
    0.2 P5 Add R109, R155 Pull up 4.7k ohm for CRT EDIE
    0.2 P16 Unpop R632, C744, C69, C746; Pop R633 +VDDIO_18_FC Tie to GND for Nun-share ROM
    0.2 P16 Add R635; Unpop R634 AMD suggestion for +VDDIO_AZ
    0.2 P24 Add R170, R171 For DISO BOM option
    0.2 P13 Add U33, C1199, R830, R838, R839 For VGA_PWRGD
    0.2 P13 Remove C52, R557 For A_RST#
    0.2 P27 EC_MUTE# change as 12 PIN form 46 PIN in Codec For External Mute Fail issue
    0.2 P16 C113, C77, C743, C96 change 0603 size and add C121, C105, C108, C109 22uF cap. change two 10uF cap. 0603 size
    0.2 P19 C14 change 0603 size and add C52 22uF cap. change two 10uF cap. 0603 size
    0.2 P13 C66, C67 change 27pF Follow suggestion by TXC result
    0.2 P26 C1485, C1486 change 33pF Follow suggestion by TXC result
    C 0.2 P33 C711 Change as SF000003I00 Material shortage C

    0.2 P9 Add C643, C675, C676, C678 For DDR3 moat issue
    0.2 P26 Remove C939 ; Reserve C941, D48, D49, D51, L109 For LAN
    0.2 P7 Add C604, C684 For CRT Moniter issue
    0.3 P-- C212, C623 change 0603 size ; add C628, C685 Follow Standard Part 0805-->0603
    0.3 P27 R786 change as 15k ohm Dos Beep issue
    0.3 P19 change R21, R22 as DISO@ Device Menage Audio issue

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2010/08/20 Deciphered Date 2011/08/20 Title

    Change footprint THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    HW-PIR
    : For cost down purpose to change parts Size Document Number Rev
    20100812 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    B 0.3
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    LA-7092P P5WE6/H6/S6
    Date: Friday, October 29, 2010 Sheet 46 of 46
    5 4 3 2 1
    www.s-manuals.com

    You might also like