Module IV - Interface Peripherals To 8086

EEC 364: INTRODUCTION TO MICROPROCESSORS
Course Objectives:
1. To study the architecture of the general purpose
microprocessors 8086 and advanced Processors.
2. To understand the assembly language programming of 8086
processor.
3. To impart knowledge about assembly language programming
to interface various peripherals like data converters,
keyboards, display units etc.,
4. To interface different peripheral units with microprocessors
i.e., the hardware of various consumer electronic goods.
5. To design and implement microprocessor based embedded
systems.
Course Outcomes:
Students will be able to
1. Acquire the knowledge of the internal architecture, memory
organization and operating modes of processors.
2. To write efficient codes on 6-bit platform.
3. interface the microprocessor with different peripheral ICs
such as 8255, 8251, 8253, 8279 etc.,
4. Design standalone microprocessor - based systems.
Prepared by
Dr Sreenivasa Rao Ijjada
Dept of ECE,GIT, GITAM University, Visakhapatnam
2019-2020
dr.ijjada2019@gmail.com
Dr.Sreenivasa Rao Ijjada, Dept of ECE, GIT, GITAM University Visakhapatnam Page 1
Module IV 10 hours
Interfacing Of Peripherals to 8086
Programmable I/O ports 8255: modes of operation of 8255
Digital to Analog converters- DAC 0800 interfacing
Analog to digital dataconverters-ADC0808/0809 interfacing
Programmable interval timer 8253
Programmable communication interface 8251 USART
Programmable peripheral interface 8255:
8255A is a versatile TTL compatible general purpose programmable I/O port
device designed by Intel to interface the CPU with its outside world such as
ADC, DAC, keyboard etc. It can be programmed according to the given
conditions and applications. It can be used with almost any microprocessor.
Address/data bus must be externally de-multiplexed.
Ports of 8255A: 8255A consists of three 8-bit bidirectional I/O ports (24
I/O lines) such as PORT A, PORT B, and PORT C which can be configured
as per the requirement..
Port A contains one 8-bit output latch/buffer and one 8-bit input
buffer.
Port B is similar to PORT A.
Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and
PORT C upper (PC7-PC4).
The three ports are further divided into two groups, i.e. Group A which
includes PORT A and upper PORT C. Group B includes PORT B and lower
PORT C. The two groups can be programmed in three different modes as
Mode 0, Mode 1 and Mode 2.
Mode 0(Simple I/O mode) –In this mode, Port A and B is used as two 8-bit
ports and Port C as two 4-bit ports. Each port can be programmed in either
input mode or output mode where outputs are latched and inputs are not
latched. Ports do not have interrupt capability.
Mode 1(Handshake or Strobe I/O) – In this mode either port A or port B

can work as 8-bit I/O ports, and port C bits are used for handshake signals
before actual data transmission. It has interrupt handling capacity and
input and output are latched.
Example: A CPU wants to transfer data to a printer. In this case since speed
of processor is very fast as compared to relatively slow printer, so before
actual data transfer it will send handshake signals to the printer for
synchronization of the speed of the CPU and the peripherals.
Figure 4.1: CPU interfacing with printer
Mode 2(Bi-directional data bus mode) – In this mode, Port A can be
configured as the bidirectional port and Port B can be either in Mode 0 or
Mode 1. Port A uses five signals from Port C as handshake signals for data
transfer. The remaining three signals from Port C can be used either as
simple I/O or as handshake for port B.
Architecture of 8255:
The architecture of the 8255 is shown in the figure 5.2, it has the following
blocks
Fig.4.2: Block diagram of 8255

Data Bus Buffer: It is a tri-state 8-bit buffer, which is used to interface the
microprocessor to the system data bus. Data is transmitted or received by
the buffer as per the instructions given by the CPU. Control words and
status information also transferred via this bus. The D0-D7 lines of this
block connected to the AD0-AD7 lines of µP.
Read/Write Control Logic: This block is responsible for controlling the
internal/external transfer of data, control word and status word. It accepts
the input from the CPU address and control buses, and in turn issues
command to both the control groups. This block has the following signals
CS’ (Chip Select): A LOW on this input line enables the communication
between the 8255A and the CPU. It is connected to the decoded address,
and A0 & A1 are connected to the microprocessor address lines.
CS’ A1 A0 SELECTION ADDRESS
0 0 0 PORT A 80 H
0 0 1 PORT B 81 H
0 1 0 PORT C 82 H
0 1 1 Control Register 83 H
1 X X No Seletion X
WR’: A low signal on this input line enables the write operation. With signal,
the microprocessor writes something into a selected I/O port or control
register.
RESET: This is an active high signal. It clears the control register and sets
all ports in the input mode.
RD’: It stands for Read. This control signal enables the Read operation.
When the signal is low, the microprocessor reads the data from the selected
I/O port of the 8255.
A0 and A1: It consists of 40 pins and operates in +5V regulated power

supply. Port C is further divided into two 4-bit ports i.e. port C lower and
port C upper and port C can work in either BSR (bit set rest) mode or in
mode 0 of input-output mode of 8255. Port B can work in either mode or in
mode 1 of input-output mode. Port A can work either in mode 0, mode 1 or
mode 2 of input-output mode.
These input signals work with RD’, WR’, and one of the control signal.
Following is the table showing their various signals with their result.
A1 A0 RD’ WR’ CS’ Result
0 0 0 1 0 Input Operation
PORT A → Data Bus
0 1 0 1 0 PORT B → Data Bus
1 0 0 1 0 PORT C → Data Bus
Output Operation
0 0 1 0 0
Data Bus → PORT A
0 1 1 0 0 Data Bus → PORT A
1 0 1 0 0 Data Bus → PORT B
1 1 1 0 0 Data Bus → PORT D
PA0 – PA7 – Pins of port A

PB0 – PB7 – Pins of port B
PC0 – PC7 – Pins of port C
D0 – D7 – Data pins for the
transfer of data
RESET – Reset input
RD’ – Read input
WR’ – Write input
CS’ – Chip select
A1 and A0 – Address pins
Fig.4.3: Pin diagram of 8255
Fig.4.4: The interfacing diagram of 8255 with the 8086 processor
Operating modes: There are to operating modes in the 8255, they are
Bit set reset (BSR) mode
Input-Output mode
Bit set reset (BSR) mode –If MSB of control word (D7) is 0, PPI works in
BSR mode. In this mode only port C bits are used for set or reset.
Fig.4.5: Control word for BSR mode
Input-Output mode – If MSB of control word (D7) is 1, PPI works in input-

output mode. This is further divided into three modes:
Fig.4.6: Control word for Input-Output mode
Ex: Interface 8255 with 8085 microprocessor and write an assembly

program which determine the addition of contents of port A and port B and
store the result in port C.
MNEMONICS COMMENTS
MVI A, 90 A ← 92
OUT 83 Control Register ← A
IN 80 A ← Port A;
MOV B, A B ← A;
IN 81 A ← Port B;
ADD B A ← A+B;
OUT 82 Port C ← A
RET Return
8251 USART (universal synchronous asynchronous receiver
transmitter):
8251 universal synchronous asynchronous receiver transmitter (USART)

acts as a mediator between microprocessor and peripheral to transmit serial
data into parallel form and vice versa. It takes data serially from peripheral
(outside devices) and converts into parallel data. After converting the data
into parallel form, it transmits it to the CPU. Similarly, it receives parallel
data from microprocessor and converts it into serial form. After converting
data into serial form, it transmits it to outside device (peripheral).
Architecture of 8251 USART: USART block diagram is shown in the fig.5.7. It

contains the following blocks: There are five different sections in this
diagram. These sections are as follows:
Read/ Write control logic

Transmitter
Receiver
Data Bus Buffer
Modem Control
Data bus buffer – This block helps in interfacing the internal data bus of
8251 to the system data bus. The data transmission is possible between
8251 and CPU by the data bus buffer block.
Fig.4.7: Architecture of 8251 USART
Read/Write control logic –It is a control block for overall device. It controls
the overall working by selecting the operation to be done. The operation
selection depends upon input signals as:
In this way, this unit selects one of the three registers- data buffer register,
control register, status register.
Modem control (modulator/demodulator):A device converts analog signals

to digital signals and vice-versa and helps the computers to communicate
over telephone lines or cable wires. The following are active-low pins of
Modem.
DSR’: Data Set Ready signal is an input signal.
DTR’: Data terminal Ready is an output signal.
CTS’: It is an input signal which controls the data transmit circuit.
RTS’: It is an output signal which is used to set the status RTS.
Transmit buffer –This block is used for parallel to serial converter that
receives a parallel byte for conversion into serial signal and further
transmission onto the common channel.
TXD: It is an output signal, if its value is one, means transmitter will

transmit the data.
Transmit control –This block is used to control the data transmission with
the help of following pins:
TXRDY: It means transmitter is ready to transmit data character.
TXEMPTY: An output signal which indicates that TXEMPTY pin has

transmitted all the data characters and transmitter is empty now.
TXC’: An active-low input pin which controls the data transmission rate of
transmitted data.
Receive buffer – This block acts as a buffer for the received data.
RXD: An input signal which receives the data.
Receive control –This block controls the receiving data.
RXRDY: An input signal indicates that it is ready to receive the data.
RXC’: An active-low output signal which controls the data transmission rate
of received data.
SYNDET/BD: An input or output terminal. External synchronous mode-

input terminal and asynchronous mode-output terminal
8251 Pin description: USART pin diagram is shown in the fig.5.8. The 8251
chip is Universal Synchronous Asynchronous Receiver Transmitter (USART).
It acts as a mediator between the microprocessor and peripheral devices. It
converts serial data to parallel form and vice versa. This chip is 28 pin DIP.
Fig.4.8: Pin diagram of 8251 USART
Control Words: There are two types of control word.

1. Mode instruction (setting of function)
2. Command (setting of operation)
Mode Instruction: Mode instruction is used for setting the function of the
8251. Mode instruction will be in "wait for write" at either internal reset or
external reset. That is, the writing of a control word after resetting will be
recognized as a "mode instruction." Items set by mode instruction are as
follows:
o Synchronous/asynchronous mode
o Stop bit length (asynchronous mode)
o Character length
o Parity bit
o Baud rate factor (asynchronous mode)
o Internal/external synchronization (synchronous mode)
o Number of synchronous characters (Synchronous mode)
The bit configuration of mode instruction is shown in Fig. 5.9 and 5.10. In
the case of synchronous mode, it is necessary to write one-or two byte sync
characters. If sync characters were written, a function will be set because
the writing of sync characters constitutes part of mode instruction
Fig.4.9: bit configuration of Mode instruction (Asynchronous)
Fig.4.10: bit configuration of Mode instruction (synchronous)
Control register: This is 16 bit register and the control word consists of two
independent bytes; first byte is called Mode Instruction (Word) and the
second byte is called the Command Instruction (Word). This register can be
accessed as an output port when C/D’ is Low.
Status register: this is input register and checks the readiness of

peripherals. This is addressed as input port when C/D’ is high. The port
addresses of both the registers are same
Command control word: Command is used for setting the operation of the
8251. It is possible to write a command whenever necessary after writing a
mode instruction and sync characters. Items to be set by command are as
follows:
o Transmit Enable/Disable
o Receive Enable/Disable
o DTR, RTS Output of data.
o Resetting of error flag.
o Sending to break characters
o Internal resetting
o Hunt mode (synchronous mode)
Fig.4.11: bit configuration of command control word
Status Word: It is possible to see the internal status of the 8251 by reading
a status word. The bit configuration of status word is shown in Fig. 5.12.
Fig.4.12: bit configuration of status word
Digital to Analog converters (DAC 0800)
The DAC0800 is an 8-bit, high speed, current output DAC with a typical
settling time (conversion time) of 100 ns. It produces complementary current
output, which can be converted to voltage by using simple resistor load. The
Reference voltage for conversion is provided using +Vref and –Vref. The
output can be amplified (optional) using an op-amp. DACs are used in
various applications such as Waveform generation, PWM, Motor control
Applications, DSP etc. Here we connect the output to a display device like
CRO. By simple programmings we can generate several types of wave forms
like Ramp, Saw-tooth, Triangular waveform etc.
The DAC 0800 consists of 8 data lines and REF voltage lines. The output
from 0808 DAC is current. When the DAC is given the digital input it
converts the Digital data to corresponding current, to convert current to
voltage with UA 741 as shown in figure 5.13 below:
Fig.4.13: 0808 DAC pin diagram
Pin 5 -12(A1, A2,--A8): Digital information can be fed to the DAC through
these lines.
Pin 2 &4: output analog current pins
Pin 3: Gnd
Pin 14 &15: these are the reference pins, generally pin 15 is grounded and
pin 15 is connected to +5V. The DAC0800 require a positive and a negative
supply voltage in the range of ± 5V to ±18V.
Pin 13: Vcc
The interfacing diagram of 800 with 8086 is shown in the fig.5.14.
Fig.4.14: 0808 DAC Interface with 8086
Analog to Digital converter (ADC 0808/0809)
The process of analog to digital conversion is a slow process, and the
microprocessor has to wait for the digital data till the conversion is over.
After the conversion is over, the ADC sends end of conversion EOC signal to
inform the microprocessor that the conversion is over and the result is ready
at the output buffer of the ADC. These tasks of issuing an SOC pulse to
ADC, reading EOC signal from the ADC and reading the digital output of the
ADC are carried out by the CPU using 8255 I/O ports.
The time taken by the ADC from the active edge of SOC pulse till the active
edge of EOC signal is called as the conversion delay of the ADC. It may
range anywhere from a few microseconds in case of fast ADC to even a few
hundred milliseconds in case of slow ADCs. The available ADC in the
market use different conversion techniques for conversion of analog signal to
digitals. Successive approximation techniques and dual slope integration
techniques are the most popular techniques used in the integrated ADC
chip.
Analog input voltage must be constant at the input of the ADC right from
the start of conversion till the end of the conversion to get correct results.
This may be ensured by a sample and hold circuit which samples the analog
signal and holds it constant for specific time duration. The microprocessor
may issue a hold signal to the sample and hold circuit. If the applied input
changes before the complete conversion process is over, the digital
equivalent of the analog input calculated by the ADC may not be correct
The analog to digital converter chips 0808 and 0809 are 8-bit CMOS,
successive approximation converters. This technique is one of the fast
techniques for analog to digital conversion. The conversion delay is 100μs at
a clock frequency of 640 KHz, which is quite low as compared to other
converters. These converters do not need any external zero or full scale
adjustments as they are already taken care of by internal circuits. These
converters internally have a 3:8 analog multiplexer so that at a time eight
different analog conversion by using address lines –
Fig.4.15: Block diagram of ADC 0808
Fig.4.16: Pin diagram of ADC 0808
General algorithm for ADC interfacing contains the following steps:
1. Ensure the stability of analog input, applied to the ADC.
2. Issue start of conversion pulse to ADC
3. Read end of conversion signal to mark the end of conversion processes.
4. Read digital data output of the ADC as equivalent digital output.
Fig.4.17: ADC 0809 Interface with 8086 diagram
Programmable Interval Timers (PTIs) 8253/8254
The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed
for microprocessors to perform timing and counting functions using three
16-bit registers. Each counter has 2 input pins, i.e. Clock & Gate, and 1 pin
for “OUT” output. To operate a counter, a 16-bit count is loaded in its
register. On command, it begins to decrement the count until it reaches 0,
then it generates a pulse that can be used to interrupt the CPU.
Features of 8253/54
The most prominent features of 8253/54 are as follows −
It has three independent 16-bit down counters.
It can handle inputs from DC to 10 MHz.
These three counters can be programmed for either binary or BCD count.
It is compatible with almost all microprocessors.
8254 has a powerful command called READ BACK command, which allows
the user to check the count value, the programmed mode, the current mode,
and the current status of the counter.
Fig.5.18: 8253 architecture diagram
In the above figure, there are three counters, a data bus buffer, Read/Write
control logic, and a control register. Each counter has two input signals -
CLOCK & GATE, and one output signal - OUT.
Data Bus Buffer: It is a tri-state, bi-directional, 8-bit buffer, which is used to

interface the 8253/54 to the system data bus. It has three basic functions −
Programming the modes of 8253/54. Loading the count registers and
Reading the count values.
Read/Write Logic: It includes 5 signals, i.e. RD, WR, CS, and the address
lines A0 & A1. In the peripheral I/O mode, the RD and WR signals are
connected to IOR and IOW, respectively. In the memory mapped I/O mode,
these are connected to MEMR and MEMW.
Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the
8253/54, and CS is tied to a decoded address. The control word register and
counters are selected according to the signals on lines A0 & A1.
A1 A0 Result
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register
X X No Selection
Control Word Register: This register is accessed when lines A0 & A1 are at
logic 1. It is used to write a command word, which specifies the counter to
be used, its mode, and either a read or write operation. Following table
shows the result for various control inputs.
A1 A0 RD WR CS Result
0 0 1 0 0 Write Counter 0
1 1 1 0 0 Write Control Word
0 0 0 1 0 Read Counter 0
1 1 0 1 0 No operation
X X 1 1 0 No operation
X X X X 1 No operation
Counters: Each counter consists of a single, 16 bit-down counter, which

can be operated in either binary or BCD. Its input and output is configured
by the selection of modes stored in the control word register. The
programmer can read the contents of any of the three counters without
disturbing the actual count in process.
Fig.4.19: 8253 Pin diagram
8253/54 can be operated in 6 different modes. In this chapter, we will

discuss these operational modes.
Mode 0(interrupt on Terminal Count): It is used to generate an interrupt

to the microprocessor after a certain interval.
Initially the output is low after the mode is set. The output remains LOW
after the count value is loaded into the counter.
The process of decrementing the counter continues till the terminal count is
reached, i.e., the count become zero and the output goes HIGH and will
remain high until it reloads a new count. The GATE signal is high for normal
counting. When GATE goes low, counting is terminated and the current
count is latched till the GATE goes high again.
Mode 1(Programmable One Shot): It can be used as a mono stable multi-

vibrator. The gate input is used as a trigger input in this mode. The output
remains high until the count is loaded and a trigger is applied.
Mode 2(Rate Generator): The output is normally high after initialization.

Whenever the count becomes zero, another low pulse is generated at the
output and the counter will be reloaded.
Mode 3(Square Wave Generator): This mode is similar to Mode 2 except the
output remains low for half of the timer period and high for the other half of
the period.
Mode 4(Software Triggered Mode): In this mode, the output will remain
high until the timer has counted to zero, at which point the output will
pulse low and then go high again.
The count is latched when the GATE signal goes LOW. On the terminal
count, the output goes low for one clock cycle then goes HIGH. This low
pulse can be used as a strobe.
Mode 5(Hardware Triggered Mode): This mode generates a strobe in

response to an externally generated signal. This mode is similar to mode 4
except that the counting is initiated by a signal at the gate input, which
means it is hardware triggered instead of software triggered. After it is
initialized, the output goes high. When the terminal count is reached, the
output goes low for one clock cycle.

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EEC 364: INTRODUCTION TO MICROPROCESSORS

Interfacing Of Peripherals to 8086

Programmable I/O ports 8255: modes of operation of 8255

Digital to Analog converters- DAC 0800 interfacing

Analog to digital dataconverters-ADC0808/0809 interfacing

Programmable interval timer 8253

Programmable communication interface 8251 USART

Mode 1(Handshake or Strobe I/O) – In this mode either port A or port B

Figure 4.1: CPU interfacing with printer

Fig.4.2: Block diagram of 8255

CS’ A1 A0 SELECTION ADDRESS

A0 and A1: It consists of 40 pins and operates in +5V regulated power

0 1 0 1 0 PORT B → Data Bus

1 0 0 1 0 PORT C → Data Bus

0 1 1 0 0 Data Bus → PORT A

1 0 1 0 0 Data Bus → PORT B

1 1 1 0 0 Data Bus → PORT D

PA0 – PA7 – Pins of port A

Fig.4.3: Pin diagram of 8255

Bit set reset (BSR) mode

Fig.4.5: Control word for BSR mode

Input-Output mode – If MSB of control word (D7) is 1, PPI works in input-

Fig.4.6: Control word for Input-Output mode

Ex: Interface 8255 with 8085 microprocessor and write an assembly

OUT 83 Control Register ← A

8251 universal synchronous asynchronous receiver transmitter (USART)

Architecture of 8251 USART: USART block diagram is shown in the fig.5.7. It

Read/ Write control logic

Fig.4.7: Architecture of 8251 USART

Modem control (modulator/demodulator):A device converts analog signals

DSR’: Data Set Ready signal is an input signal.

DTR’: Data terminal Ready is an output signal.

CTS’: It is an input signal which controls the data transmit circuit.

RTS’: It is an output signal which is used to set the status RTS.

TXD: It is an output signal, if its value is one, means transmitter will

TXRDY: It means transmitter is ready to transmit data character.

TXEMPTY: An output signal which indicates that TXEMPTY pin has

RXD: An input signal which receives the data.

Receive control –This block controls the receiving data.

RXRDY: An input signal indicates that it is ready to receive the data.

SYNDET/BD: An input or output terminal. External synchronous mode-

Fig.4.8: Pin diagram of 8251 USART

Control Words: There are two types of control word.

Fig.4.9: bit configuration of Mode instruction (Asynchronous)

Status register: this is input register and checks the readiness of

Fig.4.12: bit configuration of status word

Fig.4.13: 0808 DAC pin diagram

Pin 2 &4: output analog current pins

Pin 13: Vcc

The interfacing diagram of 800 with 8086 is shown in the fig.5.14.

Fig.4.14: 0808 DAC Interface with 8086

Fig.4.16: Pin diagram of ADC 0808

1. Ensure the stability of analog input, applied to the ADC.

2. Issue start of conversion pulse to ADC

3. Read end of conversion signal to mark the end of conversion processes.

4. Read digital data output of the ADC as equivalent digital output.

Fig.4.17: ADC 0809 Interface with 8086 diagram

The most prominent features of 8253/54 are as follows −

It has three independent 16-bit down counters.

It can handle inputs from DC to 10 MHz.

It is compatible with almost all microprocessors.

Fig.5.18: 8253 architecture diagram

Data Bus Buffer: It is a tri-state, bi-directional, 8-bit buffer, which is used to