Table of Contents (1) Intreduction for the Intel's 8255 series of programable peripheral interface. (2.) Experiments 1 ‘HL. 2. 3. E13. Basic Data Transmission and Reception Data transmission. Data reception. Detecting and displaying the pulses. Introduction for the Intel's 8255 Mode 1. An exapmie of 8255 Mode I. . Data transmission handshake. . Data receiving handshake. LED Matrix Character Generator Controller . Basic LED matrix contro! ON/OFF,Flash and SHIFT. . LED matrix character display. . Character shifts and changes (1). . Character shifts and changes (2). Step Motor Control Step motor principles. . Step motor basic control. Ell. B12. Step motor direction rotation control Controlling step motor's continous rotation and “inch motion” function. Coordinationg step motor function. DC Motor Control DC Motor principles. 1- 10 P 65- 69 P 70-77 P 78 - 82 P 83 - 8&7 P 88 - 92 P 93 -100 P 101 -103B14. B15. B16. E17. E18. E19. E20. E21. #22. Starting and Stopping control. P 104 -108 Direction control. P 109 -113 Rotation speed control. Pil4-i18 Starting Stopping,Dicection and Rotation —_-P 119 -124 Speed(acceleration and deacceleration) control. Digital/ Analog Conversion Control Introduction to Digital/Analog conversion. P125 -127 Introduction of Digital/ Analog chip DAC 08. P128 -129 Digital to Analog voltage conversion. P130 -134 Use keyboard to control rises.and falls in P135 -139 voltage. To generate a Triangular wave. P140 -144 To generate a Square Step wave. PI45 -149 Analog/Digital Conversion Control Introduction to Analog/Digital conversion. P150 Introduction of Analog/Digital PIS1 -154 chip ADC 0804. Analog voltage to digital data conversion. P155 -160(1.) Introduction for Intel's 8255 series of programable peripheral interface. The input/output and memory interface are two corresponding parts of the bus control logic. The interface and bus contro! logic are directly connected, because of this the interface must have timing that corresponds to the bus control logic so as to be able to conveniently send or receive signals, An ideal input/output interface must have the following capabilities: 1) Its address and memory must determine whether or not to use the signal. And if so, the interface must also select the register. 2) It must decide whether the bus can be connected and if data can entered or retrieved. 3) From the input/output interface, data should be able to be extracted or entered, and the interface devise should convert the data to the appropriate format. 4) After the interface receives or sends data to the bus, it should send back a ready signal so that the CPU will know that the data transfer has been completed. 5) The interface must send out interrupt requests, receive respond signals and send out interrupt forms. 6) The interface must accept reset signals so as to reset itself and other input devices. Intel's 8255 series of programable peripheral interfaces provides a good example of a parallel interface. Within the series three models are offered: 8255A, 8255A-5 and 82CSSA. Of the three models, the 82C55A has the highest frequency (8 Mhz) and uses CHMOS manufacturing. The 8255A-5 uses 5 Mhz as its work frequency. Although the 8255A has the lowest frequency, all three models function similarly.As shown in figure 1-1, the 8255 series is a 40 pin, DIP LSI, mainly used to support Inte! products and CPU systems, Because of its strong compatibility, it can also be used with other CPUs such as 280, 6502 etc. .. . Such interfaces are therfore called general purpose programable input/output devices. Accepting our first understanding of the 8255 interface, and after reading how to use the MTS-88.C’s program writing function, you should be able to format the 8255 interface to coordinate experiments and use in other applications. From the figure !-1(a) and (b) we can see that the 8255 has A,B and C input and output ports. Of these, the C port can be divided into 2 groups and in this way have 24 input/output pins. The three ports are divided into A and B groups which are controlled by the A and B controllers. Inside the 8255, data is completed using an 8 bit internal data bus. The bus buffer is a data input/output control interface between the 8255's interior and the CPU system. Finally, to make the 8255 work it is necessary to write in the appropriate control characters to control the registry. Only then will there be sufficient data to decided the communication form.8255A Programmable Peripheral Intertace (PPI) Figure 1-1 (a) Block diagram of the 8255A. (b) Pin lavout. (Courtesy of Intel corn) aE ion of the 8255 pi Each 8255 has a total of of 40 pinouts, and for a detailed description, please refer to figure 1-1-(b) VCC - The +5V power supply pin. A 0.1uF capacitor between pins 26 through 7 is recommended for decoupling. GND - Ground DOD? - Data Bus: The Data Bus lines are bidirectional three-state pins connected to the system data bus. RESET - A high on this input clears the control register and all ports (A, B, C) are set to the input mode with the "Bus Hold " circuitry turned on, CS- Chip Select: Chip select is an active low input used to enable the 82C35A onto the Data Bus for CPU communications. RD - Read: Read is an active low input control signal used by the CPU to read status information or data via the data bus, WR - Write: Write is an active low input control signal used by the CPU to load control words and data into the 82C55A. AQ-A1 - Address: These input signals, in conjunction with the RD and WR inputs, contro! the selection of one of the three ports or the control work register. AO and Al are normally connected to the least significant bits of the Address Bus AO, Al. PA 0-PA 7 - Port A: 8-Bit input and output port. Both bus hold high and bus hold low circuitry are present on this port. PBO-PB7 - Port B: 8-bit input and output port. Bus hold high circuitry is present on this port. PCO-PB7 - Port C: 8-bit input and output port. Bus hold high circuitry is present on this port.Control of the 8255 Inside the 8255 there are four registers which are related to the basic operations of the 8255 as shown in figure 1-1. Figure 1-2 The Basic Operation Of The 8255 Al | ao] RD| WR | CS | — OPERATION o | o | o | 1 | © |PoRT a -> DATA BUS o | 1 | 0 | 1 | © | PoRTB -> DATA BUS 1 | 0 | 0 | 2 | © | por c -> DATA Bus o | o | 1 | 0 | 0 [DATA BUS -> PORT A o | | 1 | 0 | 0 {DATA BUS -> PORT B 1 | 0 | 1 | o | o | DATA BUS -> PoRT Cc 1 | 1 | 1 | © | © | Data Bus -> CONTROL x [x | x | x | 2 | DATA Bus -> 3 STATE 1}ifojfifo ERROR x | x | 1 | 1 | © | DATA BUS -> 3 STATE From the figuce 1-2 shown above,it can be seen that when A1A0-00, then the machine will select the A port register. When A1A0-10 the C port will be selected. If A1A0-11, then the control register will be selected. Remember, the control register is write-only.and can not be read. The 8255 has the following different operating modes: 1) Mode 0 - basic input/output 2) Mode 1 - strobed input/output 3) Mode 2 - strobed bidirectional bus input/output Before using the above three modes it is necessary to first enter the control codes into the control register.CONTROL WORD D7 | D6} DS} D4 | D3} D2} D1 | Do GROUP B PORT C (LOWER) 1=INPUT O=OUTPUT PORT B ASINPUT O=OUTPUT ODE SELECTION} {>} 0=HODE 0 1=HODE 1 GROUP A PORT C (UPPER) (____ sy gstnpur O-OUTPUT PORT A ‘A= INPUT O=OUTPUT MODE SELECTION) 00=HODE 0 KS, 01 SHOE. 1 IX=HODE 2 WODE SET FLAG eae Cas Figure 1-3 Hode Definition FormatFrom figure 1-3, it can be seen that when ALAQ=11, the function of every bit which located in control register is divided into the following: 1) D7#1 - Enables control words to function. 2) D6, DS - Selects one of A port's three operating modes. 3) D4 - Chooses port A's input or output, 0 shows the output mode. 4) D3 - Defines the input or output status of the upper four bits {upper nibble) on C port. 5) 22 - Selects one of B port's two work modes. 6) DI - Sets B port for input or output. 0 will indicate if B port is in output mode. 7) DO -Sets the input or output status of the four lower bits (nibble) on port ¢. CONTROL WORD [p7 [pss ]p4] pa} 2] pn o| BIT SET/RESET O=SET x x e 1=RESET DON’T CARE ilefsia id ifolilo 1|Bo ofalilo ijBi ofofoli 1 — B2 eo BIT SET/RESET FLAG O=ACTIVE __ Figure 1-4 Bit Set/Reset Format ?In the previous section mode-setting has been explained, it is important to bear in mind that the control board only functions when D7-1. Figure 1-4 shows the other form of the control register. When D7-0, it can be used to set or reset the bits of C Port. After attaining C port status/control, form setting becomes easier,8255's Mode 0 8255's Mode 0 is used for basic input/output. It has the following 16 possible combination forms: Convo. won ‘conrnt, sonD #4 7 Ds BS 0A 03 02 D1 Be ERErers CREPE) | + en rn aL ae parma OS [pte rorree OS ft verte maf fe me} eff ape ere a} eee Clelelelel[el: ass ‘ a |= nerves {le }—+4— rc-row rt core a} rea apo rare ‘conto, wow #7 “yl as eae Rica na— eff ee a ae sheys seers she raecommon wore #3 pte rernce wm—t ff, ap pe Geert Gabe tr ref f[ ee ref off Glebe) elle Lele ae rue ee Cleperteter Te Tete Tel)(2). Experiments 1. Basic data transmission and reception: Bi. Data transmission. 1) Title: Basic Data Transmission. 2) Goal: Understanding the way the CPU sends data in order to transmit and receive data from other machines so as to control them. 3) Experimental tools and materials: MTS-88.C, breadboard, jumpwire, needle-nosed pliers, wire-cutters, multi-meter, flat cable, 1C 74LS245,100 k ohm resistor x 8, 470 ohm x 8, LED x 8, transistor (59013 x 8. It is recommanded to use the MTS-88.C 1/0 BOARD -01 to instead of the above materials. 4) Explanation of principles: 8255 mode 0 will be used to do output applications, 5) Circuit diagram +5V f oo fear fica fine fionc foo [ise foo mTs-88.C I/0 BOARD-01 it 33 bhbehetss iaSeGRS SSRIS Saar aeeE SRE eos ' 33 3MTS-886 170 BOARD-O1 waDEL: 10-01 MTS-98C MOTHER BOARD6) Program flow chart and source listing FLOW CHART E1 STAR’ SET 6255 1 MODE 0 2 PORT B:OUTPUT mi MOVE DATA 'TO AL, WRITE AL TO PORT B ‘STOP VI FLOW CHART AND SOURCE LISTING 0000:0400 BOBO 0000:0602 E613 0000:0404 BOFF 0000:0406 E611 0000:0408 F4 Mov our Mov our HLT AL,80 ;LOAD AL WITH CONTROL BYTE 13/AL ;MODE 0 IS SELECTED FOR PORT B AND OUTPUT OPERATION AL,FF ;LOAD AU WITH FFH 11,AL ;HRITE TO PORT B 13a Confirm circuits are connected correctly by checking with the circuit diagram of 1/0 BOARD-01. b- Input program. c- Execute program and observe experiment results. d- If the setting value equals FF then the LEDs should light up 8) Experiment results VIII RESULT AL LED7 LED6 LEDS LED4 LED3 LED2 LED1 LEDO ° 1K 0 0 0 ° ° ° 1 2H 0 ° ° ° 0 ° 1 ° 4H ° ° ° ° ° 1 ° ° 8H ° ° ° ° 2 ° ° ° 10H 0 ° ° 1 ° ° ° ° 20H ° ° 1 ° ° ° ° ° 40H ° 1 ° 0 ° ° ° ° 80H 1 ° ° ° ° ° ° ° 14E2. Data reception. 1) Title: Basic data reception 2) Goal: Understanding the CPU's many ways of accepting data in order to use the CPU to process erternal styles of data to carry out effective applications. 3) Experiment tools and materials: MTS-88.0, breadboard, jumpwire, needle-nosed pliers, wire-wire cutters, multi- meter, flat cable, 1C74L82455, 4.7 k ohm resistor x 8, DIP, SW.8 bit x 1. It is recommanded to use the MTS-88.C 1/0 BOARD-01 to instead of the above materials. 4) Explanation of principles: Use the 8255 mode 0 to do input applications. 5) Circuit diagram ax PP of are f ome fame fae om ey eyeiy ys J1/E2 mrs-88.C 1/0 BOARD-01MTS-@8.5 170 BOARD-01 apeLs 10-01 nist eae6) Program flow chart and source listing FLOW CHART E2 START 1 SET 8255 : 1 MODE 0 2 PORT A: INPUT 1 READ DATA FROM PORT A VI: FLOW CHART AND SOURCE LISTING 1 000030400 BO90 MOV AL,90 ;LOAD AL WITH CONTROL BYTE 2 0000:0402 E613 OUT 13,AL ;MODE 0 IS SELECTED FOR PORT A AND INPUT OPERATION 3 0000:0404 £410 IN Ab,10 ;READ PORT A 4 0000:0406 Fa HLT. 177) Operating steps a- Confirm circuits are connected correctly by checking with the circuit diagram of 1/0 BOARD-01. b- Input program. c- Execute program and observe experimental results. d- When the program is executed wait until it has stopped and then simultaneously press F3 and R, then you can see the registries AX, BX, CX and DX. If the variable is preset to AL, then the experiments will be correct. 8) Experiment results. VIII: RESULT SW7 SW6 SWS SW4 SW3 SW2 SW1 SWO AL OK "Om ON ON ON ON ON OFF O78 CH Oy ON OH OH ON OF OM O28 ON ON ON ON ON OFF ON ON 04H GH- ON ON ON OFF ON OW OOM | OeH ON ON ON OFF ON ON ON ON 10H ON ON OFF ON ON ON ON ON 20H ON OFF ON ON ON ON ON ON 40H OF? ON ON ON ON ON ON ON 80H