Honeywell Ho20000 4551072 HOREVWELL/SS ELEK, MIL ee Preliminary HIGH-PERFORMANCE CMOS GATE ARRAY FEATURES Performance Optimized Series of 1.2-Micron CMOS. + Proven VLSI Design System (VDS) Toolkit™ Gate Arrays * Boundary and intemal Scan + TTLand CMOS V/O Interfaces. + VHSIC Built-In Self Test (BIST) Testabilty Protocols + Over 110 Library Macrocells Designed for Optimized ‘System Performance + MIL-M-38510 Qualification Pending + Standard Megacell Capablity + MIL-STD 888 Class B and Modified Class S Screening High Density Advanced Packages «Available in Miltary and Commercial Versions Honeywell's, CMOS gate arrays offer the designer ‘complete ASIC design capability coupled with state-of- the-art CMOS 1.2-micron manufacturing capability Depending on the system design, three compatible array families are available: HC, HCT and HCS. ARRAY TYPES CT. CS) r Tactical | Strategic cea Military Miltary Radiation Environment Tactical | Full Strategic cos. Process ee Array Sizes a “Consul Honeywell or avalabiy. Teh ‘This data sheet addresses the design and manufacturing capability of Honeywell's HC high-performance CMOS gate array. [ Honeywell 1150. choyenne itn. ia, Colorado Springs, Colorado 80906 (719) 540-9007 Tolox #452639DESCRIPTION ‘The high-performance HC20000 gate array offers improved system performance, testability and space reduction benefits to advanced military avionics and metal CMOS process. The Array is based upon a unique ten-transistor physical coll that allows architecture specific memory elements to be built on-array for commercial CPU designers. The HC20000 is manu- improved system performance. factured using a production level 1.2-micron, two-level HC ARRAY PHYSICAL ATTRIBUTES Device HC20000 Total Gates (67) 20,097 Equivalent 2-Input NAND Gates * 17,382 Total Pins 284 Total YO 238 Input Only 98, Power & Ground 40. Test/Clock 6 Usable gate at 05% uilzation, includes ~2K est gates HC FEATURES/BENEFITS Features Benefits + 17K Equivalent Usable Gates + Flexible System Partitionir + 238 /O Pins ‘ewer /O Boundary Crossings + TTLand CMOS Interfaces + Optimized System Performance Level of Logic Integration + Performance Programmable Macrocelis + Soft Macrocell Function Capability + Macrocell Library Compatibility with HCT and HCS CMOS Gate Arays + Proven VLSI Design System (VDS) Tookit™ + User Selectable Built-In Test Options + Advanoed Packaging with Logic Densities of 20,000 Gates/Inch? of Board Space + MIL-M-38510 Qualification Pending + Dedicated Quick-Turn Prototype Facility + Reduced Board Space Required + Increased System Reliability + Low-risk, Low-cost Implementation of DoD Standard Communications and Testability Protocols + Upward Migration Path for Systems Requiring Strategic Radiation Hardness + Minimized Design Risk + Faster Deployment of Miltary Systems + Support for Present and Emerging DoD Standards, + Simpltied Design Debug and System Test + Reduced Manufacturing Test Time and Cost + Reduced Board Space Required + Reduced Program-Specitic Qualification Costs + Quicker Deployment of Military Systems HoneywellDESIGN AND MANUFACTURING CAPABILITIES Honeywell offers a complete design and manufacturing capability, illustrated in Figure 1. The following table PHYSICAL DESIGN SYSTEM ParTeawaenenaTion | VHSIC ‘TECHNOLOGY WAFER, FAB block. [SIMULATION VECTORS + PACKAGED UNITS: or Berney lists the corresponding software for each highlighted GENERATION ‘SYSTEM | resrPRoanan Ls! TEST EQUIPMENT FIGURE 1. HONEYWELL'S DESIGN AND MANUFACTURING CAPABILITIES VDS SOFTWARE™ AND MACROCELL LIBRARY Customer Service Macrocell -Library VDS Software™ > HDB = Symbols ~ VERIFY = Simulation Models ~ DELAYD® = Tech Table = DEAD Front-End Design) = Design Manual - NETLISTERS ~ SIM INTERFACE ~ DAMSEL™ - Transistor Schematics - xPL Physical Design ~ Topology ~ MERLYN-G System ~ ERC/DRCILOGIOVPG (Back-End Design = CALMA ~ PERFBIAS™ ‘Teet Generation ~ RIGEL™ Models ~ RIGEL?« System SNS + MIGHT™ GaN 3 HoneywellVLSI DESIGN SYSTEM (VDS)™ VDS™ is a design methodology and CAD system that helps assure first pass design success resulting in faster deployment of a military system. Honeywells design methodology consists of the VDS Tookkt™, a physical design service, and a test generation service. The VDS Toolkit™ is a comprehensive, technology-independent ASIC design package that equips the ASIC designer with VDS Software™ and a macrocell library. The toolkit is accessed via a user-friendly, graphical human interface, MENTOR™ APPLICATION NETEDSYMED DESCRIPTION ‘Schematic Entry ‘Schematic Capture Error Checking ~ fanout exceeds drive capability + unconnected macro inputs/outpute external signal not connected ‘through VO butter Design Statistics + callinventory and utilization = WO inventory and utlization + total numberof nets and pins Propagation Delay Calculation = Intrinsic delay of each path within ‘each macrocell + additional delay of fanout and interconnect capacitance + atuser-defined power supply voltage and junction temperature + preipost route options Functional Simulation Fault Analysis Static Timing Analysis ‘Tost Program Generation + produces ANDO compatible functional ‘andlor scan test vectors ~ accepts output fies from Mentor, DAISY, ‘and LASAR-6 simulators ‘Automatic Test Vector Generation ‘Automatic Placeinent = Notists received by magnetic media, or dial-up field transfer ‘Automatic Routing ‘Automatic Performance Biasing ‘QuicksiM poner providing maximum flexibility and efficiency in the front- end design process. All phases of the design cycle are supported by Honeywell from schematic capture through test vector generation. The VDS Tookit™ is currently available on Mentor workstations and can be ported to other design platforms. HONEYWELL, ‘vos TOOLKIT™ HONEYWELL, VDS™ DESIGN ‘SERVICES EXPAND VERIFY™ VERIFY DELAY" ‘SIM VF MODELS LASARS. LASAR-6 DAMSEL™ MIGHT™ RIGEL™ XPL MERLYN-G PERFBIAS™ HoneywellSILICON UNDERLAYERS ‘A gate array is a semicustom device assembled on a matrix of X columns by Y rows of physical cells. The physical cell in the HC Array Family consists of ten. Uncommitted transistors. This array of uncommitted transistors, along with the VO ring, are called underlayers and are common to all personali- zations of the gate artay. The V/O ring consists of VO butfers, a clock distribution network, and power busses. The macrocell library contains the data needed to connect the transistors of one or more physical cells to forma logic function. The HC aray's VO buffers have the characteristics: following + Builtin configurable test logic + Dedicated VO and input only functions. + 8mA TTLoutput drive + CMOS or TTL input and output configurable interface + ESD input protection greater than 2000 volts Each VO butfer can be independently used as an input only, output only, or VO function. The output butter has a high impedance state. The input and output portions of the /O butter act independently CMOS/TTL INPUT INTERFACE CHARACTERISTICS Interface Logic HI Logic LO Switchpoint CMOS: 35V min 1.5 V max Vadi2 typ. TH 2.0 V min (08 Vmax 1.3. V typ. HoneywellHC20000 HONEYWELL/SS ELEK, MIL 03 DE) ¥ssia72 coogeda s 4551872 HONEYWELL/SS ELEK, MIL O3E 00241 0 TY4Q~\)-0g PERFORMANCE PROGRAMMABLE MACROCELL LIBRARY Honeywell provides an accurately modeled and highly flexible macrocell library that has been optimized for maximum synchronous system performance. The library contains approximately 110 hard-wired data path ‘elements ranging from inverters to flip-flops, adders and shifters. The CMOS 1.2-micron macrocell library has been characterized at the device level through extensive SPICE modeling. The resulting SPICE K-actors are stored in a technology table and used in circuit simulation and the simulation results compared to actual test arrays. Each macrocell has been evaluated over the entire military temperature range, voltage and process spectra to ensure accuracy and guaranteed worst case delays. ‘The CMOS 1.2-micron macrocell library provides these benefits in new system designs: = a common library of over 110 cells including bit-width programmable register, counter and multiplexer, ‘macrocelis to maximize array efficiency, and minimize dynamic power. LSI FUNCTION PERFORMANCE - performance programmable NAND, NOR and inverter ‘macrocells to optimize critical path performance. - static and dynamic register bits are constructed using CMOS ‘transmission gates and optional serial-scan testability to allow the tradeoff of minimum register area (dynamic) with minimum register power (static) during the design process. = architecture specific soft RAM macrocells can be constructed to provide improved system performance by eliminating /O delays required during accessing off-array memory, ‘The table below provides performance data for selected LSI functions designed with the CMOS macrocell library. ‘The Maorocell Performance Guide shows the area, intrinsic delay, and additional metal loading delays for ‘macrocelis in the HC Typical Case (1) ] Worst Case (2) Celt Function (ns) (ns) Count 16-bit Adder/Subtractor 7 13 302 ‘82-bit Fast Adder with Full Carry Look Ahead 14 23 445 S2-bit x 32-bit Word Register File. Read 8 15 4,300 (1 Read /1 Write) Write 16 30 ‘16-word x 1-bit RAM (1 Read / 1 Write) i 12 108 (1) Vag=5.0V, 7; 25, Prooss = Nominal Byars '=+150°C, Process = Worst caso HoneywellHONEYWELL/SS ELEK, MIL 03 Def 4Ssua72 ooooaN2 7 HC20000 = 4551872 HONEYWELL/SS ELEK. MIL O3E 00242 Db THya--0g — MACROCELL PERFORMANCE GUIDE (Tj = 25°C; Vdg =5.0V; Tig = 118; Process = Nominal) (Typical) Gell_[ Cell | Coll | Base |Load Factor | Base |Load Factor | Input Coll Description Name | size | count | Rising | Rising | Falling | Falling | Cap. (wxh) (ns) | (rep) | ts) | (nsipF) | (oF) Inverters/Butfers Inverter wwvo | xt | ot | 183 527 188 586 492 Power Inverter invt | txt 1 | 208 “360 081 235 365 Double Power inverter inva | x2 | 2 | 206 178 ove | 142 | 668 Balanced Drive Inverter INV3 | 1xt 1 207 371 116 369 334 Non-Inverting Butter Burt | ix | 1 | 469 518, B71 406 | 127 Delay Macro Burs | 2x1 | 2 | 1gs6 | 1024 | 1058 | 713 | 127 AND, OR, NAND, & NOR 2-NAND ND2 | 1x1 1 276 983 186 850 128 3-NAND. NDS. 4x1 1 342 97 301 1.070 113 4-NAND ND4 1x2 2 477 911 494 1.32 423 6-NAND NDe | 2x2 | 4 | 1.195 520 | 1.118 | 431 126 2-AND AND2 | 1xt 1 | S33 | 1.108 539 | 640 | 1423 S-AND ANDS | 2xt 2 | 1.245 1.173 681 734 123 Power 2-NAND ND2H | 1x2 Z 289 388 214 356 364 Power 3-NAND NOSH | 1x2 2 A19 493 386 548, 283 2NOR NOR2 | txt 1 512 1.337 194 446 191 3-NOR NOR3 | 3x1 3 | 1.041 542 839 409 151 6-NOR NOR6 | 2x2 4 | 1.362 599 1.010 650 126 Power 2-NOR NoRH | 1x2 | 2 | .440 673 158 252 | 979 2-0R one | 1x1 ies (ee20) 104 782 743 | 128 AND/OR, OR/AND Gates 4-2 AND/ORinvert aon | at | 1 | 43 | 1.638 218 745 112 2-2 AND/OR/Invert ao | at | 3 | 1.139 527 983 391 128 3-3 AND/OR/Invert aos | 3xt | 3 | 1042 | 1.010 | 1.028 645 127 Power 1-2 AND/OR/Invert AOIH | 1x2 485 946 211 407 267 4-2 OR/AND/Invert oan | ax | + | 450 | 1.509 306 939 129 2-2-1 OR/AND/Invert OAIS | axt 2 840 1714 603 1.106 131 Power 1-2ORV/AND/Invert | iAH | tx2 | 2- | 471 754 273 432 | 268 3-3-3 AND/OR aos | 2x2 | 4 | 50 97 779 | 1.089 | 114 4-2:3-4 ANDIOR aos | 2x3 | 6 | 930 997 986 | 1190 | 115 1-3 OR/AND oa | 22 | 4 | 639 903 -766_| 1.037 _| 203 Exclusive OR/NOR Gates Exclusive-OR exon | ax1 | 3 | 913 535 704 | 438 225 Exclusive-NOR EXNR | ax1 | 3 | 575 Bat 1667 | 461 247 4-Bit Exclusive-OR Exo4 | 2x3 | 6 | 1.730 532 «| 1.748 | 1.938 | 202 Exos | es | 18 | 2.298 sai atta | 4s 263 eExng | 4x5 | 20 | 2612 | 537 | 2323 | 439 185 2-2 AND/Exclusive-OR axoz | 22 | 4 |i2i7 | svt | tie | (495 143 Priority/Decode 2 t0 4 Decode w/ Enable vece | 2x5 | 10 [1469 | 588 | ta7za | 441 188 310 8 Decode w/ Enable pecs | 6xs | te | 1.852 | 525 | 1690 | 401 324 8-Bit Priority Selector SEL8 | 3x5 15 | 1.070 1.398 861 630 233 4-Bilt Priority Encoder enca | 2x2 | 4 | 500 | 1.438 514 | 755 248 7 HoneywellHONEYWELL/SS ELEK. MIL O3 DEM 4551872 Goo0e43 4 HG20uvy 1 Ly 4351872 HONEYWELL /SS ELEK. MIL O3E 00243 D Tzya-y)-0g — MACROCELL PERFORMANCE GUIDE (continued) (Tj = 25°C: Veg =5.0V; Tin = ts; Process = Nominal) (ypica Cell | Cell | Cell | Base |[LoadFactor | Base [Load Factor | input Coll Description Name | size | count | Rising | Rising |Fating | Falling | Cap. (wxhy (ns) (nsipF) | (ns) | (nsipF) | (PF) Multiplexers 210 1 Multiplexer uxca} 2xt | 4 | 1.072 547 | 1091 | 496 119 Mxe2 | 2x1 210 1 Multiplexer with mxoa/| 3x2 | 9 | 1.362 1042 [1.335 | 1.053 | 138 Complement Enable xe | 3x1 410 1 Multiplexer with mxca} 2x2 | 8 | 1.900 960 |1.474| 869 196 Enable MCE4 | 2x2 8 to 1 Multiplexer with MxCB/} 2x3 16 1.622 1.092 1.886 1.160 122 Enable Mxes | 2x5 Flip-Flops (F/F) Dynamic F/F prc] 2x2 | 6 | 1.456 985 | 1497] 709 126 Dre | 2x1 Dynamic F/F wiCik Drca| 3x4 | 15 | 1.964 seo | 1.203 | 764 124 En. & Syne. SevCir. DFE2 } 3x1 Dynamic F/F wiCik. Dros} 2x4 | 10 | 1.734 1.055 | 1.663] 802 176 En, DFES | 2x1 Dynamic FIF wi 2-4 Decay | 2x4 | 10 | 1.850 1061 | 1.791 | 844 167 MUX Data Input DFE4 | 2x1 Dynamic F/F wiCik orcs | 3x4 | 15 | 2130 1019 | 2042] 759 207 En. and 2-1 pres | 3xt MUX Data In. Static FF w/ Cik orce/| 2x3 | 10 | 2680 541 2273) 466 257 En, & Sync. Clr. DFEG | 2x2 Single FF srr2 | 2x4 | 8 | 137 488 126 | 550 130 ‘Quad D Latch aor | 2x4 | 8 796 477 959 | 1503 302 SCAN Flip-Flop (F/F) SCAN Reg Cont! wieset |Dsce/| 5x3 | 15 633 osas | 511 | 0656 420 SCAN FIFEle.wieset. | DSE6 | 5x1 | 5 | 1.264 944 | 42a | 651 150 SCAN Reg. Cont!wiset |DSCe/| 5x3 | 15 | 590 ‘078 60s | ‘072 312 SCAN FiF Ele. wiset oses | 5x1 | 5 | 1.265 944 | 1242] 652 150 Miscellaneous 4-BitUp/Dn Counterw/ | CNT4 | 5x7 | 35 | 2.03 509 2.46 | 989 180 Parallel Load 4-Bit Shitter sro | 3x4 | 24 | 1.240 528 1187 | 455 258 SFEI | 3x4 4-Bit Adder Apps | exe | 48 | 1.869 794 1621 | 805 263 4-Bit Partial Adder apps | a3 | 9 | 1.808 1.07 1845 | 878 257 Single-Bit Adder appt | 23a | 6 | 1.713 768 1586 | 688 215 4-Bit Comparator cmp1 | 3x5 | 15 | 1.819 540 1774 | 429 241 4-Bit Magnitude Comp. | CMP4 | 4x7 | 28 | 2.081 1163 | 2050] 794 198 4-Bit Incrementer inca | 4x6 | 24 | 1.530 566 1686 | 519 255 4-Bit Decrementer pera | 4x5 | 20 | 1.828 565 1559] 458 236 16-Word x N-Bit Simul. |MMC1/Ji8x4xN] 108 | 2898 | 1.197 | 3.105] 1.258 407 Rd/Wr RAM MMEX | 18x2 Honeywell 8HONEYWELL/SS ELEKs MIL 03 eB) 45S1872 oooo244 o HC20000 4551872 HONEYWELL/SS ELEK. MIL O3E 00244 DD T-yQ-yj-—9g MACROCELL PERFORMANCE GUIDE (continued) (Tj = 25°C; Vag = 5.0V; Tin = 18; Process = Nominal) (Typical) Cot | Got] Coll | Base | LoadFactor | Base |Load Factor] Input Cell Description Name | size | count | Rising | Rising | Falling | Falling | Cap. (wxh) (ns) (nsipF) (ns) (nsipF) (pF) HC VO Cells* Clock Driver (Low Drive) |CLKA | — | — | 2760 oos | | 2.77 on 40 Clock Driver (High Drivey |CLKB | — | — | 1.770 0078 1.920 0081 5.50 2-Stage CMOS input (CTL) | CIN2 | — | — | 990 499 942 | “581 3.0 2-Stage TTL input (CTL) | CIN’ | — | — | 571 425 | 1.480 | ‘660 | 30 Unused input w/SCAN tooo | — | — | — a —| — |= Unused Input only w/SCAN too3** | — il 3.515 985 3.01 1.068 3.0 CMOS Inv. InputwiSCAN | It03"} — | — | ‘e13 400 881 475 | 30 wiinput SCAN Reg. 2-Stage CMOS Input Only, 1203 —_ —_— 4.050 967 3.743 1.005 3.0 wi SCAN 2-Stage TTL Input Only 1303 | — | — | 3057 930 3.937 1.060 3.0 wi SCAN Unused /0 Butter Bo00 | — | — | — — — — |— Unused /O B004**| — co 4.26 914 3.845 986 069 w/ SCAN CMOS Low Drive Output | 8014" — | — | 961 0953 ftss1 | 1120 | 40 w/ SCAN ‘CMOS Output B021 —_ _ 3.44 042 3.14 057 4.0 w/SCAN (CMOS High Drive Output | Boza*} — | — | 3.44 0423 3.140 0567 40 wi SCAN 5V TTL Output Buffer BO41 —_ _ 3.61 085 3.24 038 4.0 wi SCAN @mATTL Output posae} — | — | sato e790 | 3.060 | 0383 | 40 wi SCAN CMOS Invert Input Bios} — | — 813 400 881 AB 40 wi SCAN 2-Stage CMOS Input 8203 | — —_ 1.55 75 1.43 778 3.0 w/ SCAN 2-Stage CMOS Input B204**} — —_— 1.44 700 1.350 720 3.20 wi SCAN 2-Stage CMOS V0 peess| —_ | — | 244 sm | 22a | see | 40 wiSCAN 2-Stage TTL Input Boos | — | — 982 69 2.00 89 3.0 wiSCAN 2-Stage TTL Input 8304 | — _ 926 647 1.880 823 3.20 wiSCAN 2-Stage TTL Input (CMOS High Drive Out B324"*] — _ 2.183 344 251 4.39 4.0 wiSCAN 2-Stage TTL VO 344") —_— 2.296 383 2.62 464 40 w/ SCAN 2.030 41g | 2020 | 118 | 667 ‘SCAN Control Circuitry ecoz2 | — | — BIST Control Circuitry ccos | — _ 2.61 ANT 2.73 118 667 CMOS High Drive Output |coT2 | — | — | 2887 143 | 5.470 | ‘039 | 4.0 For Tesi-Data-Out ‘TTL Output For coT4 | — _ 2.843 071 5.023 033 4.0 Test-Data-Out “AITTTL outputs have 8mA dive capabilly. “For use with BIST (Buit-In Solf-Test) 9 HoneywellHC200bu 4551672 HONEYWELL/SS ELEK, MIL. CALCULATING PERFORMANCE Each macrocell has its own intrinsic base delay and load factor. Macrocell_ performance is influenced by temperature, voltage, and process variations. Intrinsic base delay is also a factor of the input edge rate. When calculating the propagation delay of a macrocell or logic path, temperature, voltage, process, input capacitance of the next macrocell, and capactive loading due to metal interconnect ‘must be considered. Tpa=[ To + (LFXC) + (EF x (No-1))] where, ‘Tp= Intrinsic base delay at 25°C, 5V, nominal process, ns LF = Load tactor for macrocell,ns/pF Cj = Total capacitive load = Cin + Cmetals PF EF = Element factor for control that macrocel, ns/element Ng = Number of elements attached to the control hat Example 1. ‘Assume a 2-input NAND gate, ND2, 25°C, 5V, nominal process, fanout = 2 identical 2-input NAND gates. From Macrocell Performance Guide, Cip = 0.128 pF. From Metal Load vs. Fanout, interconnect capacitance = 0.375 pF Tpd(Rising)=[ Tp + (LF xC))] = [0.276 + (0.983 x ((2x 0.128) + 0.375))] =0.896 ns Example 2. ‘Assume a 2:1 multiplexer with 4 elements (MXC2/MXE2), 25°C, SV, nominal process, fanout = 4 2-input NAND gates. EF = 0.05 From Macrocell Performance Guide, Cin= 0.119 pF. From Metal Load vs. Fanout, interconnect ‘capacitance = 0.592 pF (worst case) Tpd(Falling)}=[ Tp + (LF x Cj) + (EF x (Ne-1))] [1.091 + (9.496 x ( (4x 0.119) +.0.592)) + (0.05 (4-1))] 083 ns. HONEYUELL/SS ELEK, MIL 03 pe ussiaz2 ooooess 2 ff O3E 00245 DD T=4a-4)-09 Macrocells using a control hat and elements (e.g., DFC1, DFE) require an addtional load per element. In the following equation for calculating the propagation delay, Tpd, the input edge rate for the intrinsic base delay is ns. Best case/worst case delay values can be obtained trom Honeywell's CMOS Design Manual. METAL LOAD vs. FANOUT 12 ‘0 g Sos ios é a ‘C(metal) = (0.238) x (Fanout) 9-657 (Nominal) HoneywellHONEYWELL/SS ELEK. MIL 03 Dé| 4551872 HONEYWELL/SS ELEK, MIL POWER DISSIPATION Power dissipation of a CMOS circu is dificult to calculate because it is extremely dependent upon such conditions as switching frequency, load capacitance, supply voltage, inputtise orfalltime and temperature. Typically, power consumption of a CMOS gate array is comprised of array power and VO power. The array is dominated by AC power (CV2 4), which is controlled by the logic function (how heavily loaded each gate is and how fast they switch). Within the array, power is dissipated by two components: the clock and the rest of the array. The VO buffers are dominated by DC power (IV), although AC power is an important consideration. A first-order approximation of power dissipation can Array Power PL =GxP x £988 x Vdd225 x 0.23 x 109 in miliWatt, where equivalent gates (number of physical cells ussua7e oooo24e 4 Bf 03E 00246 HC20000 0 T-Ha-1)-0g — be made by summing array power (Pl), output butfer power (PE) and clock power PC) as follows: PT =(Pl+ PEn +PC) where x is the number of output butters. Maximum power dissipation should not exceed a level at which the junction temperature (Tj) will exceed 150°C. Tj=PTx TRja + Ta where TRja is thermal resistivity of the package from junction to ambient and Ta is ambient temperature for the condition of device cooled by free air. usedx 1.5). P = fraction of gates which switch, on the average, each clock cycle (0 (minimum time between data changes) PE(max) = Vddx2 (T x Cj+1__min( To, T4) x 103) in milliWatt, By ToT path characteristic impedance, inohms minimum of values in brackets wverage time signals at logic LO average time signalis at logic HI Forthe example above, min{T9,T4) = 4 = 0.4 Wels =) Note that the expression for this case is indicated as a maximum. Although itis theoretically possible to dissipate the maximum power, it is realistically not probable. Power dissipation for long lines that may contain more than one pulse ‘onthe line at one time is a complex function of duty cycle, line length and frequency. Clock Power PC = (30+ Cg + 0.26xL +5.24 xB) x 1088 x Vdd 225 x 10 Sin miliWatt, where: lock frequency, in MHz Vdd = Array supply voltage. Co = Totalclook bus capacitance composed of metal and macro clock pin capacitances, in pF. 1B Total number of clocked macros, e.g., DFC1 L_ = Total number of elements in stacked flip-flop macros, e.g., DFE1. Constants used in PC formula are derived from actual test results. Honeywell 12HONEYWELL/SS ELEK, MIL 03 Def 4: 4551872 HONEYWELL/SS ELEK. MIL DESIGN-FOR-TEST AND MAINTAINABILITY Design-for-Test and Maintalnabillty Today's designs offen carry demanding component and. system-level test and maintenance requirements. Honeywell provides support for a full range of Design-For- Test (OFT) techniques, intended to reduce design debug time, board and module casts, and field system down time.’ Built-in Self-Test reduces test costs and Improves system maintainability. Boundary Scan simplifies testing of board interconnects and_ provides excellent fault isolation. Serlal Scan generates high- fauit-coverage test patterns which simplify system and software checkout. Honeywell also offers automatic test rogram generation in the form of MIGHT™, and an automatic, deterministic test pattem generation system with RIGEL™, MIGHT™ The MIGHT™ system provides automatic test program. generation for Honeywell gate arrays. Test programs are automatically generated and formatted, simpliying a process that requires weeks of manual development ‘and expensive debug time on the tester. The shell and, menu approach allows rapid integration of new technologies, expands to any language driven ATE, and achieves a new standard in test quality control. RIGEL™ RIGEL™ js an automatic, deterministic single stuck-at fault test pattern generation system. it is based on an. enhanced D-algorithm. Fundamental to its use is the circuit implementation of Honeywell Scan Design (HSD), ‘a scan structured approach to design for test. The RIGEL™ test generation tools provide a greater than 98 percent fault coverage of permanent single stuck-at faults. BUILT-IN SCAN CIRCUITRY ‘The HC gate array supports synchronous scan design and boundary scan design testability methods. Serial Scan Design Designs which provide easy application of stimulus and easy measurement of responses are necessary to make circuits thoroughly testable. Honeywell's primary technique that supports this is called Synchronous Scan Design (SSD). SSD specifies that registers in the circuit have an abilily to also be reconfigured into a serial shift register (Figure 2). The serial chain is able to be loaded with test input and unloaded with test responses trom. the component edge. Honeywell's RIGEL™ automatic test generation tool can be used to build a test that is, Capable of detecting greater than 98% of all permanent 551872 coooeus 3 03€ oozae HC20000 0 Hallo single stuck-at type faults. These tests are applied and gathered using SSD. Boundary Scan Design The boundary scan method is also fully supported uitizing scan-compatible input, output, and VO butter macrocells. Figures 3 and 4 illustrate the scan circuitry associated with each input and each output butter, Hs bp oy oppo Ly a Ly oT Loy by ses FIGURE 2. 16-BIT D-REGISTER IN SERIAL ‘SCAN PATH 13 HoneywellHONEYWELL/SS ELEKs HC20000 4551672 HONEYWELL/SS ELEK, MIL row iis NIL 03 deff yss1872 ooo0249 o 03E 00249 0 T-4Q-!\-0g — ToARRAY wa) FIGURE 3. INPUT SCAN REGISTER he is Tamer Be “By ie Be FIGURE 4. OUTPUT SCAN REGISTER Built-In Self-Test respectively. if an VO buffer is selected, the circuitry contained in Figures 3 and 4 is tied together. Note that ‘each scan register is connected to the next register in such a way as to configure an input scan ring and an ‘output scan ring around the periphery of the array. Also note that logic can be done between registers by entering and leaving the array. With these options, the user can design logic for generating serial pseudo- random test patterns, and, by adding logic to the output ‘scan path, can generate a signature analysis result. The macrocelll library also includes the CCO02 cell, which contains the logic necessary to control the scan registers associated with the /O cells. ‘The Built-In Self-Test (BIST) testabilly protocols of the Department of Defense VHSIC Phase 2 program are fully supported via the use of Honeywell's Test Interface Unit (TiU),-Test and Maintenance Controller (TMC), and the Element Test and Maintenance Bus (ETM-bus). Honeywell's Test-bus Interface Unit (TIU) chip interfaces between the busses in the hierarchical test-bus structure shown below. This device is rapidly gaining acceptance as a DoD and industry standard. The TIU broadcasts and receives test control and data signals and acts as either a bus master or slave for the back-plane based VHSIC Test, and Maintenance bus (TM-bus). It supports dual TM- FIGURE 5. VHSIC TESTABI ILITY ARCHITECTURE Honeywell 144551872 HONEYWELL/SS ELEK. MIL ‘busses for increased fault tolerance. A microprocessor and memory interface increases the capabilities of the TIU as a TM-bus master or as the test interface on an application module. “The Joint Test Action Group (JTAG-) bus and the Element Test and Maintenance (ETM-) bus ports provide standard test and maintenance control at the chip level. Honeywell's TIU supports muttiple STAGIETM ports to handle large boards with up to 128 ATAG- or ETM-bus compatible components. The ETM-bus is a multidrop, synchronous bus that transfers bit-serial test and maintenance instructions and data between a master device and up to 32 slave elements on other chips in a module. The slave element is the on-chip TMC, a function block that controls the test and maintenance features such as chip initialization, serial scan, debug, and built-in self-test. Figure 5 lilustrates how the TIU and TMG are used in a testable VHSIC system to assure low cost field maintenance and ‘quick design debug. User configurable built-in self-test methodologies can also be implemented using the scan macrocells in the HC. macrocell library. ~~ HONEYUELL/SS ELEKs MIL 03 Def 4552872 oooo2so & If HC20000 03— 00250 D T-4} a.)-09— ADVANCED PACKAGING The HC array is available in advanced single and mut- array packages to reduce board and module space, quickly debug brassboard and prototype systems, and improve system reliablltly through reduction of ‘array junction temperatures. Leaded chip carriers (LOCC) and pin grid array (PGA) packages, available in open or proprietary tooling, are supported over the military temperature range for a varity of miitary and commercial applications Honeywell's advanced —MICROPAK.II™ — mult-array module provides packaging techniques for assembly of multiple HC series CMOS arrays and cache memory die into a single hermetically sealed ceramic module. MICROPAK-II™ mutti-array modules dramatically improve systems’ reliabilly, and reduce system volume and cost. Consult Honeywell for more details. ‘The HC20000 is available in a 256 LDCC and a 284 PGA Package. If more specific packaging information is needed, please contact your Honeywell representative, 15 HoneywellHONEYWELL/SS ELEKy MIL HC20000 03 ef) s5s38z2 ooocasa 2 &f 4551872 HONEYWELL/SS ELEK, MIL 03 00251 DB T-4R+1-09 — 284 PIN GRID ARRAY ‘THERMAL CHARACTERISTICS je prion [SSSTSTSOSSSOOOSOOOOR* SU Sera ee SSSEaESETS pesseeesssesssasessg pesseseseceseeeseses : Besssescscesseseessg 3 ee 3 sea 3 S38 : 3 ea : 3 333 i 3 eee i 3 238 2 838 : 8 288) oe 3 eer : e3 et 1 ow! ° Be Se ‘s'o02| o 200 400 600 800 1000 saesess | Sesess: ees Tene sae Hest: 7 Fg Oe 1.807) 256 LEADED CHIP CARRIER Honeywell 16HONEYWELL/SS ELEK, MIL 03 4551872 HONEYWELL/SS ELEK, MIL QUALIFICATION AND SCREENING ‘The HC20K array is qualified and soreened to thé most, advanced military or commercial standards. For military applications, the array will be generically qualified 10 MIL-M-88510/605 requirements. Program specific quaification data is available, at an ad charge, upon request from Honeywell. ussiav2 ooogese Oo ff HC20000 03€ 00252 Dv ~T-4a-Ii-0q — Figures 6 and 7 illustrate MIL-STD-883C Class B or modified Class S flows available, For advanced commercial CPU applications, the HC20K can be qualified to Honeywell's commercial specification orto customer-specitic qualification flows. FIGURE 7. MODIFIED MIL-STD-883C CLASS S PRODUCT FLOW 7 HoneywellHONEYUELL/SS ELEK, MIL 03 Def) 4551872 aooDes3 1 HC20Guu r 4551872 HONEYWELL/SS ELEK, MIL 03E o0z53 D T-4Qt-04 —— ABSOLUTE MAXIMUM RATINGS Parameter Description oe Units Min, Map Vad DC Supply Voltage 7.0 Vv Vi Input Voltage ves+03 [Vv 1 DC Input Current 400 HA To DC Output Current =10 40 mA Ta Operating Ambient Temperature 65 +125 °C Ts Storage Temperature 65 +150 °C Note: Stresses above those ised undor “Absolute Mavimum Ratings" may cause permanent damage tothe device, Thisis astress rating and functional epraton ofthe davic a these or any conston above those Inccatod in the operational sections ofthis pectieaton's notimplied. Exposure to absolute maximum raing condos lor extendod periods may llect device reliably DC CHARACTERISTICS Parameter Description aun co Units me it aa wax Tan | max Test Conditions y | Beeeeds tow Sanat Over Racommended Vy | Low Level Input Voltage 08 15 CPi y_ Becsfledas High Sera “i r 20 35 ‘Over Recommended in | High Love! Input Voltage Qrer co 04 V_ | Vag=45V, fo = 8mA Vo | Low Level Output Voltage 05 |v | Vag=45V, gy < HA c 24 V_| vag=45V, on=-4mA lon | High Level Output Voltage Ngo = vag= #50 lap WA $,©) | Low Level input Current -50 50. HA_| Min = 0-5V° lin @)__| High Level Input Current -20 -20 BA in = Vad" (@) |$-State Output ort ; . toa |i gakage Current Low 0 “50 HA | Vout = Ves 1... (@)_ | 3State Output Off Vout = Ved exh ®) | Leakage High coo os C tos (@) | Output Short Circuit Curent} -96 | -15 | -96 | -15 | mA | Vou =Vss © 3.0 3.0 [pe _[INPUTONLY Cin (| Input Capacitance B 40 40 | pF _| BIDIRECTIONAL Court) | Output Capacitance 40 40 | _pF_| BIDIRECTIONAL 0 ov 10%, {@) Ambient temperature range Tals -5°C to +125°C. {@)_ Curententering pin's dofinadas positive. Curretleaving a pinks defined as negative. For specying e most negative value ls the minimum and the most paiive valuo is the maximum. (8) Val fr Oy, and Cay, do notincue package capacitance. (6) Forlag testing, not more than one ouput should be shorted ata ime, nor for more than one second, “Includes pulldown device Honeywell 18