ENTITY circuito_logico_13 IS

PORT(

a,b,c,d, :IN BIT;

f3,f2,f3 :OUT BIT);

END Circuito_logico_13;

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ARCHITECTURE arch_cir_log_13 OF circuito_logico_13 IS

BEGIN

f1 <=(NOT a AND b AND NOT c AND NOT d) OR (a AND b AND NOT c AND NOT d);

f2 <=(NOT a AND b) OR (NOT a AND c AND d) OR (a AND NOT b AND NOT c);

f3 <=(NOT a AND NOT b) OR (NOT a AND NOT d) OR (NOT a AND NOT c);

END arch_cir_log_13;