Lab3

Design Compiler - Adder

Dr. Yu Cheng Fan
National Taipei University of Technology, Taipei, Taiwan
 Environment Setup
Copy File for Environment Setting
cd□~   Go to root

cp□/home/standard/Environment_Setup_File/synthesis_setup_for_18/synopsys_d
c.setup□.synopsys_dc.setup

□ ←Press Space 

Copy File for Synthesis
cp □‐r□/home/standard/electronic_circuit_102□.      

Don’t forgot this point

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Open Design Vision

Use commend
cd electronic_circuit_102/lab3
Then commend dv

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 Read file
1

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 Verilog code
module lab1(a,b,c,sel,z);
input [7:0] a,b,c;
input sel;
output reg [8:0] z;

always @(*) 
begin
if (sel) z = a + b; Synthesize if..else
else z = a + c; adder logic circuits
end
endmodule

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Synthesize Design
1

New Cell
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Report - Resources

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Press OK, Display Report

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Report – Timing Path

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2

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 Adder Architecture
1 2

Double Click 4
3

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 Report (1)
 Use “Design/Report Design Resource”
 Adder type(current implementation)=_______

 Use “Design/Report Area ＆ Timing/Report Timing”
 Area (total cell area)=______ μm2
 Timing (data arrival time)=______ ns

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 Set Timing Constraints
2
1
4
3
Choose
In/Output port

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 Report (2)
 After setting, “Design/Compile Design”  to synthesize 
design again.

 Use “Design/Report Design Resources” to see what type of 
adder is used?
 Adder type=________

 Use “Design/Report Area ＆ Timing/Report Timing”
 Area(total cell area)=______  μm2
 Timing(data arrival time)=______ ns
 Slack =_______  ns
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 Change Different DesignWare
 Change the type of adder, input commend 
“set_implementation cla r301”for .72.28
“set_implementation cla r300”for .72.42
 Recompile “Design/Compile Design”

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 Report (3)
 Use “Design/Report Design Resources” to see what 
type of adder is used?
 Adder type=______

 Use “Design/Report Area ＆ Timing/Report Timing”,
 Area:________ μm2
 Timing:______  (arrival) ns    
 Slack:________  (violated) ns

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 Comparison
 What the difference between the three types of adder?

Rpl: Ripple‐carry adder
Cla: Carry‐look ahead adder
Pparch: Parallel‐Prefix Adder Architecture

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 Different Conditions
 1. Repeat page 4‐page 10 (5 Times)
 2. In page 6, set different area, power, map conditions.
 3. Excel file (Adder type, Area, Power, Timing)

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Dr. Yu Cheng Fan National Taipei University of Technology Taipei, Taiwan 17