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GRAPHENE TRANSISTOR:-
GRAPHENE
Introduction:-
Graphene is a one-atom-thick planar sheet of sp2-bonded carbon atoms that are
densely packed in a honeycomb crystal lattice. It can be viewed as an atomic-scale chicken
wire made of carbon atoms and their bonds. The name comes from GRAPHITE + -
ENE; graphite itself consists of many graphene sheets stacked together. Carbon is one of the
most versatile chemical elements. Because it can form single, double and triple bonds, it
forms thousands of chemical compounds, and has numerous elemental structures, or
allotropes. The most common allotropes of carbon are diamond and graphite. Diamond
consists of carbon atoms single-bonded to four other carbon atoms producing a tetrahedral
crystal lattice. Its structure leads to its extreme hardness and thermal conductivity, but
diamond is a very poor electrical conductor. In contrast, graphite consists of stacked layers
of carbon sheets. Within an individual carbon sheet, known as graphene, the carbon atoms
are sp2 hybridized and form a planar hexagonal lattice. The sp 2 hybridization means that the
carbons are -bonded in the plane, but are also -bonded above and below the plane.
Graphene thus possesses one of the strongest bonds in nature and has a very high tensile
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strength. Graphene’s perpendicular p-orbitals lead to electron delocalization because there is
no distinction between neighboring bonds, as indicated in Figure below.
Fig. Aromatic hydrocarbons like benzene shown here, share electrons in the p-orbitals with
many neighboring atoms.
This conjugated orbital system permits the electrons to travel freely above and
below the plane of carbon atoms with minimal scattering. Because of the minimal scattering
and strong delocalization of the electrons, graphite is a good conductor along the plane.
However, in graphite, electrostatic forces bind the layers together only very weakly, and
graphite is a very soft mineral. In addition, the other layers interfere with the behavior of the
single sheets, even if not strongly. An ideal system would be to study free single-layer
graphene, but until a few years ago, two-dimensional systems like free graphene were
believed to be impossible.
In recent years, the two most familiar allotropes of carbon have been joined by a
number of newly discovered graphene-like materials. The first major graphene-related
substance discovered was C60, also known as buckminsterfullerene, buckyball, and fullerene,
a soccer-ball-like configuration of carbon atoms found in common lamp soot and known to
be very stable. Soon, the scientific community encountered similar fullerene-type carbon
structures called a carbon nanotubes. Carbon nanotubes are needle-like tubes of rolled up
graphene sheets that exhibit many unusual and useful properties such as extreme tensile
strength and high conductivity. .
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Discovery of Graphene
Fig. A representation of the rippling of 2D graphene into 3D. The red arrows are ~800nm
long.
But why is there such interest in graphene? Aside from the obvious interest in the
novelty of a two-dimensional crystal, graphene crystals exhibit unusual electrical properties
that may prove useful both theoretically and practically. In particular, graphene’s charge
carriers are very unusual in that they behave like massless Driac fermions and are most
effectively described by the Dirac equation rather than the non-relativistic Schrödinger
equation:
EN = [2ehc2 B(N+1/21/2)]1/2.
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Anomalous Quantum Hall Effect in Graphene
Graphene is an ideal
system for examining the quantum Hall effect for a number of reasons. First, graphene
samples are available in such purity that the charge carrier concentration can be tuned
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continuously from high concentrations of electrons to high concentrations of holes simply by
changing the gate voltage. Second, the purity of the graphene samples is so high that the
QHE can be observed even at room temperature, whereas most materials only exhibit the
QHE at much lower temperatures. Finally, graphene’s anomalous quantum Hall effect, by
being shifted by half compared to most systems, exhibits non-zero conductivity even as the
charge carriers change from electrons to holes (the neutrality point or the Dirac point). For
most materials, as the charge carrier concentration tends towards zero, so does the
conductivity, so that there is a metal to insulator transition at no temperatures. But graphene
has shown no signs of a metal-insulator transition even down to liquid helium temperatures.
Aside from the anomalous quantum Hall effect, one of the most exciting prospects for
graphene is that it may eventually prove useful in electronic applications. Graphene’s high
conductivity and its unusual electronic properties may lead to unexpected advances in
processor and electronic technologies. After carbon nanotubes have so far failed to
revolutionize the field, scientists are cautious in advertising the possible future applications of
graphene. For graphene, it is too early to tell whether graphene will significantly affect the
field of commercial electronics, but it’s small scale and unusual properties may contribute to
the development of nanoscopic electronic components or quantum computing. Graphene has
been used to produce a functional transistor even though this initial proof of concept
transistor leaks electrons and is highly inefficient.
Scientists acknowledge that graphene will be an important material in future
technologies. It might be used to store hydrogen in fuel cells or in batteries as electrodes. It
may serve a use in the production of ultra-thin fabrics that require great strength. If glues are
used between the graphene layers, it might be possible to assemble very strong materials. Its
chemistry can be controlled to change its electrical properties to be conducting, insulating or
semiconducting. It may even prove useful in the possible development of quantum
computing. Graphene’s immense potential is especially exciting considering how easy and
cheap it is to produce.
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Graphene transistor
Transistors less than one-quarter the size of the tiniest silicon ones - and potentially
more efficient - can be made using sheets of carbon just one-tenth of a nanometre thick,
research shows. Unlike other experimental nanoscopic transistors, the new components
require neither complex manufacturing nor cryogenic cooling. The transistors are made of
graphene, a sheet of carbon atoms in a flat honeycomb arrangement. Graphene makes
graphite when stacked in layers, and carbon nanotubes when rolled into a tube. Graphene
also conducts electricity faster than most materials since electrons can travel through in
straight lines between atoms without being scattered. This could ultimately mean faster, more
efficient electronic components that also require less power.
The first graphene transistor was demonstrated in 2004. But this leaked current and
could never switch it off, because electrons hopped too easily between the carbon atoms. We
have now made a graphene transistor that does not leak current that can control the flow of
just a single electron efficiently. The leak-free transistor is made from a "nano-ribbon" of
graphene less than 10 nanometres wide and just a single carbon atom thick (0.1 nm). The
device not only works at room temperature but, unlike other transistors of a similar size, it is
relatively simple to make. The ribbon at the heart of the device, as well as the surrounding
connections, can be cut from a graphene sheet using electron beam lithography - the same
method used to make silicon devices.
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Operation of Graphene Transistors at GHz Frequencies
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Fig. A Optical image of the device layout
Fig. B
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Fig. Measured output characteristics of the graphene transistor for various top-gate voltages
The dc electrical characteristics of the completed graphene device after the deposition
of the top-gate electrode are shown in Fig. The inset shows the measured current as a
function of (top-gate) voltage VG at a drain bias of VD = 100 mV. Despite the small on/off
ratio, the graphene devices are essentially ambipolar field-effect transistors, as indicated by
the "V"-shape gate dependence in the measured ID-VG curve. In these graphene field-effect
transistors (GFET), the transport is dominated by electrons and holes for positive and
negative gate voltages, respectively, and the conductance minimum is denoted as the Dirac
point where electrons and holes make equal contributions to the transport.
Fig. shows the n-type output characteristics, ID-VD, of the grapheme transistor at
various gate voltages. It is found that the top-gated GFETs studied here exhibit a nearly linear
ID-VD dependence up to 1.6 V for the gate voltage ranges measured. This lack of current
saturation is due to the fact that graphene is a zero-gap semiconductor. It has been suggested
that velocity saturation at higher biases may lead to the current saturation phenomenon in
graphene transistors. However, a higher carrier mobility may be required to achieve this
saturation velocity within the drain bias of practical interest.
The de-embedded S parameters constitute a complete set of coefficients to describe
intrinsic input and output behaviors of the graphene device, and can be used to derive other
important electrical properties such as gain.
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Fig. The current gain h21
In Fig. the de-embedded current gain h21 decreases with increasing frequency
following the 1/f slope expected for a conventional FET. In a regular FET, this 1/f frequency
dependence of h21, equivalent to a decay slope of -20dB/decade, results from the gate
impedance given by Z = 1/jωCG, where ω = 2πf and CG is the gate capacitance, that
decreases with increasing frequency. Therefore, the 1/f dependence of current gain obtained
in Fig. is significant because it not only validates the high-frequency measurements and the
de-embedding procedures used to extract the intrinsic GFET characteristics, but it also
suggests regular FET-like behaviors for graphene transistors as a function of frequency. One
of the important figures of merit for characterizing high-frequency transistors is the cut-off
frequency fT, defined as the frequency where the current gain becomes unity (h21 = 1). In
practice, for a transistor possessing the ideal -20dB/decade slope for h21, the cut-off
frequency fT is determined by the product of h21 and frequency, i.e. f × h21(f), over the
measured frequency range. Thus, for the device shown in Fig. 4, the cut-off frequency fT can
be determined by either approach to be ~ 4 GHz. The high-frequency operation of the
graphene transistor is found to be highly dependent on the dc bias condition. Fig. 5 shows the
measured cut-off frequency fT of the GFET as a function of gate voltage. At all gate voltages,
the de-embedded current gain h21 exhibits the 1/f frequency dependence similar to that
shown in Fig. so that the cut-off frequency can be reliably determined. The n-branch of the
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graphene transistor is shown here because of the higher transconductance for electrons than
for holes in this device.
These results show that the high-frequency behavior of these graphene transistors can
be described as an FET with a static, constant gate capacitance within a significant portion of
the bias range. In principle, the maximum cut-off frequency of an FET can be improved by
reducing the gate length. To investigate the length dependence of fT in graphene devices,
graphene transistors with various gate lengths down to 150 nm were fabricated and
investigated for their high-frequency operations.
All of the graphene devices studied here were prepared in one batch and on the same
chip in order to minimize the device-to-device variations introduced in the fabrication
processes. As before, mobility degradation was observed in all devices after ALD oxide
deposition. The maximum fT was found to increase with reduced gate lengths, as expected,
and for the 150-nmgate GFET, a peak cut-off frequency as high as 26 GHz was obtained, as
shown in Fig. 6. To the authors’ knowledge, this is the highest value measured for graphene
transistors to date.
In summary, top-gated graphene transistors of various gate lengths were fabricated
and their high-frequency response was directly characterized by standard S-parameter
measurements. The short-circuit current gain showed the ideal 1/f frequency dependence,
confirming the measurement quality and the FET-like behavior for graphene devices. As the
gate voltage is varied, the measured fT was found to be proportional to the dc
transconductance gm, following the relation fT = gm/(2π CG). Furthermore, fT was found to
increase with decreasing channel length, with the scaling dependence fT ~ 1/LG 2 for the
GFETs studied here. A peak cut-off frequency fT as high as 26 GHz was measured for a
150-nm-gate graphene transistor, establishing the state of the art for graphene transistors.
These results also indicate that if the high mobility of graphene can be preserved during the
device fabrication process, a cut-off frequency approaching THz may be achieved for
graphene FET with a gate length of just 50nm and carrier mobility of 2000 cm2/V⋅s.
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Graphene Nanoribbon Field-Effect Transistors
Since our GNRFETs were Schottky barrier (SB) type FETs where the current was
modulated by carrier tunnelling probability through SB at contacts, high work function metal
Pd was used to minimize the SB height for holes in p-type transistors. In fact we used Ti/Au
as contact and found that Pd did give higher Ion in device with similar dimensions. 10nm SiO 2
gate dielectrics was also important to achieve higher Ion because it significantly reduced SB
width at contacts compared to 300nm in previous work
For wide GNR devices, they all showed metallic behavior because of vanishingly
small bandgaps. Compared to sub-10nm GNRFETs with similar channel length, the current
density in wide GNR devices was usually higher (~3000μA/μm at Vds=1V for the device in.
We note that our wide GNRs showed relatively weak gate dependence in transfer
characteristics, likely due to interaction between layers. The Dirac point was usually not
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observed around zero gate bias, indicating p-doping effects at the edges or by physisorbed
species during the chemical treatment steps.
We next analyze how close the GNRFET operates to the ballistic performance limits
by comparing experiments with theoretical modelling. The theoretical model computes the
ballistic performance limits by assuming a single ballistic channel and ideal contacts
(sufficiently negative SBs).
Any subsequent edge scattering after OP/ZBP emission has a small direct effect on
the DC current because edge scattering is elastic and does not change the carrier energy. Such
a carrier rattles around in the channel and finally diffuses out of the drain. At high drain biases,
therefore, only elastic scattering near the beginning of the channel matters and the rest of the
channel essentially operates as a carrier absorber.
Our sub-10nm GNRFETs afford all-semiconducting nano-scale transistors that are
comparable in performance to small diameter carbon nanotube devices. GNRs are possible
candidates for future nano-electronics. Future work should focus on elucidating the atomic
structures of the edges of our GNRs and correlate with the performances of GNRFETs. The
integration of ultra thin high dielectrics and more aggressive channel length scaling is also
needed to achieve better electrostatics, higher Ion and ideal subthreshold slope.
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Fabrication Process of GNRFETs
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Tunable Graphene Single Electron Transistor
Fig. Schematic illustration of the tunable SET device with electrode assignment
Here we investigate a fully tunable single electron transistor (SET) that consists of a
width modulated grapheme structure exhibiting spatially separated transport gaps. SETs
consist of a conducting island connected by tunneling barriers to two conducting leads.
Electronic transport through the device can be blocked by Coulomb interaction for
temperatures and bias voltages lower than the characteristic energy required to add an
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electron to the island. The sample is fabricated based on single-layer grapheme flakes
obtained from mechanical exfoliation of bulk graphite. These flakes are deposited on a highly
doped silicon substrate with a 295 nm silicon oxide layer. Electron beam (e-beam)
lithography is used for patterning the isolated graphene flake by subsequent Ar/O2 reactive
ion etching. Finally, an additional e-beam and lift-off step is performed to pattern Ti/Au (2
nm/50 nm) electrodes.
TABLE I: Capacitances and lever arms of the different gate electrodes, including source and
drain contacts, with respect to the graphene island. Most values are independent from the
measurement regime, NN or NP. If there is a difference the NP value is given and the NN value
is put in brackets.
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Graphene field-effect transistors with Co contacts as source and drain electrodes show
anomalous distorted transfer characteristics. The anomaly appears only in short-channel
devices (shorter than approximately 3 μm) and originates from a contact-induced effect. Band
alteration of a graphene channel by the contacts is discussed as a possible mechanism for the
anomalous characteristics observed.
In order to construct such electronic devices, metallic materials should make a contact
with the grapheme layers. The effect of metal contacts can be detected using the structure of a
field-effect transistor (FET) and measuring the transfer characteristics (drain current, D I , vs.
gate voltage, G V , characteristics). For instance, the difference between the drain currents of
graphene FETs at exactly opposite charge densities (at the same carrier densities with
opposite charge polarities) has been explained by a metal-contact effect. Charge transfer from
metal to graphene leads to a p-p, n-n or p-n junction in graphene, depending on the polarity of
carriers in the bulk of the graphene sheet. An additional resistance arises as a result of the
density step created along the graphene channel, which causes asymmetry.
In this we analyse the effect of metal contacts on the transfer characteristics of
graphene FETs. In particular, the choice of metal and the gap between the metal contacts
(source and drain electrodes) have been examined by employing a FET structure. It was
found that graphene FETs with Co contacts and short channels display anomalous distorted
transfer characteristics, indicating that the anomaly originates from Co contacts.
Graphene layers were formed onto a highly-doped Si substrate with a 300 nm thick
thermal oxide layer using conventional mechanical exfoliation. The starting graphite crystal
used was Super Graphite from Kaneka Corporation. The thicknesses of the graphene layers
were determined to be approximately 1nm by atomic force microscopic observations in
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tapping mode. These layers were determined to be one-atom thick from the optical contrast.
Metal electrodes (Co and Au) were fabricated onto the grapheme layers by electron beam
lithography and liftoff techniques. For the Au electrodes, 5nm thick Cr was deposited as an
adhesive layer prior to Au deposition. The electrodes fabricated in this study had a total
thickness of 50nm. The FET characteristics were measured in low vacuum at room
temperature.
Fig. Transfer characteristics of a graphene FET with Cr/Au electrodes with channel length 1.5
μm.
Fig Transfer characteristics of a graphene FET with Co electrodes. The channel length was 2.0
μm
The transfer characteristics are shown in Figs. 1(b) and 1(c) for Cr/Au and Co
source/drain electrodes, respectively. Cr/Au is a conventionally used metallic material for
electronic devices, and Co is a popular material for spin-electronic devices as a source of
spinpolarized current. Although the graphene FET with Cr/Au contacts exhibits conventional
transfer characteristics, as widely reported previously, that with the Co contacts displays
anomalous distorted characteristics, especially in the negatively gated region.
The shorter channel results in lower channel resistance, and the resistance originating
from the contacts should have a more dominant effect on the two-terminal resistance. In fact,
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the resistances at the D I minima are not proportional to the ratio of channel length to channel
width, and thus the contact-related effects contribute to the device resistance.
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This describes the behavior of top gated transistors fabricated using carbon,
particularly epitaxial graphene on SiC, as the active material. In the past decade research has
identified carbon-based electronics as a possible alternative to silicon-based electronics. This
enthusiasm was spurred by high carbon nanotube carrier mobilities. However, nanotube
production, placement, and control are all serious issues. Graphene, a thin sheet of graphitic
carbon, can overcome some of these problems and therefore is a promising new electronic
material.
Although graphene devices have been built before, in this work we provide the first
demonstration and systematic evaluation of arrays of a large number of transistors entirely
produced using standard microelectronics methods. Graphene devices presented feature high-
k dielectric, mobilities up to 5000 cm2/Vs and, Ion/Ioff ratios of up to 7, and are
methodically analyzed to provide insight into the substrate properties. Typical of graphene,
these micron-scale devices have negligible band gaps and therefore large leakage currents.
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Fig. Preparation stages of the G/SiC substrate chips (4.5x3.5mm).
Prior to integration G/SiC chips were characterized using optical and AFM
measurements at MIT LL. It is important to note that SiC is not symmetric, the Si – C bond in
the [0001] direction has an asymmetry just due to the fact that one end is Si and the other is
C. Consider cleaving the SiC lattice by breaking that particular bond along the (0001) plane.
This cleave results in two interfaces, the silicon terminated surface is called the Si-face, and
the carbon terminated surface is called the C-face, figure
Fig. Crystal structure of SiC showing the two faces of the crystal cut along the (0001) plane.
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A typical SiC wafer will have a Si-face in the front with a [0001] normal, and a C-
face in the back with a [000-1] normal. During silicon sublimation graphene layers are
generated on both faces of the SiC wafer, however the film generated on the C-face has
different properties from the film generated on the Si-face.
Device integration:-
After characterization, G/SiC chips were mounted on 150-mm silicon carrier wafers
using epoxy bonding. This was done so that the silicon fabrication tools are able to process
the small chips. First, alignment marks were defined with standard g-line lithography and
etched into the G/SiC with a Cl2/He plasma etch. These marks are required because the
active MEG layer is too difficult to see optically for consistent alignment of subsequent
layers. Following the alignment mark etch, the resist was stripped in 80°C sulfuric acid; this
strip did not affect the appearance or resistivity of the MEG layer. Next, the active MEG
layer was patterned using a low energy O2 plasma etch. The source/drain layers were
deposited directly on the MEG film layer and consisted of 2 nm Ti and 20 nm of Pt, defined
using a lift off process. A 40 nm HfO2 layer was then deposited over the entire chip, using
thermal evaporation. The HfO2 film was verified to have a dielectric constant of 23 via a
capacitive measurement of a finished device. Finally, a 100 nm Al gate was deposited and
defined using lift-off. The AFM of a finished device is shown in Figure 5.
The mask pattern used in this experiment contained approximately 100 devices, with
different gate lengths, graphene widths, and alignment conditions. The nominal device was a
one with a source to drain spacing of 10 μm, a graphene width of 5 μm, and a 15 μm gate
overlapping the source and drain by 2.5 μm on each face. Hundreds of transistors where
fabricated, with functional yield as high as 95% for some samples.
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Figure 5: AFM scan of a finished nominal device
Although promising, graphene based electronics faces many obstacles before it can
become a competitive technology. Minimum conduction has to be decreased, device to
device variability has to be controlled, and a stable gate dielectric must be found. However
the chip level integration of hundreds of graphene devices on insulating SiC substrates is a
step towards making graphene technology possible. The main driver for a graphene
technology is clearly mobility. Even in this preliminary experiment mobilities up to 5000
cm2/Vs have been achieved. This is already 10 times better than silicon technology which
has had decades of optimization. It doesn’t seem unreasonable to expect that after thorough
investigation and process optimization, graphene devices will have mobilities over 10,000
cm2/Vs. The greatest obstacle to a graphene technology is the lack of a band-gap, and thus an
inability to turn off conduction below a certain level. It is likely that some method of
obtaining an on/off ratio for current in the hundreds will be demonstrated in the near future.
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CONCLUSION
Although promising, graphene based electronics faces many obstacles before it can
become a competitive technology. Minimum conduction has to be decreased, device to
device variability has to be controlled, and a stable gate dielectric must be found. However
the chip level integration of hundreds of graphene devices on insulating SiC substrates is a
step towards making graphene technology possible. The main driver for a graphene
technology is clearly mobility.
So, I thought to take my technical seminar onGraphene Transistor. I learn a lot of knowledge.
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BIBLIOGRAPHY
1. en.wikipedia.org/wiki/Graphene
2. www.ias.ac.in/currsci/may252007/1338.pdf
3. http://images.google.co.in/images
4. http://www.whereisdoc.com/
5. whatis.techtarget.com/definition/graphene-transistor.html
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