IEEE INDICON 2015 1570188397

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Novel design of cascaded multilevel inverter with
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reduced number of components
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Bhogeswara Rao Angara M.M.Tripathi
10   Department of Electrical Engineering Department of Electrical Engineering
11   Delhi Technological University (DTU) Delhi Technological University (DTU)
12   New Delhi-India New Delhi-India
13   bhogeswararaoangara@gmail.com mmtripathi@dce.ac.in
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16   Abstract— Multilevel inverters are of special importance in high Multilevel converters are being used for variety of
17   power and medium power applications. Reduced distortion, applications and also are commercially available in the
18   better output power quality, minimum switching losses, markets. The growing demand of these devices attracted
reduced switching stress make multilevel architecture preferred. researchers and industries. An in-depth study is being done on
19   This paper demonstrates a new topology of a 9-level and 15-level
20   various parameters of multilevel converter systems across the
inverters which requires less number of power switches and as
21   world. Researchers are trying to improve the performance of
well as DC voltage sources than that of existing conventional
22   multilevel inverters (MLI) which results in decreased cost of multilevel systems especially in terms of energy efficiency,
23   inverter, switching losses and design complexity. This paper power density, complexity, accuracy and reliability. Multilevel
24   presents simulation results of the inverter system at existing 7 inverters produce output voltage in the form of stepped.
25   level and proposed9 and 15 levels. The fast Fourier transform Despite various advantages discussed above multilevel
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(FFT) spectrums of the outputs of 9-level and 15-level inverters inverters have the disadvantages due to the design requires
are compared. The proposed topology requires same number of higher number of DC voltage sources and power switches.
27   switches and DC voltage sources to produce 11-level, 13-level and Major limitation on the design of cascaded MLI is the number
28   15-level outputs. Simulation results show that THD can be of power switches required. In this work we have proposed
29   decreased by using lesser number of switches.
one new topology based on H-bridge. This design also reduces
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the number of DC voltage sources, each DC voltage source
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Keywords—Multilevel Inverter, Total Harmonic Distortion, having unequal magnitudes of voltage. This model has been
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Fast Fourier Transform. designed for 9-level, 13-level as well as 15-level inverters. All
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the multilevel systems are simulated using MATLAB
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Simulink.
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36   I. INTRODUCTION
Section II presents the conventional multilevel cascaded
37   Multilevel Inverters are used in many applications such as un-
inverter structures. Section III presents the proposed new
38   interruptible power supply (UPS), Medium voltage Industrial
topology for multilevel inverters. Simulation and Results are
39   (induction motor) drives, ship propulsion Induction heating,
discussed in section IV and in section V conclusion is
40   high voltage direct current (HVDC) power transmission, grid
presented.
41   connected photovoltaic system ([1]-[2]), railway locomotives,
42   active filters, wind Energy System, and applications of power II. MULTILEVEL CASCADED INVERTERS
43   system for example flexible AC transmission (FACTS).Total
harmonic distortion (THD) [3] is an important parameter The cascade H-Bridge inverter is a H-Bridges connected in a
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associated with every inverter (including multi-level) and is series or cascade of H-Bridges [7]- [8]. The number of DC
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ideally desired to be almost zero. Multi-level cascaded inverter sources required to produce a (2n+1) output voltage levels in a
46   multilevel cascade inverter is given by the relation.
47   reduces the total harmonic distortion, switching stress on
48   devices, electromagnetic compatibility (EMC) and produce
49   high power ratings of the output current and voltage. As the 2 1 (1)
50   number of levels increases the output of the voltage is very
51   close to sinusoidal signal reduces harmonic distortion. Where ‘n’ represents the required number of DC sources and
52   Depending on the DC voltage source magnitude, the M is number of output voltage levels. Output voltage is given
multilevel cascade inverters are classified into two groups as the sum of voltages of each single phase H-bridge cell.
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54   such as Asymmetric design and symmetric design. In the
symmetric design [4]-[5], the DC voltage source magnitude is (2)
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equal for all single phase H-bridges and in asymmetric model Fig.1 illustrates the general structure of single phase
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[6] the magnitudes of DC source voltages are different for
57   cascaded multilevel H-bridge inverter. Each single phase H-
each single phase which contains H-bridges.
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61   978-1-4673-6540-6/15/$31.00 ©2015 IEEE
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bridge or full bridge contains separate DC source. A five level
cascaded multilevel inverter generates five output voltage
levels such as Vdc, 2Vdc, 0, - Vdc, - 2Vdc with two DC separate
voltage sources and a seven level cascaded multilevel inverter
produces seven output voltage levels as Vdc, 2Vdc, 3Vdc, 0, -
Vdc, - 2Vdc, - 3Vdc with three separate DC voltage sources.
From Fig.1 it shows that each single phase full bridge contains
four switches, S11, S12, S13, S14 are generates three output
voltage levels such as Vdc, 0, - Vdc. + Vdc. The cascade
multilevel inverters are scalable, good circuit layout due to Fig.2 Seven level inverter
series structure and switching redundancy feasible. Due to
availability of separate DC voltage sources these inverters are Table1: Switching scheme of 7-level inverter
restricted to certain applications.
Sr.No S1 S2 S3 S4 Sa Sb V0

1 1 0 0 1 0 1 V1

2 0 1 1 0 0 1 V2

3 1 0 1 0 0 1 (V1 + V2)
4 0 1 0 1 0 1 0
0 1 1 0 1 0 - V1
6 1 0 0 1 1 0 -V2
7 0 1 0 1 1 0 -(V1 + V2)

B. Proposed 9-level, 13-level and 15-level inverter

The 9-level, 13-level and 15-level inverters have been
designed from the 7-level inverter as shown in Fig.3 and Fig.4
Fig.1 general structure of cascaded multilevel inverter. respectively. The proposed 9-level inverter topology consists
of eight switches and three DC voltage sources. The 13-level
and 15-level inverter design comprises of Three DC voltage
III. PROPOSED TOPOLOGY
sources with different magnitudes and ten switches. The same
A. Seven level inverter topology design is generating 9-level, 11-lvel, 13-level and 15-level
The proposed topology is based on the modified H-bridge output voltages with different magnitudes of DC voltage
topology [9]. From conventional cascaded multilevel inverters sources. The number of output voltage levels and the
it is observed that the proposed topology reduces the number magnitudes of DC voltage sources are shown in Table 2 below
of DC voltage sources and also switches. In this work we and switching topology of 9-level and 15-level inverter is
proposed new topologies for 9-level, 11-level, 13-level and shown in Table 3 and Table 4 respectively.
15-level inverters. All these inverters are derived from a 7-
level inverter is presented. Figure.2 shows the 7-level inverter
with modified H-bridges. This structure consists of six power
switches and two unequal magnitudes of DC voltage sources.
Since if the values of DC voltage sources are same, reduces
the number of output voltage levels and hence to generate
more number of voltage levels the magnitudes of voltage
sources should be different values. The switching scheme of7-
level inverter is shown in Table 1. For this design the DC
voltage source magnitudes are given below

(3)
2 (4)

Fig.3Nine level inverter

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 Table 2: The magnitudes of DC voltage sources IV. SIMULATION MODEL AND RESULTS
Voltage source 9-level 11-level 13-level 15-level
The simulation is being done for the existing 7-level and
proposed topology for 9-level and 15 level inverters using
MATLAB Simulink and THD analysis also done using FFT
2 2 2 2
spectrum in simulink. The all inverters are designed for R-L
2 3 4 load with resistance and inductances are 70Ω and 60mH
respectively.
Table 3: Switching scheme of 9-level inverter
The developed topologies are unique and help in gradually
No. S1 S2 S3 S4 Sa Sb ST1 ST2 Output Voltage reducing number of switches and sources. It utilizes of three
asymmetrical DC voltage sources for generating 9,15 output
1 1 0 1 0 1 0 0 0 0
levels and the dc voltage sources are been arranged in the
2 1 0 0 1 0 1 1 0 V1 fashion such as 2n, 3n, 4n…..Increments in the DC, Where n
3 0 1 1 0 0 1 0 0 V2 represent the magnitude of lowest DC voltage source.
4 1 0 1 0 0 1 1 0 (V2+ V1)
Sinusoidal pulse width modulation method is used for
generating switching pulses with carrier frequency as 2.4
5 1 0 1 0 0 1 0 1 (V2 + V1 + V3)
KHz.
6 0 1 1 0 1 0 1 0 -V1
A. Existing 7-level inverter
7 1 0 0 1 1 0 0 0 -V2
The magnitudes of DC voltage sources are
8 0 1 0 1 1 0 1 0 -(V2+ V1) 30
9 0 1 0 1 1 0 0 1 -(V2 + V1 + V3)
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The simulation results and FFT analysis of output voltage
for 7-level inverter are shown in Fig.5 and Fig.6 respectively.

Fig.4 Proposed multilevel inverter (13 and 15 levels)

Fig.5 Output voltage for seven level inverter
Table4: Switching scheme of 15-level inverter
No S1 S2 S3 S4 Sa Sb ST1 ST2 ST3 ST4 Output Voltage
1 0 1 0 1 0 1 0 0 0 1 0
2 1 0 0 1 0 1 0 1 0 1 V1
3 0 1 1 0 0 1 0 0 0 0 V2
4 1 0 1 0 0 1 0 1 0 1 (V2+ V1)
5 1 0 0 1 0 1 1 0 1 0 V3
6 1 0 0 1 0 1 0 0 1 1 (V3+ V1)
7 1 0 1 0 0 1 1 0 1 0 (V2+ V3)
Fig.6 FFT spectrum of 7-level inverter for output voltage
8 1 0 1 0 0 1 0 0 1 1 (V2 + V1 + V3)
9 0 1 1 0 1 0 0 1 0 1 -V1 B. Proposed 9-level inverter
10 1 0 0 1 1 0 0 0 0 0 -V2 The Simulink model for 9-level inverter is shown in Fig.7 and
11 0 1 0 1 1 0 0 1 0 1 -(V2+ V1)
the design parameters for 9-level inverter are given below
12 0 1 1 0 1 0 1 0 1 0 -V3
30
13 0 1 1 0 1 0 0 0 1 1 -(V3 + V1)
14 0 1 0 1 1 0 1 0 1 0 -(V2 + V3)
60
15 0 1 0 1 1 0 0 0 1 1 -(V2 + V1 + V3) 30

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 Fig.10Proposed multilevel inverter (11, 13 and 15-level) Simulink model

C. Proposed 15-level inverter

The DC voltage source magnitudes for 15-level inverter are
given below and the simulation results, FFT analysis of
Fig.7 Matlab Simulink model for 9-level inverter
current and voltage for 15-level inverter are shown in Fig.11,
The simulation results and FFT analysis of output voltage for Fig.12.
9-level inverter are shown in Fig.8 and Fig.9 respectively.
15
30
60

Fig.8 Output voltage and current of 9-level inverter.

Fig.11The output voltage and current of 15-level inverter

Fig.9 FFT spectrum of 9-level inverter for output voltage

The Simulink model for 11-level, 13-leveland 15-levelinverter

is shown in Fig.10.
Fig.12 FFT spectrum of 15-level inverter for output voltage

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THD values of voltage for7-level, 9-level and 15-level V. CONCLUSION
Inverters are shown in below Table 5. The proposed 9-level and 15-level inverters were designed
and simulated using MATLAB Simulink. The proposed
Table 5:THD of 7-level, 9-level and 15- level Inverters
inverters were compared with conventional cascaded inverters
THDv(%)
Level for number of power electronic components. From the
comparison it has been found that the proposed inverter design
7-level 11.86 requires lesser number of switches and DC voltage sources
and also its performance is better than conventional design.
9-level 10.13

15-level 8.18 REFERENCES

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Fig.13 Conventional MLI versus Proposed MLI