A Study of Thermal Performance for Chip-in-Substrate Package

on Package
Tuan-Yu Hung, Ming-Chih Yew, Chan-Yen Chou., and Kuo-Ning Chiang
Advanced Microsystem Packaging and Nano-Mechanics Research Lab., Department of Power Mechanical
Engineering, National Tsing Hua University, HsinChu, Taiwan 30013, R.O.C.

Phone: 886-3-5742925, Fax: 886-3-5745377 and E-mail: knchiang@pme.nthu.edu.tw

Abstract

The three-dimensional package (3D package) is one of the popular designs for high-density packages. The chip-
in-substrate (CiS)-type structure is one of the popular manners in 3D package because of the resulting
improvement in package-stacking ability. To study its thermal performance, the finite element (FE) analysis is
applied in this study. The designed dummy solder bumps and relatively better power arrangement conditions are
proposed to improve the thermal performance of the package. The dummy solder bumps under the chip can
improve the efficiency of heat dissipation from the chip to the printed circuit board (PCB). Moreover, the highest
power dissipation is suggested to be placed at the lower chip. Thus, the thermal performance of the CiS
packaging technology can be further enhanced, and it is suitable for applications on high-power IC devices.

Key words: 3D package, thermal performance, CiS packaging technology, FE analysis

designs for the high density packages. Moreover, the

Introduction
Among the important factors for packaging
technology are the intergral circuit (IC) package cost,
the drop performance of the paclage, the reliability
of the paclage, and the thermal performance of the
package. Nowadays, the subject of thermal
management for the package is consistently
becoming critical because the density of the package
and the I/O on each chip increase progressively.
There has been a proliferation of studies on the
subject. In 2000 an article was published by Kim et
al. [1] that provides extensive discussions on the
thermal performance of thin quad flat j-forming
(TQFJ). Kim’s study utilizes the FLOTHERM
simulation and thermal measurement. The results
show that the maximum junction temperature rises
noticeably as the stacking number of packages
increases. In 2003, Chen et al. [2] proposed an
effective methodology that integrates an infrared (IR)
thermpgraphy measurement and finite element (FE)
model for thermal characterization of packages. The
thin qual flat package (TQFP) is the test vehicle in
Chen’s study, and the melodology is benchmarked
by a thermal test die measurement. Chen et al. [3]
and Chang et al. [4] used the FE method to discuss
the thermal performance of the flip chip-plastic ball
gird array (FC-PBGA) and the quad flat non-leaded
(QFN) package, respectively. Nowadays, computer-
aided engineering (CAE) methodology is being
utilized to improve the efficiency of packaging
technology.
Because of the improvement of IC
manufacturing process and the demand of system
integration, 3D package is one of the popular
thermal management for high density packages has
also become critical. In this study, a packaging
technology wich retans the advantage of 3D package,
chip-in-substrate (CiS) type structure, is purposed to
develop the packaging capability of signal fan-out
for the fin-pitched IC and the improvement of
stacking ability for packaging. Besides, it also looks
for the better thermal dissipation performance by
designed dummy ball under the chip. Figure 1 shows
the schematic structure of CiS packaging technology.
In the CiS packaging technologe, the chp is placed
in the substrate’s designed opening after wafer
dicing. The filler material is selected to fill the
trench between chip and substrate and to provide the
smooth surface for the redistribution line. The
interconnecting through hole inside the substrate is
defined toconect the signal between two sides of
substrate. The solder bumps can be located on both
the chip and the substrate surface, and the pitch of
the chip is faned out. Furthermore, there are singnal
pads connected by the interconnecting through hole
in both sides of the substrate. Therefore, the
packaging technology of package-on-package (PoP)
can be achieved.
Figure 1: The schematic structure of CiS
Packaging technology
 A number of studies [5] have investigated the
thermo-mechanical behavior of designed packaging
which uses the solft material around the chip. The
studies indicate theat the thermo-mechanical
behavior of the packaging is different from that of
conventional wafer level package (WLP) because of
the designed packaging structure. The soft filler and
lamination material can offer a stress buffer layer for
solder joints. Therefore, the solder joint reliability of
the designed structure is prominent. Moreover, the
accumulated stress/strain from the coefficient of
thermal expansion (CTE) mismatch at rhe metal
trance can be efficiently released through a proper
layout technology. The purpose of this study is to
investigate the thermal performance of CiS
packaging, which also applies solft material around
the chip. The route of heat dissipation is observed by
the three-dimensional FE analysis. On the other
hand, the thermal management of stacking chip-in-
substrate package on package (CiSPOP) is also
dicussed. Likewise, the effects of dominate design
parameters in CiSPOP technology are extracted.
Based on the numerical analysis, the thermal
characteristic of designed 3D packaging techmique
is discussed herein.
FE modeling and Thermal Properties
Determination
Figure 2 shows the established FE model
which refers to the CiS packaging technology.
Meanwhile, the quarter model contains the silicon
chip, the filler material, the lamination material, the
solder bumps, copper pad, through hole, the solder
mask, and the standard thermal test board [6].
Besides, the model includes 7 solder bumps. The
chip is embedded by the CiS technology, and the
package is mounted on the test board. The chip size
of CiS package is 3.75mm × 3.6mm × 0.15mm. The
external diamension after packaging is 9.6mm ×
7.2mm × 0.252mm, and the pitch of solder bumps is
0.8mm. Moreover, the diamension of
95.5Sn/3.8Ag/0.7Cu lead-free solder bumps is
0.34mm.
transfer coefficient is a nonlinear function of exterior
surface temperature applied to natural and forced
convection regime and includes the contribution of
radiation. The total heat transfer coefficient, hT , is
calculated from the following equation [3, 7].
1
(
3
hT = hNC 3
+ hFC ) 3
+ hrad (1)
n
⎛ T −T ⎞
hNC = a ⎜ s amb ⎟ (2)
⎝ Lch ⎠
hFC = 3.79 V
LFC (3)
hRAD = εσ ⎡⎣(Ts + Tamb ) Ts2 + Tamb
2
⎤
⎦ ( ) (4)
where Ts and Tamb are the external surface
temperature of the package and the ambient
temperature, respectively, ε is emissivity, σ is the
Stefan-Boltzman constant, and the Lch is
characteristic length. The emissivity of the package
device is set at 0.9. For horizontal plates,
Lch = 0.5WL / (W + L ) , where W and L are the width
and length of the plate, respectively. For vertical
plates, Lch = H , where H is vertical hight of the
plate. Furthermore, the constant a and n are given
as a = 0.83 and n = 0.33 for a horizontal plate
facing upward, a = 0.415 and n = 0.33 for a
horizontal plate facing downward, and a = 1.09 and
n = 0.35 for a vertical plate. In the forced
convection regime (Eq. 3), V describes the free-
flow air velocity. LFC is the characteristic length
(given as equal to the package length).
According to the JEDEC standard [6], the test
board is a four-layer printed circuit board (PCB) in
which copper-patterns are printed in both of the
surfaces. The effective thermal conductivity of the
test board can be calculated by the following
equation [8]:

N N

∑ k ×t i i ∑t i
kin− plane = i =0
N
, kcross − plane = i =0
N (5, 6)
ti
∑ ti
i =0
∑
i = 0 ki

where ti and ki are the thickness and thermal

Figure 2: The established three-dimensional finite conductivity of each layer, respectively. Besides, the
element model for thermal characterization of applied thermal material properties in FE analysis
CiS packaging technology are listed in Table 1.

In the FE analysis, the boundary consisting of

heat transfer coefficient are applied to the top and
bottom of the package, the top and bottom of the test
board, the side wall of the package and the test board,
and the side wall of the solder bumps. The heat
Table 1: Material properties applied in FE model
Material Thermal Conductivity
K (W/m℃)
Filler 0.2
Cu trace & pad 380
Chip 150
Substrate 0.34
Lamination 0.2
Solder mask 0.2
SAC387 solder 57
PCB (x, y/ z) (x, y/ z)=(22.8/ 0.34)
FE analytic results and discussion of CiS package
Through the established FE model of CiS
package, the numerical analysis is initially executed
as the power dissipation is 0.5W. The ambient
temperature is set at 25℃, and the predicted stable
temperature distribution is shown in Figure 3. The
results show that the junction temperature under
natural convection is 59.9℃.
(a) (b)
Figure 3: Thermal performance analysis of the
CiS packaging technology. (a) predicted
temperature distribution; (b) temperature
distribution on package (natural convection,
power dissipation = 0.5W)
As the substrate and filler with worse thermal
conductivity are around the chip, the generated
power can not be dissipated by these materials. For
this reason, the dummy solder bumps are suggested
to be placed under the chip as shown in figure 4.
Because the dummy solder bumps in the chip region
provide a better route of heat dissipation in the CiS
package (as shown in figure 5(b)), the junction
temperature could be reduced effectively (59.9℃ to
47℃).
Figure 4: The established finite element model
of CiS Packaging technology with dummy
solder bumps
Traditionally, the thermal performance of a
given package is described by the junction-to-
ambient thermal resistance, θ ja , defined bellow:
Tj − Tamb
θ ja = (7)
P
where T j and Tamb are the junction and ambient
temperature, respectively, and P is the power
dissipation at the given chip. In this study, the
calculated thermal resistance of the CiS package
structure and CiS package structure with dummy
solder bumps are 69.8℃/W and 44℃/W
respectively.
(a) (b)
Figure 5: Thermal performance analysis of the CiS
packaging technology with dummy solder bumps.
(a) predicted temperature distribution on package;
(b) temperature distribution on printed circuit
board (natural convection, power dissipation =
0.5W)
In CiS packaging technology, the filler
material is selected to fill the trench between chip
and substrate. Moreover, the lamination provides the
electrical insulation for the redistribution line. These
substances have relative poor thermal conductivity
(K), and their effects are studied by FE analysis.
Figure 6(a) shows the presicted packaging thermal
resistance as the thermal conductivity of the filler is
adjusted. The results show that the thermal
resistance reduces by 32％ as the K of filler modies
from 0.2 to 100 (W/m℃ ). Besides, the effective
thermal conductivity of lamination layer consisting
of dielectric and metal lines is calculated by Eq. (5,
6). The ratio of metal/laminatin can affect the
effective thermal conductivity of lamination layer
directly. Figure 6(b) shows the 35％ improvement of
thermal performance as the metal ratio increases
from 20％ to 80％. When the lamination has larger
thermal conductivity, the heat dissipated through
solder bumps is much easier.
(b)
(a)
Figure 6: Thermal conductivity effect of materials
in the CiS packaging technology. (a) filler material;
(b) metal/lamination layer
CiS packaging technology may contain
different sizes of the chips. As the size of the
embedded chip decreases, the number of the solder
bump under it reduces. In this study, the effect of
chip/package ratio in the CiS packaging technology
is also discussed. Different sizes of chips with the
same powe dissipation, i.e. 0.5W, are analyzed.
Figure 7 shows that the thermal resistance reduces
by 46％ as the ratio of chip/package size changes
from 20 ％ to 52 ％ . The larger chip size which
contains 4 solder bumps could provide effective
thermal channeals from the package to the PCB and
have relatively smaller power dissipation.
Figure 7: Thermal resistance value under
differet (chip size/ package size) ratios
FE analytic results and discussion of CiSPOP
After the numerical analysis of CiS
packaging technology, the stacking CiS packaging
technology, CiSPOP, is also investigated. Figure 8
shows the established FE model which refers to the
CiS packaging technology. In this model, the
designed dummy solder bumps are applied under the
chips as shown in figure 9. The quarter model
contains 10 solder bumps under chip No.1; 14 solder
bumps and one-half solder bump under chip No.2,
and 14 solder bumps and one-half solder bump
under chip No.3. The size of the chip No.1, No.2,
and No.3 of CiSPOP are 3.75mm × 3.6mm ×
0.15mm, 7.2mm × 4.8mm × 0.15mm, and 7.2mm ×
4.8mm × 0.15mm respectively. The external
diamension after packaging is 9.6mm × 7.2mm ×
1.062mm, and the pitch of solder bumps is 0.8mm.
Figure 8: The established three-dimensional finite
element model for thermal characterization of
CiSPOP packaging technology
Figure 9: The established finite element model
of CiSPOP with dummy solder bumps
Through the established FE model of
CiSPOP, the numerical analysis is executed as the
power dissipation is 0.5W at every chip. The
ambient temperature is set at 25℃, and the predicted
stable temperature distribution is shown in Figure 10.
The results show that the junction temperature under
natural convection is 76.7℃. The junction
temperature occurs at the chip No.3. As the filler
with worse thermal conductivity is placed over the
CiS package, the generated power can not be
dissipated from the upper CiS package to the lower
one efficiently. In another words, the upper CiS
package has worse ability of heat dissipation. For
this reason, the underfill is suggested to be placed
between the CiS packages as shown in figure 11.
Because the underfill between the CiS packages
provide a better route of heat dissipation from the
upper CiS package to the lower one (as shown in
figure 12), the junction temperature could be
reduced effectively (76.7℃ to 69℃). Moreover, the
thermal resistance could also be improved from
103.4℃/W to 88℃/W.
(a)
(b)
Figure 10: Thermal performance analysis of the
CiSPOP packaging technology. (a) predicted
temperature distribution; (b) temperature
distribution on package (natural convection, total
power dissipation = 0.5 × 3 = 1.5W)
Figure 11: The established finite element model
of CiSPOP with Underfill (thermal conductivity
of underfill = 2 W/m℃)
Figure 12: Predicted temperature distribution of
the CiSPOP packaging technology with underfill.
(natural convection, total power dissipation = 0.5 ×
3 = 1.5W)
CiSPOP packaging technology may contain
different power dissipations at the given chips. In
this study, the effect of power dissipation is also
discussed. Different power dissipations of chips with
the same total powe dissipation, i.e. 1.5W, are
analyzed. There are three arrangement conditions of
power dissipations: 0.75W/ 0.375W/ 0.375W, 1W/
0.25 W/ 0.25 W, and 1.25W/ 0.125 W/ 0.125 W.
Figure 13 shows the thermal resistance value under
different power dissipations. The X-axis indicates
the position of the highest power dissipation. As the
lower CiS package has better ability of heat
dissipation, the highest power dissipation is
suggested to be placed at the chip No.1 (black and
red lines). However, the chip No.1 with a small size
has a larger power dissipation density. When the
excessively high powe dissipation is placed at the
chip No.1, the extremely high junction temperature
may be occurred (green line). On the other hand,
thermal performance under forced convection is also
comparded in figure 14. The further improvement of
thermal performance can be achieved through the air
flow effect.
Figure 13: Thermal resistance value under
differet arrangements of power dissipations
Figure 14: Air flow velocity effect in the
CiSPOP packaging technology
Conclusion
The design concepts of the POP using CiS
manner can be applied to the high-density IC
devices. In the CiS packaging technology, I/Os with
small pitch can be expanded through the lamination
layers on the designed filler material and substrate
material. In this study, the designed dummy solder
bumps and the relatively better condition of the
power arrangement are proposed to improve the
thermal performance of the package. Based on the
simulation results, the dummy solder bumps under
the chip can improve the heat dissipation from the
chip to the PCB efficiently. As the thermal
comductivity of the filler and the lamination increase,
the thermal performance can be improved. In the
investigation of CiSPOP packaging technology, the
highest power dissipation is suggested to be placed
at the lower chip. Besides, the underfill between CiS
package can effectively conduct the accumulated
heat from the upper package to the PCB. Therefore,
the thermal performance of the CiSPOP can be
further enhanced, and it is suitable for applications
on high power IC devices.
Acknowledgements
.
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