library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity ripple_using_fulladder_16bec1046 is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

b : in STD_LOGIC_VECTOR (3 downto 0);

c : in STD_LOGIC;

sum : inout STD_LOGIC_VECTOR (3 downto 0);

cout : out STD_LOGIC);

end ripple_using_fulladder_16bec1046;

architecture Behavioral of ripple_using_fulladder_16bec1046 is

component fulladder
port(a : in STD_LOGIC;

b : in STD_LOGIC;

c : in STD_LOGIC;

sum :inout STD_LOGIC;

cout: out STD_LOGIC);

END COMPONENT;

signal C0,C1,C2:STD_LOGIC;

begin

F1:fulladder port map(a(0),b(0),c,sum(0),C0);

F2:fulladder port map(a(1),b(1),C0,sum(1),C1);

F3:fulladder port map(a(2),b(2),C1,sum(2),C2);

F4:fulladder port map(a(3),b(3),C2,sum(3),cout);

end Behavioral;

code for full adder

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity fulladder is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : in STD_LOGIC;

sum : out STD_LOGIC;

cout : out STD_LOGIC);

end fulladder;

architecture Behavioral of fulladder is

signal p,q,r:STD_LOGIC;

begin

sum<= a xor b xor c;

p<= a and b;

q<= b and c ;

r<= a and c;

cout <= p or q or r;