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    Digital system design

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    20 views3 pages

    Digital System Design 2017

    Uploaded by

    Sachin
    Digital system design

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
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    Brs-wv—o417-0632 Ree [TT TT 7 | | | A B.Tech. Degree IV Semester Examination April 2017 EC 15-1406 DIGITAL SYSTEM DESIGN (2015 Scheme) ‘Maximum Marks: 60 PART A. (Answer ALL questions) (10 x2=20) 1. (@)_ A ROM isto be used to implement the following circuit: Eight 1-bit inputs - x7, x6, x5,x4, x3, x2, x1, x0 Three I-bit outputs - 22,z1,20 z2=1 when there is an odd number of 1's in the set of inputs {x7,x6,x5}; and 0 otherwise. z1=1 when there is an odd number of I's in the set of inputs {x3,x2,x1}; and 0 otherwise. 20=1 when there is an odd number of 1’s in the set of inputs {x4,x2,x0}; and 0 otherwise. How many memory locations, address bits, data bits will be there for the minimal size ROM memory required to implement this circuit? What will be contents in the memory location if the inputs are (x7,x6,x5,4,x3,x2, x1, x0) = 01111001? (b) Implement the following circuit using 8:1 multiplexer. G i (©) A digital module receives a 4 bit number (x3,x2,x1,x0) and returns a binary output Y. ‘The output Y becomes ‘1’ only when input takes a decimal value (0 to 9). Write the high level expression and the switching expression of the module. (d) The state diagram describes a 2-input (x1, x0), I-output (Z) sequential circuit, Assuming that the initial state is “A”, write the sequence of states and outputs attained by the circuit when the input pattern shown in table is received. Draw the state table too. x1, x0 {01, 10, 11}: ze 31, x0 = (0 Cy x, 50 1 eo Zeal bt fb xi: 00 0 x0: 0 1,10 (©) Covert the above Mealy machine to its equivalent Moore machine (0) Givea state description for a sequential decoder for the following code a=0, b=1, c=20, d=21, e=220, f =221, g=222 (@) Using Mod 16 counter module design a counter that counts 8-9-10-11-12-13-14-15-0- I- 2.8. (h) A digital sequential circuit with one bit input and one bit output generates an output ‘1° whenever the input value is same as that of the previous input value, x(t)=x(r—1) Design using D flip flop. (i) Draw the FPGA digital design cycle. (Mark the statements conceming FPGA which are true. (i) FPGA consist of a set of basic blocks and interconnections layers that can be customized. (ii) The customization (programming, configuration) process of the basic blocks and the interconnections of a FPGA can be performed in the designer's laboratory. (iii) The advantages of FPGA is that this customization process is faster and less expensive. (iv) FPGA are particularly suitable for the implementation of prototypes. PART B (4 «10 =40) UL (a) Implement using: (5) (i) A suitable decoder and OR gate. (ii) A suitable PLA. P a- R (b) Differentiate between simple shifter, p-shifter and barrel shifter. (6) OR tL A two bit comparator has two 2-bit numbers A and B (4=al a0;B=61b0) — (10) and three outputs G (greater than), E (equal to) and L (less than) so that: G=lifA>B E=lif 4=B L=1 if A8,¢,=1if a,=8, andl, =lif a,

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